JPS61193593A - Time switching circuit - Google Patents

Abstract

PURPOSE:To realize multi-distributing function by variable-specifying a channel memory address which writes respective time slots data on an incoming highway together with a channel address memory which reads data to respective time slot on an outgoing highway. CONSTITUTION:For an incoming highway 101 data, only bits specified by a lead 103 are written with respect to an SPM 1 address specified by a lead 104. On the other hand, an RSCM 5 stores the encoded information, which is encoded from an SPM 1 concerning to an outcoming highway 102, corresponding to the time slot of an outcoming highway 102, while an RCNT 4 supplies discrete values synchronized with the time slot number of the outgoing highway 102 to the RSCM 5 and an ASEl 7. An AGEN 6 generates the slot number of dial tone, talkie and no call pattern as a reading address to supply it to the ASEL 7. The ASEL 7 selects either an output lead 109 or an output lead 113 according to I/O corresponding relation and supplies it as an reading address to the SPM 1. Thus this can provides a time switching circuit having high functionality, economical merits and wide application fields.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a time switch circuit in a time division exchange.

[Prior art]

Various time-division switching systems are currently in use, and these communication paths are constructed using time switch circuits. These conventional time switch circuits are, for example, [D70
As shown in [I], P, 154-P, 163 J, there is a random write sequential read type consisting of a communication path memory, a write address holding memory, a read address generation counter, and ■ a communication path memory. , a sequential write/random read type consisting of a read address holding memory, and a write address generation counter.

Among these, conventional examples of the random write sequential read type time switch (2) include, for example, the multiple exchange time switch circuit shown in "IEICE technical report, IN33-8J," or the rERIcssONREVIEW
There is a secondary time switch circuit of the T-8-T time division switch shown in Nl14 1983, P, 140-P, 149 J. In the former case, a time switch circuit capable of multiple exchange was realized by using the fact that a random write time switch can write to the same address multiple times within one frame period. In the latter case, by configuring the secondary time switch in a random writing type, and by using a holding memory that serves both the holding memory of the space switch and the holding memory of the secondary time switch, an economically advantageous time division switch can be achieved. realized.

On the other hand, as shown in the above-mentioned DTQ type automatic switching system [I], there are applications in which time switches are required to have multi-distribution functions such as tone and talkie. Since this cannot be achieved with a switch, a sequential write/random read type time switch has generally been used in such application cage blinds.

In this way, conventional random write time switches have excellent features in terms of function and economy, but
Since the multi-distribution function cannot be realized, there is a problem that it can only be applied to limited applications.

[Purpose of the invention]

An object of the present invention is to provide a time switch circuit that realizes a multi-distribution function under a random write type.

[Summary of the invention]

The present invention makes it possible to variably specify the address of the communication path memory for writing data of each time slot on the incoming highway, and to variably specify the address of the communication path memory for reading data into each time slot on the outgoing highway. It is something that

[Embodiments of the invention]

FIG. 1 shows an embodiment of the time switch circuit of the present invention.

The time switch circuit has 1 channel memory (SPM) that can be selectively written into 8 bits and 16 words, and 4 bits for writing.
Bit counter (WCNT) 2.12 bits) 16-word write address holding memory (WSCM) 3, 4-bit counter for reading (RCNT) (This functions as a kind of sequential address reading circuit) 4.2 A 16-bit read address holding memory (180M) 5, an address generation circuit (AGEN) 6 that generates an SPM address to be multi-distributed, a read address 105 to be supplied to the SPM as a sequential address 109 or a multi-distribution address 113, a read address selection circuit (ASEL) 7 determines which one is to be used.

FIG. 2 is a waveform diagram of each part, and FIGS. 3 and 4 are input/output truth tables of the address generation circuit 6 and read address selection circuit 7 in FIG. 2, respectively. In FIG. 2, the arrows indicate dial tone time slots, the % arrows indicate talky time slots, and the horizontal arrows indicate no-call gloss turn time slots. Third
In the figure, the mark 'x' indicates that either '1' or %01 is acceptable.

In Figure 1, incoming highway 101 and outgoing highway 102
For example, a 16 time slot TSO with 8 pits ~
1024Kb/TS16 multiplexed at 8KHz cycle
It is the highway of s. T S of the entrance highway 13.
14 and 15 are assigned to each dial tone and talkie-1 no-call gloss turn. That is, input highway 10
1. The frame period of the exit highway 102 is 8KHz,
One frame carries signals consisting of 16 slots, and each slot consists of 8 bits.

WSCM3, regarding the data of input highway 101,
Write addresses to the SPMI and bit positions to be written are stored in correspondence with time slots of the input highway 101.

The WCNT2 sends a count value synchronized with the time slot number of the human highway 101 to the address line 108,
Determine the read address of WSCM3. The read result is sent to the address line 104 as the SPMI write address.
is simultaneously supplied to SPMI via lead 103 which specifies the write bit position of KSPMI.

Data on the input highway 101 is written only to the bit specified by the read 103 at the SPMI address specified by the read 104. ROchi, SPMl,
It is commonly called bit selection random write type. A random write type without bit selection is simply called a random write type.

On the other hand, the R8CMs stores encoded information for determining the read address from the SPMI for data on the outgoing highway 102 in correspondence with the time slot of the outgoing highway 102. RCNT4 supplies the count value synchronized with the time slot number of outbound highway 102 to R80M5 and ASEL7 via lead 109.

As a result, the read data of R80M5 is supplied to AGEN6 and ASEL7 via lead 110. The AGEN 6 generates the dial tone, the time slot number of the talkie 1 no call/arm turn as a read address with truth values as shown in FIG. 3 according to the input data, and supplies them to the ASEL 7 via the lead 113. ASE
In L7, according to the designation from the board 110 from R80M5, the output lead 109 from RCNT4 (sequential read address) or the output lead 113 from AGEN6 (multi-distribution address) is selected and read according to the input/output correspondence relationship shown in FIG. It is supplied to the SPMI via lead 105 as an address.

Next, the signal converted to a 64 Kb/s uniform signal at a bearer speed of 32 Kb/s is sent to TSOlTSI on the incoming highway 101 as T S 13 K 64 K
b/s dial tone is assigned, and
Iway 102 TS3, entering Highway 1 old TSO
, TSI data is bearer multiplexed and output, and TS4. The operation of the time switch according to the embodiment of the present invention will be explained in more detail by taking as an example the case where dial tones are multi-distributed to TS7. When performing this exchange operation, the exchange control device (not shown in the figure) includes an address bus 106, a data bus 107, and a write enable line 1.
11, data '00' is sent to address O of WSCM3.
1101010101" and data '00' to address 1.
1110101010', data% to address 13
110111111111'' is written, and data 10 is written to address 3 of 'R8CM5 via address bus 106, data p/4 bus 107, and write enable line 112.
0〃, and data '01' is written to address 4 and address 7.

Here, the TSO data for input highway 101 is ' a
abbecdd”, TSI data 1eeffggh
h", the data of T S 13 is 'atuvwX7Z'. At the timing corresponding to the TSO of the incoming highway 101, the content of address O of WSCM3 is '001101.
010101' is read and supplied to the SPMI, the odd bit of data 'abad' is written to the odd bit position of address 3 of the SPMI, and the input highway 1
At the timing corresponding to TSI 01, the contents 10011101010101 of address 1 of WSCM3 are read out and supplied to SPMI, so the contents of address 3 of SPM1 are read out and supplied to SPMI.
'efgh' is written to the even bit position of the data, and as a result, the contents of address 3 of SPMI are '
eafbgchd'.

Furthermore, at the timing corresponding to TSI3 of the input highway 101, the content of address 13 of WSCM3 is '1101
11111111 is read out and supplied to SPMI, so the SPMI address (13K is 'lltuvwx
yzl is written.

On the other hand, at the timing corresponding to Ta3 of the output highway 102, the content 100 of address 3 of R8CMs is read out and supplied to ASEL7, so in ASEL7,
The output of RCNT4 ('0011' at this time) connected to DI03 to D100 is connected to DO3 to DOOK output j, SP
Since it is supplied to MI, the contents of address 3 of SPMI are read, and the data 'e' is sent to Ta3 of the outgoing highway 102.
afbgchd' is sent.

Also, at the timing corresponding to Ta4 and Ta2 of the output highway 102, the contents of addresses 4 and 7 of R80M5 (all 'oi') are read, and the contents of AGIN6 and AS
Supplied to E7. AGIN6 outputs an output '1101# corresponding to this input to 003-DO. ASEL
7, S2 from R80M5, S1 human power ('o1')
Inputs D113 to DIIO('
1101') is output to DO3 to DOI, and '1101' is supplied to SPMI as a read address.As a result, address 13 of SPMI is read out, so no data is sent to Ta4 and Ta2 of output highway 102. '
atuvwxyz'' is sent.

As described above, by using the time switch of this embodiment, the bearer speed of time slots O and l of the incoming highway is set to 32K.
A multiple exchange function that performs bearer multiplexing of 53 K b/s universal signals and outputs them to time slot 3 of the outgoing highway, and time slot 13 of the incoming highway.
A multi-distribution function was realized that outputs the dial tone assigned to the output highway to time slots 4 and 7.

In this embodiment, the write operation to the channel memory is performed by bit selective writing, but in applications that do not require bit selective writing, the contents of each address in the memory held in the write control circuit of this embodiment are A time switch having the same effect can be realized by using only the address for writing data of each time slot on the input highway into the channel memory.

Furthermore, in this embodiment, in order to reduce the bit width of the holding memory of the read control circuit, the holding memory stores coded information for determining the read address of the channel memory, and generates the read address. Although the readout address selection circuit is provided in the readout control circuit, a time switch circuit having the same effect can also be realized by providing a holding memory in the readout control circuit that stores the readout address of the channel memory itself. .

〔Effect of the invention〕

According to the present invention, since it is possible to variably specify both the address of the communication path memory in which data of the incoming highway is written and the address of the communication path memory from which data to the highway is read, it has the characteristics of a random write type switch. , we were able to provide a time switch circuit that can realize multi-distribution functions, has high functionality, is economical, and has a wide range of applications.

[Brief explanation of drawings]

FIG. 1 is an embodiment of the time switch circuit of the present invention, FIG. 2 is a time chart thereof, FIG. 3 is a truth table of the address generation circuit 6, and FIG. 4 is the input/output of the address selection circuit 7. It is a figure showing a correspondence table. ! ...Speech path memory (SPM), 2...Writing counter (WCNT), 3...Writing holding memory (
WSCM), 4... Read counter (RCNT),
5... Reading holding memory (R80M), 6...
Address generation circuit (AGIN), 7...Address selection circuit (AsEL). Agent Patent Attorney Tadashi Akimoto Actual Figure 2 +03 〕22〕22 Goko +02 J Nikyo 2'' Masayu → T4TI Figure 3

Claims (1)

[Claims] 1. A communication path memory provided between an incoming highway and an outgoing highway, and a write address for storing address correspondence information of the communication path memory into which data of each time slot on the incoming highway is to be written. and a read address holding memory for storing address correspondence information of the channel memory from which data of each time slot on the outgoing highway is to be read. 2. The address correspondence information to be stored in the above-mentioned write address holding memory is information specifying the address of the channel memory where the data of each time slot on the corresponding input highway is to be written and the bit position to be written. A time switch circuit according to claim 1, comprising: 3. A communication path memory provided between the incoming highway and the outgoing highway, a write address holding memory that stores address correspondence information of the communication path memory into which data for each time slot on the incoming highway is to be written, and an outgoing highway. A read address holding memory that indirectly specifies the address correspondence information of the channel memory from which the data of each time slot on the outgoing highway is to be read, and a continuous read address memory for the channel memory corresponding to each time slot on the outgoing highway. sequential read address generation means for generating addresses; multi-distribution address generation means for generating multi-distribution addresses according to the read contents of the read address holding memory; A time switch circuit comprising: a read address selection circuit for selecting a read address as an output of either the sequential read address generation means or the multi-distribution address generation means. 4. The address correspondence information to be stored in the write address holding memory is information specifying the address of the channel memory to which data of each time slot on the corresponding input highway is to be written and the bit position to be written. A time switch circuit according to claim 3, comprising: