JPS6379457A - Signal tone trunk drive circuit - Google Patents

Abstract

PURPOSE:To easily change a pattern of an intermittent signal tone and also to simplify the constitution of a circuit by storing pattern data of various intermittent signal tones in a random access memory. CONSTITUTION:A memory control signal 9 and a mode changeover signal 11 are zero from a memory control circuit 3, an address counter 2 generates sequentially addresses 0, 1, 2 by using a clock signal 10 to read data from the random access memory 1. On the other hand, it is supposed that data 1 is stored in the 0-th bit of, e.g., address 3, 7... in the random access memory 1 and data 1 is stored in the 1st bit of addresses 7, 15..., then outputs of output buffers 41, 42 go respectively to a high level at a period 4/8 times that of a clock signal and an intermittent signal tone with a desired period is outputted from a signal tone trunk 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal tone trunk drive circuit for driving a signal tone trunk that generates various intermittent signal tones in an exchange or the like.

[Conventional technology]

FIG. 4 is a block diagram of a conventional example of this type of signal tone trunk drive circuit, and FIG. 5 is a time chart thereof.

The signal tone trunk 13 has a signal tone generator 18 and one communication line 1.
7.18 and transformers 14.15 and 14.15, respectively, and
It consists of relays A and B and their contacts a and b, and by connecting and disconnecting relay contacts a and b, intermittent signal sounds with different cycles are output to communication lines 17 and 18. By turning on transistor 5.6, relay A,
B is driven respectively. The binary counter 25 is composed of three T flip-flops 25, 252, 253, and receives a clock signal! The period of 0 is T6 (-0,125
sec), each flip-flop 25. ,25□
, 253 outputs 2Ef, 27, 28 have periods Tx(=2To), Tz(=4To) as shown in FIG.
), T3(-8To). AND gate 29 is a T flip-flop 25. , 252 output 2e ,
27 and outputs an output 31 to the base of the transistor 5. AND gate 30 is a T flip-flop 25. The outputs 26 to 28 of ~253 are logically ANDed, and the output 32 is output to the base of the transistor 6. Therefore, the outputs 31 and 32 have a period T, respectively, as shown in FIG.
2 (-0.5sec).

The width is 2T3 (=15 sec) and To (-0, 125 sec), and the level becomes high. As a result, transistor 5.
6, relays A and B are driven at a cycle of 0.5 sec, 15 sec, and the signal tone trunk 13 outputs 0.5 sec.
, An intermittent tone signal with a period of 1 sec is output to the communication lines 17 and 18.

[Problem that the invention seeks to solve]

In the conventional signal tone trunk drive circuit described above, as the types of intermittent patterns increase, the number of counter circuits and gate circuits increases, and the number of connection points within and between each circuit increases, so it is necessary to change the function. In this case, there is a drawback that the circuit cannot be easily changed.

[Means for solving problems]

The signal tone trunk drive circuit of the present invention includes a signal tone generator;
A signal tone trunk drive circuit that drives a signal tone trunk including a device or a plurality of relays that connect and connect the signal tone of a signal tone generator by connecting and disconnecting contacts, and a switching transistor that drives each of the relays.

Random on/off data for each switching transistor is written to a predetermined bit position for each switching transistor so that each relay closes at a cycle that is a desired integer multiple of the clock signal by sequentially reading from each address. an access memory; an address counter that generates an address for the random access memory; a memory control circuit that supplies the clock signal to the address counter and controls writing/reading of the random access memory; and a memory control circuit that lowers the output of the random access memory. It has an output buffer that converts the impedance into impedance and outputs it to each switching transistor.

By storing the pattern data of various intermittent signal tones in the random access memory in this way, the circuit configuration can be simplified, and the pattern of the intermittent signal tones can be easily changed by simply rewriting the data in the memory.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flow diagram of one embodiment of the signal tone trunk drive circuit of the present invention, FIG. 2 is a diagram showing an example of data in the random access memory 1, and FIG. 3 is a time chart of this embodiment.

The configuration of the signal tone trunk 13 is the same as the conventional example shown in FIG.
・Call with two types of intermittent signal tones! i! 17.18
I'm going to go to the middle of the day. Random access memory 1 has addresses 0, 1, 2, . . . in bytes. ... is attached, and the Oth and 1st bits are respectively transistor 5 (relay A),
Corresponding to transistor 6 (relay B), the 2nd and subsequent bits are unused), the 0th bit is at address 3°7, . . . , and the 1st bit is at address 7, 15, . ...The address contains "1°° data." When the mode switching signal 11 is "1" (data accumulation mode), the address counter 2 transfers data from the memory data line 7 to the address specified by the address data line 12. The input data of is stored in the memory 1, and the mode switching signal 11 is
0" (read mode), addresses 0, 1, 2...
・ are generated sequentially and output to the random access memory 1. The memory control circuit 3 outputs a read/write memory control signal 9 to the random access memory l, and outputs a mode switching signal 11 and a clock signal 10 to the address counter 2.
Output.

Next, the operation of this embodiment will be explained with reference to FIG.

The memory control circuit 3 sets the memory control signal 9 and the mode switching signal 11 to "0", and the address counter 2 changes to addresses 0°, 1, 2, . . . by the clock signal 10. . . , are generated in sequence, and data is read from the random access memory 1. As mentioned above, in the random access memory 1, the 0th bit is assigned to addresses 3, 7, . ..., the data of "l II" is stored, and the first bit is the address 7.15.
Since the data of "1" is stored in the output buffers 41 and 42, the outputs of the output buffers 41 and 42 become high level at a period of 4 times and 8 times that of the clock signal 10, respectively, as shown in FIG. 3, which is different from the conventional example. Similarly, signal tone trunk 13 is also 0.5s
ec, an intermittent signal tone with a period of 1 sec is sent to the communication line 1, respectively.
Output on 7.18.

〔Effect of the invention〕

As explained above, the present invention can simplify the circuit configuration by storing pattern data of various intermittent signals in the random access memory, and can easily change the pattern of intermittent signal sounds by simply rewriting the data in the memory. can be changed,
It has a large economic effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the signal tone trunk drive circuit of the present invention, FIG. 2 is a diagram showing an example of data in the random access memory 1, FIG. 3 is a time chart of the embodiment of FIG. 1, FIG. 4 is a block diagram of the conventional example, and FIG. 5 is a time chart of FIG. 4. 1... Random access memory, 2... Address counter, 3... Memory control circuit,
' I s 42... Output buffer, 5.6... Transistor, 7... Memory data line, 81 + 82
...Output data line, 9...Memory control signal, 10...Clock signal,
11...Mode switching signal, 12...Address data line, 13...Signal trunk, A, B...Relay, 'a, b...Relay contact, 14.
15...Transformer, 16...Signal tone generator, 1
7.18...Call line. Hitto sword figure 2 A

Claims (1)

[Scope of Claims] A signal tone trunk drive circuit for driving a signal tone trunk including a signal tone generator and one or more relays that connect and connect the signal tone of the signal tone generator. and a switching transistor that drives each of the relays, and a corresponding bit position at a predetermined bit position for each switching transistor so that each relay closes at a cycle of a desired integral multiple of the clock signal by sequentially reading from each address. A random access memory into which on/off data of a switching transistor is written; an address counter that generates an address for the random access memory; and a memory that supplies the clock signal to the address counter and controls writing/reading of the random access memory. A signal tone trunk drive circuit comprising: a control circuit; and an output buffer that converts the output of the random access memory into a low impedance and outputs it to each switching transistor.