JPS59212061A - Out pulse dial circuit - Google Patents

Abstract

PURPOSE:To record new dial data accurately even during telephone service by inhibiting dial information from being read out of a memory by a mode switching signal for nonservice/service mode switching. CONSTITUTION:An FF38 for mode switching is reset when telephone service is off, and a gate circuit 42 is in an off state to hold the reception of an external dial request signal 16 in readiness. An external recording mode signal 37 is at a level L, so a gate circuit 39 is ready to accept a write pointer preset signal 5 from a memory write control circuit 1. When a recording signal 37 is inputted in recording mode, on the other hand, a write pointer 4 is preset in an address 00 through the gate circuit 39. Further, the FF38 is set to inhibit reading operation in recording mode. Therefore, new dial data is recorded accurately during service.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an outpulse dialing circuit, and more particularly to an outpulse dialing circuit capable of rewriting dialing information during a call.

[Prior art]

An example of a control circuit for recording and reading out dial information in a conventional out-pulse dial circuit is shown in FIG. 1 and will be explained. In FIG. This is a memory write control circuit that operates according to the write control signal 1 when inputted. 4 is a write pointer for addressing (hereinafter abbreviated as write pointer).

5 is a write pointer preset signal from the memory write control circuit 1 that presets an address in this write pointer 4, 6 is a control signal from the memory write control circuit 1 that increments the write pointer 4, T is an address bus, and 8 is a dial information memory circuit that stores
Reference numerals 10, 11, 12, and 13 are gate circuits that are controlled by the write enable signal 9 from the memory write control circuit 1 and write dial data to the address of the memory circuit 8, respectively.

14 is an address bus, 15 is a read pointer for specifying an address when reading the memory (hereinafter referred to as read pointer), and 18 is an input for an external dial request signal 16 and a data request signal 17 from a dial pulse generation control circuit 30. A gate circuit 19 inputs the output of this gate circuit 18 and sends a control signal 32 and a read pointer preset signal 33 to the read pointer 15.
The memory read control circuits 21, 22, 23.24 that control the read pointer 15 by sending out the read data 25.2B from the memory circuit 8 are controlled by the read enable signal 20 from the memory read control circuit 19.
, '27.28, respectively, in the dial pulse generation control circuit 30, 31 is a dial pulse output terminal, and 29 is a data load signal sent from the memory read control circuit 19 to the dial pulse generation control circuit 30.

34 is a system control section, and this system control section 34 is configured to send a control signal 35 and a control signal 36 to the memory write control circuit 1 and the memory read control circuit 19, respectively, to control their operations.

Next, the operation of the dial data recording/reading control circuit shown in FIG. 1 will be explained with reference to FIG. 2.

This figure 2 is a time chart showing the operating waveforms of each part.
(A) shows the case of writing dial data (dial information), and (B) shows the case of reading dial data (dial information).

First, in the initial state, the write pointer 4 during memory writing is preset to the address ""001 by the write pointer preset signal 5 (see (a) in FIG. Address '00' of memory circuit 8 through bus T
Select. This aspect is shown in (,) of FIG. 2(A).

This second country (,) indicates the manner in which blank data is written to the memory 4, and ADR8* is the address 100',
ADR8 is an address '01', and RT indicates an area of one cycle. Also.

INL in (a) of FIG. 2(A) indicates initialization, and RT in (,) of FIG. 2 ((translation)) indicates first digit writing.

Then, blank data as shown in FIG. 2(A) (e) is written into the address of the memory circuit 8 by the memory write control circuit 1.

Next, when dial data 3 is input from the outside,
The memory write control circuit 1 is activated by the write control signal 2 having a waveform as shown in FIG. Gate circuits 10 and 11 by signal 9
, 12, 13, respectively, and are written to address 100' of the memory circuit 8.

When the writing of the first digit is completed, the control signal 6 from the memory write control circuit 1 ((d) in FIG. 2(A)
), the write pointer 4 is incremented by +1, and address 101' of the memory circuit 8 is selected.
Blank data as shown in (.) of the second country is written to address 101' of the memory circuit 8.

-5-^^1 4- Thereafter, in the same way as described above, the second and subsequent digits of dial data 3 are written to the memory circuit 8, and when the writing of the final dial data is completed, the write pointer 4 will write the number of dial digits to be written + 1. It points to a memory address and retains that state unless another write operation is performed.

Next, the operation when reading dial data in the 1 normal mode will be explained with reference to FIG. 2(B).

First, in the initial state, the read pointer (hereinafter referred to as read pointer) 15 for specifying an address when reading the memory is activated by the read pointer preset signal 33 (see FIG. 2(B)) from the memory read control circuit 19.
, )) is preset to address 100', and the address 1 of the memory circuit 8 is preset to address 100' through the address bus 14.
Select 00#.

Next, when a dial request signal 16 having a waveform as shown in (,) in FIG. 2(B) is input from the outside to the memory read control circuit 19 through the gate circuit 18.

6- The read enable signal 20 shown in FIG. 2(B) (d) from the memory read control circuit 19 causes the memory circuit 8 to pass through the gate circuits 21, 22, 23, and 24, respectively. The contents of address '00', ie, the dial data of the first digit, are read out. The read data 25, 26, 27° 28 read from this memory circuit 8 is sent to the memory read control circuit 19.
Yoyo data load signal 29 ((・) in Figure 2 (B)
) is set in the dial pulse generation control circuit 30, and the dial pulse output terminal 3 is set at a predetermined period.
1, it is output as a dial pulse signal with a waveform as shown in (4) of FIG. 2(B). Here, this Figure 2 (B)
In (f), t indicates the prepause time, and t,
indicates the interdigit Bose time. DP indicates an area for one digit of dial pulse.

When the output of the first digit dial pulse signal is completed, the dial pulse generation control circuit 30 outputs the dial pulse signal as shown in FIG. 2(B).
Data request signal 1 with a waveform as shown in (g) of
T is output. Further, according to the read pointer increment shown in FIG. 2(B), which is the control signal 32 from the memory read control circuit 19, the read pointer 15 is incremented by +1, and the address 101' of the memory circuit 8 is selected. However, similarly to the first digit described above, the gate circuits 21 to 2 are activated by the read enable signal 20 shown in FIG.
4 respectively, the contents of the address 101' of the memory circuit 8, that is, the second digit dial data 25 to 2.
8 are respectively read out, set in the dial pulse generation control circuit 30, and output as a dial pulse signal to the dial pulse output terminal 31 at a predetermined period.

Thereafter, the contents of the memory circuit 8 are sequentially read in the same manner, and the read operation is completed when the data read from the memory circuit 8 becomes blank data. and,
In this mode, writing and reading are performed in this way, but what is the relationship between the writing and reading cycles?

Since the read cycle follows the write cycle, the system control s34 controls the memory write control circuit 1 so that the read cycle is not performed during write.
A control signal 35 is sent to the memory read control circuit 19, and a control signal 36 is sent to the memory read control circuit 19.
．． The above write and read operations through 36 are in a call state.

It operates in the same way regardless of the non-call state.

Therefore, if you want to record new dial data during a call in this state, the light pointer 4 is not preset and is held.

The new dial data will be written to the next digit of the previous dial data.

In addition, in the dial data recording/reading control circuit in such an outpulse dial circuit, new dial data must always be written from memory address OO, so it is impossible to record accurate dial data. The drawback is that it cannot be done. At the same time, when writing dial data, a dial pulse signal was output from the dial pulse output terminal even though the caller was in a telephone call state, causing audible noise to the caller. This has the disadvantage of causing malfunction of the switching equipment.

[Object and structure of the invention]

In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks, and its purpose is to make new dialing data accurate even during a call and to prevent other interference. The object of the present invention is to provide an out-pulse dial circuit that can record without affecting the output.

In order to achieve such an object, the present invention provides a mode switching means for switching between a non-call time and a call time.

comprising means for presetting a write pointer of a memory circuit that stores dial information according to an input signal supplied to the mode switching means, and means for inhibiting reading of dial information from the memory circuit in response to the input signal;
The memory circuit can be rewritten during a call.

〔Example〕

10- Embodiments of the present invention will be described in detail below based on one drawing.

FIG. 3 is a circuit diagram showing an embodiment of an outpulse dial circuit according to the present invention, and only the parts necessary for explanation are shown.

In FIG. 3, the same reference numerals as in FIG. 1 indicate the priest part, 37 is a recording mode signal, 38 is a 7-lip-flop for mode switching which inputs this recording mode signal 3T, and this flip-flop 38 is a non-conducting flip-flop. It constitutes a mode switching means for switching between the time of a call and the time of a call. 3
9 is a recording mode signal 37 and a memory write control circuit 1.
This is a gate circuit that receives the light pointer precent signal 5 from the gate circuit 39, and receives the control signal 40 from the gate circuit 39.
It is configured to control the line pointer 4 by. The gate circuit 39 and the control signal 40 constitute means for presetting the write pointer 4 of the memory circuit 8 which stores the serial information according to the input signal supplied to the mode switching means. Reference numeral 42 denotes a gate circuit which inputs the ``mutual'' output signal 41 of the flip-flop 38 and the output of the gate circuit 1B, performs a logical product of both signals, and sends the output to the memory read control circuit 19. It constitutes a means for inhibiting reading of dial information from the memory circuit 8 in response to an output signal from the switching means. The memory circuit 8 is configured so that it can be rewritten during a call.

Next, the operation of the embodiment shown in FIG. 3 will be explained with reference to FIG. 4, which is a time chart showing operating waveforms of each part.

First, 1 normal mode, that is, when not talking, as shown in Figure 4 (ml
A mode in which the recording mode signal 37 as shown in FIG.
The switching circuit 7 lip-flop 38 is in the reset state, so that its output signal 41 (FIG. 4(c)) is
) is in the 'H level, the gate circuit 42 is in the OFF state, and is in the state of accepting and accepting the dial request signal 16 from the outside. Furthermore, since the recording mode signal 3T from the outside is 1L level as shown in FIG. It is ready to be attached.

Therefore, it is clear that the circuit of the embodiment shown in FIG. 3 satisfies the same functions as the conventional write and read operations shown in FIG.

Next, the operation in the recording mode according to the present invention will be explained. First, when a recording mode signal 37 having a waveform as shown in (,) in FIG. 4 is input from the outside, the gate circuit 3
Throughout the day, the light pointer 4 is preset to address 100'. Also, this recording mode signal 37 causes the flip-flop 38 to be in the set state.
As shown in FIG. 4(,), the output signal 41 changes from the ``H'' level to ``LL level'', prohibiting the read operation in the recording mode. (a) in FIG. 4(b) showing a certain light pointer precent signal shows the light pointer preset time, and also shows the light pointer preset time, and the flip-flop 370'
4(a) showing the ζ" output signal 41, 12-(b) indicates the acceptance state of the dial request signal 16, and (c) indicates the time when reading is prohibited.

In this state, the dial data is written, but the operation when writing is as follows.

The operation is exactly the same as in normal mode, so
The explanation here will be omitted. However, the read operation is performed by the gate circuit 42 using the external dial request signal 16.
Since the data request signal 1T from the dial pulse generation control circuit 30 is prohibited from being input to the memory read control circuit 19, no read operation is performed as in the normal mode.

In this way, even during a single call, new dialing data can be recorded accurately and without causing any trouble to others. It is clear that the recording mode signal 3T can also be realized by providing a recording key that is not used in the normal operation mode. Furthermore, this method can be applied not only to outpulse dialing circuits but also to outpulse dialing circuits having a speed dial mechanism.

〔Effect of the invention〕

As explained above, according to the present invention, new dial data can be recorded accurately and without causing any trouble to others even during a single call, so the practical effect is extremely large. .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a dial data recording/reading control circuit in a conventional out-pulse dial circuit; FIG. 2 is a time chart for explaining the operation of FIG. 1;
FIG. 3 is a circuit diagram showing an embodiment of an outpulse dial circuit according to the present invention. FIG. 4 is a time chart for explaining the operation of the embodiment shown in FIG. 8...Memory circuit, 38...Flip-flop, 39.42...Gate circuit. Special pestle applicant: Iwasaki Tsushinki Co., Ltd. Representative: Masaki Yamakawa (and one other person) 15- Figure 1

Claims (1)

[Claims] mode switching means for switching between non-call time and call time;
Means for presetting a write pointer of a memory circuit for storing dial information in response to an input signal supplied to the mode switching means, and prohibiting reading of dial information from the memory circuit in response to an output signal from the mode switching means. 1. An outpulse dialing circuit comprising means for rewriting the memory circuit during a call.