JP2999877B2 - Access method to time switch, write access method to call path memory, read access method to call path memory, time switch, time switch matrix, time division communication path, and time division digital electronic exchange - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for externally accessing a time switch for exchanging time slots, comprising a channel memory, a control memory, and the like, and a method of writing to the channel memory by the control memory. Access method, read access method to call path memory by control memory thereof, time switch considering wired OR of call data read from call path memory, time switch matrix as time switch aggregate, time switch The present invention relates to a time-division communication path in which a matrix is controlled by a communication path control circuit, and a time-division digital electronic exchange having such a time-division communication path.

[0002]

2. Description of the Related Art Generally, a communication path in a time-division digital electronic exchange is composed of a plurality of time switches having the same configuration. FIG. 4 shows a basic configuration of the time switches. In this time switch, random writing / sequential reading is performed in the channel memory 3. That is, the write data (communication data in frame format) DAW from the input highway 1 is:
The data is read from the control memory 5 by the sequential read address from the counter 4 and written into the communication path memory 3 by the write address ADW supplied through the selector 6. On the other hand, in accordance with the read address ADR supplied from the counter 4 via the selector 6, read data (communication data in a frame format) DAR is read from the communication path memory 3 onto the output highway 2. At the time of writing / reading, if the write address ADW is in a different order from the read address ADR, so-called time slot conversion is performed in the communication path memory 3, so that a function as a time switch is realized. It is.

FIG. 5 shows a configuration in the case where a large-scale communication path is formed by using a plurality of time switches configured as described above. In this case,
The write data DAW1 from the input highway 101 is written into the channel memory by the write address from the control memory in each of the time switches 301 and 302, and
The read data DAR01, DA is determined by the read address from the counter in each of the time switches 301, 302.
R02 is to be read. Similarly, the write data DAW2 from the input highway 102
Is written into the channel memory by the write address from the control memory in each of the time switches 303 and 304, and the read data DAR0 is read by the read address from the counter in each of the time switches 303 and 304.
3, DAR04 is read. Read data DAR0 from each of time switches 301 and 303
1, DAR03 is selected and output from the selector 701 under the selection control by the selection signal S1 from the control memory 601 and is output on the output highway 201 as read data DAR1. . Similarly, any one of the read data DAR02 and DAR04 from the time switches 302 and 304 is selectively output from the selector 702 under selection control by the selection signal S2 from the control memory 602, and then read. Data DAR
2 is output on the output highway 202.

As described above, when a large-scale communication path is constituted by a plurality of time switches, it is necessary to externally provide a control memory and a selector for controlling selection of data read from each of the time switches. Not only that, as the number of time switches constituting the communication path increases, the number of parallel bits increases as the control memory increases, and the selector also requires a multi-input memory. I have.

As a method of solving such a problem, for example, an "output control method of a time-division switch" described in JP-A-59-156097 can be mentioned. FIG.
Shows the configuration of a basic time switch according to the method. In this case, the operation of this time switch is sequential writing / random reading, but the basic configuration is the same as that of the time switch shown in FIG. However, the difference is that, in addition to the respective input channel connection information as the read address ADR to the communication path memory 3 in the control memory 5, each of the read addresses ADR has a free / busy management bit S as a pair with the input channel connection information. That is, the read data from the communication path memory 3 is logically ANDed with the free / busy management bit S by the AND circuit 7 and output to the output highway 2. Therefore, if the idle / busy management bit S for an idle input channel is set to “0” and the idle / busy management bit S to an input channel in use is set to “1” in advance. Irrespective of the data state of the data read from the channel memory 3 for the empty input channel,
The output of the D circuit 7 is in the "0" state. Therefore, using multiple such time switches,
When configuring a large-scale communication channel, the outputs of AND circuits in a plurality of time switches are ORed by an OR circuit,
What is necessary is just to output on an output highway. When constructing a large-scale communication channel, some multi-input OR circuits are required as external circuits, but in any case, the control memory and selector conventionally required are not required, and only a time switch is required. An almost large-scale communication channel can be formed.

[0006]

In the time switch according to the prior art, the idle block management bit is an extension bit, whereby the output of read data from the channel memory to the idle input channel to the outside is suppressed. However, since data is read from the channel memory even though it is an empty input channel, when a large-scale channel is configured by a large number of time switches, the power consumption of the entire channel is ignored. It has not been obtained. In addition, when the communication path is configured as a large-scale communication path, in order to write the channel connection information from the outside to the control memory and to read the contents of the control memory to the outside, an access order is issued from the communication path control circuit. It is necessary to individually issue each time switch, but there is no mention of an access method at that time.

A first object of the present invention is to externally update a communication data write address and an extension bit on a control memory in each time switch when the communication system is configured as a large-scale communication path, An object of the present invention is to provide a method for accessing a time switch, which facilitates reading of a call data write address from the outside. A second object of the present invention is to provide a large-scale communication path,
An object of the present invention is to provide a write access method to a channel memory in which power consumption in the entire channel can be suppressed by controlling write data to the channel memory in each time switch. A third object of the present invention is to provide, when configured as a large-scale communication channel, data read from the communication channel memory in each of the time switches can be wired-ORed on the output highway, and furthermore, consumption of the entire communication channel can be reduced. An object of the present invention is to provide a read access method to a communication path memory in which power can be suppressed. A fourth object of the present invention is to externally update a call data write address and an extension bit on a control memory when a large-scale call path is configured, and to write call data from the control memory. The time switch itself, in which the address can be easily read out to the outside, and the read data from the channel memory can be wired-ORed on the output highway, and the power consumption in the entire channel can be suppressed. To serve. A fifth object of the present invention is to provide a time switch matrix as a time switch aggregate when a large-scale communication path is constituted by such time switches. A sixth object of the present invention is to provide a time division communication channel including such a time switch matrix. A seventh object of the present invention is to provide a time-division digital electronic exchange having such a time-division communication path.

[0008]

A first object of the present invention is to permit external access to a control memory only when one or more bit data on an external access address bus matches self-selection data of the control memory. When updating the address for writing call data and the extension bit, the comparison result between one or more bit data on the external access data bus and the self-selection data of the control memory is used as the extension bit, and While the call data write address is read out onto the external access data bus, the call data write address read from the control memory is stored with the address. A time switch other than that time switch based on the extension bits read simultaneously in pairs Between the call data writing address to be read is accomplished by output control as being wired friendly externally accessible data bus. A second object of the present invention is to sequentially read out a call data write address and an extension bit stored as a pair in a control memory from a control memory in an updatable manner and sequentially read the call data write address and an extension bit in a predetermined address order. The write access to the channel memory based on the address is achieved by controlling whether or not a write operation can be performed in the channel memory based on the simultaneously read extension bits. A third object of the present invention is to provide a read access to a call path memory based on a call data read address based on a counter value from a counter, and to perform a read operation in the call path memory based on an extension bit read from an extension bit memory. On the other hand, the call data read from the call path memory is controlled by using the extension bit as a gate control signal, and the call data is read from the call data read from the call path memory in a time switch other than the time switch. This is achieved by controlling the gate output as being wire-ORable on the output highway.

A fourth object of the present invention is to compare one or more bit data on an external access address bus with the self-selection data of the control memory around the control memory, and, based on the result of the comparison, to externally control the control memory. A comparator for controlling whether or not access from the external memory is possible, and comparing one or more bit data on an external access data bus with self-selection data of the control memory, and comparing the comparison result with a write extension bit for the control memory. And a communication data write address read from the control memory using an extension bit from the control memory as a gate control signal,
A gate element for performing gate output control on the external access data bus so as to be able to perform a gate output control between the address switch and the call data write address read from the control memory in the time switch other than the time switch; The extended bits are input as a write operation enable / disable control signal, and the extended bits from the extended bit memory are input as a read operation enable / disable control signal. The call data read from the call path memory is
This is achieved by providing a gate element enabling wired OR on the output highway between the time switch and the call data read from the call path memory in the time switch. The fifth object is achieved by connecting the time switches configured as described above in a multidrop manner in parallel to an external access data bus and an external access address bus common to the time switches. The sixth object is achieved by accommodating the time switch matrix configured as described above in a communication path control circuit via an external access data bus and an external access address bus common to each time switch. The seventh object is achieved by providing an electronic exchange with a time-division communication path configured as described above.

[0010]

When the communication path control circuit accesses each time switch via the external access address bus and data bus common to each time switch, one or more bit data on the address bus is self-selected by the control memory. As an external access to the time switch including the control memory only when the data matches,
When updating the call data write address and the extension bit, a comparison result between one or more bit data on the data bus and the self-selection data of the control memory is used as an extension bit to write the call data as write data. On the other hand, when the call data write address is read onto the data bus, the call data write address read from the control memory is stored in an extension bit that is read simultaneously with the address. Based on
The output is controlled so that wired OR can be performed on a data bus between the switch and a call data write address read from a time switch other than the time switch. In addition, a call data write address and an extension bit, which can be updated in the memory and are stored as a pair, are sequentially read from the control memory sequentially in a predetermined address order, and a call is made based on the call data write address. At the time of writing access to the channel memory, if the write operation in the channel memory is controlled based on the extension bits read at the same time, the write operation in the channel memory can be suppressed.
The power consumption in the channel memory is reduced. Further, when reading and accessing the communication path memory based on the communication data read address based on the count value from the counter, whether or not the read operation in the communication path memory is possible based on the extension bits sequentially read out sequentially from the extension bit memory in a predetermined address order. Is controlled, the reading operation in the channel memory can be suppressed, so that the power consumption in the channel memory can be reduced. Further, when the communication data read from the communication channel memory is gate-controlled in a predetermined manner using the extension bit as a gate control signal, the communication data simultaneously read from the communication channel memory in a plurality of time switches is , Which can be wired OR on the output highway as it is.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS. First, a description will be given of a time switch related to random write / sequential read according to the present invention. FIG. 1 shows an example of the configuration. In this case,
The counter 4 whose count value is updated in a predetermined cycle, and the count value from the counter 4 as a read address, and a call data write address stored as updatable as a pair to indicate the open / closed state of the input channel. A frame format from the input highway 1 using the control memory 5 which is sequentially read out externally in a predetermined cycle together with the extension bit, a call data write address from the control memory 5 as a write address, and a counter value from the counter 5 as a read address. A communication path memory 3 for performing random writing of communication data and sequential reading of frame-format communication data to the output highway 2, a communication data writing address read from the control memory 5, a writing address, and a counter 5. From the control memory 5 as a read address using the counter value of Storing the extended bits read together, it has become one extension bit is configured as including at least a extension bit memory 13 to be read to the outside in a predetermined period.

The communication channel memory 3 is generally composed of a plurality of memories (the capacity of each memory is equivalent to one frame of communication data), and its write / read mode is alternately updated at a frame cycle. The operation in the write mode of the communication data from the input highway 1 to the communication path memory 3 will be described as follows. That is, in the write mode, the address for writing call data to the call path memory 3 is generated by the read access of the control memory 5 via the selector 12 using the count value from the counter 4 as the read address. It has become something. The call data is written in the call path memory 3 by the call data write address given from the control memory 5 via the selector 6. At this time, an extension bit read out together with the call data write address from the control memory 5 is used. Is logically ANDed with the clock signal by the AND circuit 11 via the selector 14, and then inputted to the communication path memory 3 as a write operation enable / disable control signal. The extension bit indicates whether the input channel is free or blocked,
Since writing is not required when the input channel is vacant, whether or not the writing operation to the channel memory 3 can be performed can be controlled by the extension bit. In other words,
When the extension bit is in the "1" state, the write operation is permitted, but when it is in the "0" state, the write operation is disabled. As a result, write access to an empty input channel is prohibited. Therefore, when a large-scale communication path is formed by a plurality of time switches, the power consumption can be considerably reduced as a whole. When writing the call data to the call path memory 3, the extension bits read out together with the call data write address from the control memory 5 use the call bit write address as the write address. 13
Is written to. Extended bit memory 1
The extension bit written in 3 is used for gate-controlling the read data read from the channel memory 3 later, which will be described later.

On the other hand, in the mode for reading the call data from the call path memory 3, the call data is read from the call path memory 3 by the call data read address given from the counter 4 via the selector 6. The extension bits are simultaneously read from the extension bit memory 13 using the address for reading the call data from the counter 4 via the selector 6 as a read address. The extension bit is input to the communication path memory 3 via the selector 14 as a read operation enable / disable control signal. This controls whether or not the read operation of the communication data from the communication path memory 3 can be performed. That is,
When the extension bit is in the "1" state, the read operation is permitted. When the extension bit is in the "0" state, the read operation is disabled. As a result, read access to an empty input channel is prohibited. Therefore, when a large-scale communication path is formed by a plurality of time switches, the power consumption can be considerably reduced as a whole. Thus, only when the extension bit is in the “1” state, the call data is read from the call path memory 3, but the call data read from the call path memory 3 is:
The gate is controlled by the AND circuit 7 based on the extension bit read from the extension bit memory 13, and is output on the output highway 2. When a large-scale communication path is formed by a plurality of (in general, N ² , where N is an integer of 2 or more) time switches arranged in a matrix, the output of the AND circuit 7 is transmitted through a multi-input OR circuit. What is necessary is to output on the output highway.
A tri-state buffer gate is used instead of the ND circuit 7, and when the extension bit is in the "1" state, the impedance state of the gate output is controlled by the extension bit so that the output impedance state is set to the low output impedance state. In this case, these gate outputs can be wired-ORed on the output highway 2 without the need for a multi-input OR circuit.

As described above, the communication data write address and the extension bit are stored in the control memory 5 as a pair, and these are updated as necessary, and are stored in the communication path control circuit as necessary. It is to be read. Here, an external access to the control memory 5, that is, a write / read access by the communication path control circuit, will be described. The access is made by an external access data bus (16 in this example) common to each time switch. DATA, external address bus (assuming 16-bit configuration in this example) AD
This is performed by the DR and the write / read mode control signal R / W (-). When a large-scale communication path is formed by a plurality of time switches arranged in a matrix, any of a plurality of time switches in a column direction or a row direction is selected, and access is performed to the time switches. However, the selection control is performed by controlling a predetermined number of bits (the upper three bits in this example) in the external access address bus ADDR and the self-selection data IDO ××× (×××: 000 to 111) of the self-selection data IDO of the time switch. ). Self-selection data ID
Oxxx is set in advance around the comparator 9 by a jumper wire or the like.
The comparator 3 compares the upper three bits from the DR with the comparator 9 and, based on the result of the comparison, controls whether write / read access to the control memory 5 is possible. When the write / read access is permitted, the write / read access address is the lower 13 bits on the external access address bus ADDR and is input to the control memory 5 via the selector 12. It is.

Further, the contents stored in the control memory 5, that is,
When the call data write address is updated by a write access from the call path control circuit, the extension bit needs to be updated together, but the extension bit to be updated is generated by the comparator 8. It has become. Comparator 8
In this example, a predetermined number of bits (the upper three bits in this example) of the external access data bus DATA passed through the buffer gate and self-selection data IDI ××× (××× ×: 000 to 11
1), and the result of the comparison is generated as an extension bit. Therefore, at the time of write access, the lower 13-bit data on the external access data bus DATA as the address for writing the call data, together with the extension bit from the comparator 8, is set to the same address on the control memory 5. It can be written as

Further, when it is necessary to read out the contents stored in the control memory 5 to the communication path control circuit, a read access is made to the control memory 5 by the communication path control circuit, and the data is read out from the control memory 5. It is necessary for the communication data write address to be read by the communication path control circuit via the external access data bus DATA. However, in consideration of the case where a large-scale communication path is constituted by a plurality of time switches, the control memory 5 The address for writing the call data read from the external access data bus DATA is wired-ORed with the address for writing the call data read from the other time switch on the external access data bus DATA. Data bus DATA
This is what is output above. The output impedance of the tri-state buffer 10 only needs to be controlled by an extension bit that is read out simultaneously with the call data write address. If necessary, the extension bit is set to any one of the upper three bits. It is also possible to assign and output it together with the call data write address. In this case, when the self-selection data IDIxxx is output together with the upper three bits on the external access data bus DATA, the content stored in the control memory is determined by the later-described communication path control circuit. It can be easily reproduced by rewriting.

Here, external access data bus DAT
How the extension bits are generated according to the relationship between the upper three bits (DATA13 to 15) from A and the self-selection data IDIxxx, and the upper three bits (ADDR13) from the external access address bus ADDR ~ 1
Depending on the relationship between 5) and the self-selection data IDOxxx, how the control memory 5 can be accessed (chip enable state), and how the read output from the control memory 5 is external depending on the state of the extension bit. It will be described below with reference to FIG. 2 in the sense of confirming whether the data is output on the access data bus DATA. That is, as can be seen from FIG. 2, when any access is made to the control memory 5, it is a precondition that the ADDRs 13 to 15 match the IDOxxx. When data is written to the control memory 5 under the precondition (when the write / read mode control signal R / W (-) is in the "0" state), DATA13 to DATA15 and IDIxxx are used. Is found to be "1" if the match is found, and "0" otherwise, and is written to the control memory 5. When reading from the control memory 5 is performed (when the write / read mode control signal R / W (−) is in the “1” state), the extension bit read from the control memory 5 is set to “1”. "" Only,
The read output results in an external access data bus DATA
The tri-state buffer 10 is put in a high output impedance state when it is "0", and cannot be output on the external access data bus DATA. You can see that.

FIG. 3 shows a configuration of an example of a large-scale time-division communication path including four time switches having the above configuration. In this case, the time switches 301, 30
2, 303 and 304 are connected in parallel with a common external access data bus and external access address bus by multi-drop connection, all of which are configured as a time switch matrix and accommodated in a communication path control circuit. It has become. However, the time switch 3 in this example
Since the AND circuits 01, 302, 303, and 304 use an AND circuit for outputting call data, the OR circuit 40
1,402 are required for call data OR.
Here, the operation of the entire communication path will be briefly described. The self-selection data IDIxxx and IDOxxx in each of the time switches 301, 302, 303, and 304 constituting the time switch matrix are described below. For convenience, they are expressed as (IDIxxx, IDOxxx) as (00000, 000) and (00000, 000, respectively).
1), (001, 000), and (001, 001). Now, call data DA1 in time slot (synonymous with channel) T1 on input highway 101 is
Assuming a case where the connection is inserted into the time slot T2 on the output highway 202, it is understood that the time switch 302 should be used to perform the time slot conversion, as is clear from the figure. Therefore, all the time switches 301, 30 connected by multi-drop connection from the communication path control circuit 501.
DATA13 ~ 15 = 00 for 2,303,304
0, ADDR13 to 15 = 001, and if write access is performed to write address data T2 for writing call data to address T1 of the control memory in each of time switches 301, 302, 303, 304, the time switch In the control memory at 302, together with the address data T2 for writing call data, the extension bit is set to "1".
While the extension bit is written as "0" in the control memory of the time switch 304 together with the call data write address data T2. In any case, the time switches 301 and 303 are written.
Are not accessed and the stored contents are not updated. The communication data DA1 in the time slot T1 on the input highway 101 has the extension bit of the control memory in the time switch 302 set to "1", so that the communication data writing address data T2 is used as the write address. The data is written to the address T2 of the communication path memory in the time switch 302, and at the same time, the address data T2 for writing the communication data from the control memory is used as the write address, and the extension bit " 1 "will be written. On the other hand, the time slot T on the input highway 102
Since the extension bit of the control memory in the time switch 304 is "0" in the speech data DA2 at 1, writing to the address T2 of the speech path memory in the time switch 304 is not performed. However, at this time, in the time switch 304, the address bit T2 for writing call data from the control memory is used as a write address, and the extension bit "0" is written to the address T2 of the extension bit memory. . Eventually, the call data will be read from the call path memory in each of the time switches 302 and 304 according to the call data read address from the counter. At this time, the time switch 302 with the extension bit set to "1" , The speech data DA1 is read into the time slot T2 only, and the read operation from the address T2 of the speech path memory is not performed in the time switch 304 in which the extension bit is set to "0". Is output as "0" as the read call data. Therefore, if the read output from each of the time switches 302 and 304 is ORed by the OR circuit 402, the call data DA is stored in the time slot T2 on the output highway 201.
1 is to be inserted. The communication path in this example is 4
However, when the self-selection data IDIxxx and IDOxxx are configured as 3 bits, the matrix can be expanded to a matrix of up to 8x8 time switches. Yes, and it is clear that a larger matrix can be constructed by increasing the number of bits.

As described above, with reference to the time switch according to the present invention, an access method to the time switch, a write access method to the channel memory in the time switch, a read access method to the channel memory in the time switch, Although the time switch itself, the time switch matrix as the time switch aggregate, and the time division communication path in which the time switch matrix is accommodated in the communication path control circuit have been described, all of these techniques are applied to the time division digital electronic exchange. It is clear that it can be applied.

[0020]

As described above, according to the first aspect, when a large-scale communication channel is configured, the address for reading the communication data and the extension bit on the control memory in each time switch are externally provided. And it is easy to read out the call data readout address from the control memory to the outside.
When configured as a large-scale communication channel, power consumption in the entire communication channel can be suppressed by controlling write data to the communication channel memory in each of the time switches. If configured as a call path,
The data read from the channel memory in each of the time switches can be wired-ORed on the output highway, and the power consumption of the entire channel can be suppressed. When configured
It is easy to externally update the call data read address and the extension bit on the control memory and read the call data read address from the control memory to the outside, and the read data from the call path memory is output. A time switch in which wired OR can be performed on the highway and power consumption in the entire communication path can be suppressed can be obtained.

According to a fifth aspect of the present invention, there is provided a time switch matrix as a time switch aggregate when a large-scale communication path is constituted by such time switches. A time-division communication path including such a time switch matrix, and according to the seventh aspect, time-division digital electronic exchanges each having such a time-division communication path can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an example of a time switch related to random writing / sequential reading according to the present invention;

FIG. 2 is a diagram for explaining a function of self-selection data according to the present invention;

FIG. 3 is a diagram showing a configuration of an example of a large-scale communication channel including a plurality of time switches according to the present invention;

FIG. 4 is a diagram showing a basic configuration of a time switch related to random writing / sequential reading;

FIG. 5 is a diagram showing a configuration of an example of a large-scale communication path using the time switch according to the related art;

FIG. 6 is a diagram showing an example of a configuration of a time switch according to the related art having an extension bit in a control memory;

[Explanation of symbols]

1, 101, 102 ... input highway, 2, 201, 2
02: output highway, 3: communication channel memory, 4: counter, 5: control memory, 6, 12, 14 ... selector, 7,
11 AND circuit, 8, 9 comparator, 10 tristate buffer, 13 extended bit memory, 301 to 30
4. Time switch, 401, 402 ... OR circuit, 501
... Speech channel control circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-267698 (JP, A) JP-A-55-136788 (JP, A) JP-A-61-116496 (JP, A) (58) Investigation Field (Int.Cl. ⁷ , DB name) H04Q 11/00-11/08 H04Q 3/52 (54) [Title of the invention] Access method to time switch, write access method to channel memory, channel Read access method to memory, time switch, time switch matrix, time division channel and time division digital electronic exchange

Claims (7)

(57) [Claims] 1. A counter in which a count value is updated in a predetermined cycle, and a count value from the counter as a read address, a call data write address stored as updatable, and an extended bit as a pair together with an extension bit in a predetermined cycle. , A write address of a call data write address from the control memory as a write address, and a count value from the counter as a read address as random read / write of frame format call data from an input highway. A communication path memory in which sequential reading of frame-format communication data to the output highway is performed, and an address for writing communication data from the control memory is used as a write address.
Storing the extension bits read from the control memory,
Using the count value from the above counter as a read address,
A method for accessing a time switch including an extension bit memory from which extension bits are sequentially read out, comprising: updating a call data write address and an extension bit on a control memory; and externally accessing the call data write address. When data is read onto the data bus for use by address data from the address bus for external access and write data from the data bus for external access, one or more bit data on the address bus is used for self-selection of the control memory. External access to the control memory is permitted only when the data matches, and when updating the address for writing call data and the extension bit, one or more bit data on the data bus for external access and self-selection data of the control memory are updated. The result of the comparison with When the call data write address is read onto the external access data bus, the call data write address read from the control memory is simultaneously read in pairs with the address. On the basis of the extension bit, a time switch is controlled to be output as a wired OR on an external access data bus between a call data write address read from a time switch other than the time switch and a call data write address. how to access. 2. A counter in which a count value is updated in a predetermined cycle, and a count value from the counter as a read address, a call data write address stored as updatable, and an extended bit as a pair together with an extension bit in a predetermined cycle. , Random writing of frame-format communication data from an input highway, using a control memory which is sequentially read out externally as an address, a communication data writing address from the control memory as a writing address, and a count value from the counter as a writing address. A communication path memory in which frame-type communication data to the output highway is sequentially read, and a communication data writing address from the control memory as a write address.
A write access method to a communication path memory in a time switch including an extension bit memory in which an extension bit is stored and an extension bit is sequentially read to the outside using a count value from the counter as a read address. The call data write address and the extension bit stored in the memory as an updatable and stored as a pair are sequentially read sequentially in a predetermined address order, and then the call path memory is written and accessed based on the call data write address. A write access method to the communication path memory, wherein whether or not a write operation is performed in the communication path memory is controlled based on the extension bits read at the same time. 3. A counter in which a count value is updated at a predetermined cycle, and a count value from the counter as a read address, a call data write address stored as updatable and an extension bit as a pair, together with an extension bit at a predetermined cycle. , Random writing of frame-format communication data from an input highway, using a control memory which is sequentially read out externally as an address, a communication data writing address from the control memory as a writing address, and a count value from the counter as a writing address. A communication path memory in which frame-type communication data to the output highway is sequentially read, and a communication data writing address from the control memory as a write address.
A read access method to a communication path memory in a time switch including an extension bit memory in which an extension bit is stored and an extension bit is sequentially read to the outside using a count value from the counter as a read address, wherein the count from the counter is When a read access is made to the speech path memory based on a read address which is a value, whether or not a read operation is possible in the speech path memory is controlled based on the extension bit read from the extension bit memory, and the extension bit is used as a gate control signal. Between the call data read from the call path memory and the call data read from the call path memory in a time switch other than the time switch,
A read access method to a channel memory in which gate output is controlled as being wire-orable on an output highway. 4. A counter in which a count value is updated in a predetermined cycle, and a call data write address stored as updatable using the count value from the counter as a read address, together with an extension bit as a pair, in a predetermined cycle. , A write address of a call data write address from the control memory as a write address, and a count value from the counter as a read address as random read / write of frame format call data from an input highway. A communication channel memory for sequentially reading frame-format communication data to the output highway, and a communication data writing address from the control memory as a write address.
A time switch including an extension bit memory for storing extension bits and sequentially reading extension bits to the outside using a count value from the counter as a read address, wherein at least one of the time switches on an external access address bus is provided around the control memory. And a comparator for controlling whether or not the control memory can be externally accessed based on the comparison result, and one or more bit data on an external access data bus. And a comparator for comparing the self-selection data of the control memory with the self-selection data, and generating the comparison result as an extended bit for writing to the control memory; and an extended bit from the control memory as a gate control signal.
Wired OR on the external access data bus between a call data write address read from the control memory and a call data write address read from the control memory in a time switch other than the time switch A communication path memory in which an extended bit from the control memory is input as a write operation enable / disable control signal, and an extended bit from the extended bit memory is input as a read operation enable / disable control signal. In the periphery, the extended bit from the extended bit memory is used as a gate control signal, and the speech data read from the speech path memory is separated from the speech data read from the speech path memory in a time switch other than the time switch. A gate element that enables wired OR on the output highway Vignetting time switch comprising. 5. A counter for updating a count value in a predetermined cycle, and a count value from the counter as a read address, a call data write address stored as updatable and an extension bit as a pair together with an extension bit in a predetermined cycle. , A write address of a call data write address from the control memory as a write address, and a count value from the counter as a read address as random read / write of frame format call data from an input highway. A communication path memory in which sequential reading of frame-format communication data to the output highway is performed, and an address for writing communication data from the control memory is used as a write address.
An extension bit memory for storing the extension bits and externally reading the extension bits sequentially to the outside using the count value from the counter as a read address is provided. One or more bit data on an external access address bus is provided around the control memory. And a self-selection data of the control memory, and a comparator for controlling whether or not the control memory can be accessed from the outside based on the comparison result; A comparator for comparing self-selection data in a memory and generating the comparison result as a write extension bit to the control memory; and a call read from the control memory using the extension bit from the control memory as a gate control signal. The data write address is read from the control memory in a time switch other than the time switch. A gate element for gate output control is provided between the address for writing data and the address for external access on the data bus for external access as a wired-OR, and an extension bit from the control memory is input as a write operation enable / disable control signal. In the vicinity of the communication path memory where the extended bit from the extended bit memory is input as the read operation enable / disable control signal, the extended bit is used as a gate control signal,
Between the call data read from the call path memory and the call data read from the call path memory in a time switch other than the time switch, a time provided with a gate element that enables wired OR on the output highway A time switch matrix in which each switch is multi-drop connected in parallel and in a matrix to an external access data bus and an external access address bus common to each time switch. 6. A counter for updating a count value in a predetermined cycle, and a count value from the counter as a read address, a call data write address stored as updatable and an extension bit as a pair together with an extension bit in a predetermined cycle. , A write address of a call data write address from the control memory as a write address, and a count value from the counter as a read address as random read / write of frame format call data from an input highway. A communication path memory in which sequential reading of frame-format communication data to the output highway is performed, and an address for writing communication data from the control memory is used as a write address.
An extension bit memory for storing the extension bits and externally reading the extension bits sequentially to the outside using the count value from the counter as a read address is provided. One or more bit data on an external access address bus is provided around the control memory. And a self-selection data of the control memory, and a comparator for controlling whether or not the control memory can be accessed from the outside based on the comparison result; A comparator for comparing self-selection data in a memory and generating the comparison result as a write extension bit to the control memory; and a call read from the control memory using the extension bit from the control memory as a gate control signal. The data write address is read from the control memory in a time switch other than the time switch. A gate element for gate output control is provided between the address for writing data and the address for external access on the data bus for external access as a wired-OR, and an extension bit from the control memory is input as a write operation enable / disable control signal. In the vicinity of the communication path memory where the extended bit from the extended bit memory is input as the read operation enable / disable control signal, the extended bit is used as a gate control signal,
Between the call data read from the call path memory and the call data read from the call path memory in a time switch other than the time switch, a time provided with a gate element that enables wired OR on the output highway A time-division communication path in which each switch is multi-drop-connected in parallel and in a matrix to an external access data bus and an external access address bus common to each time switch, and accommodated in a communication path control circuit. 7. A counter for updating a count value in a predetermined cycle, and a count value from the counter as a read address, a call data write address stored as updatable, and an extension bit as a pair together with an extension bit in a predetermined cycle. , A write address of a call data write address from the control memory as a write address, and a count value from the counter as a read address as random read / write of frame format call data from an input highway. A communication path memory in which sequential reading of frame-format communication data to the output highway is performed, and an address for writing communication data from the control memory is used as a write address.
An extension bit memory for storing the extension bits and externally reading the extension bits sequentially to the outside using the count value from the counter as a read address is provided. One or more bit data on an external access address bus is provided around the control memory. And a self-selection data of the control memory, and a comparator for controlling whether or not the control memory can be accessed from the outside based on the comparison result; A comparator for comparing self-selection data in a memory and generating the comparison result as a write extension bit to the control memory; and a call read from the control memory using the extension bit from the control memory as a gate control signal. The data write address is read from the control memory in a time switch other than the time switch. A gate element for gate output control is provided between the address for writing data and the address for external access on the data bus for external access as a wired-OR, and an extension bit from the control memory is input as a write operation enable / disable control signal. In the vicinity of the communication path memory where the extended bit from the extended bit memory is input as the read operation enable / disable control signal, the extended bit is used as a gate control signal,
Between the call data read from the call path memory and the call data read from the call path memory in a time switch other than the time switch, a time provided with a gate element that enables wired OR on the output highway A time-division communication path in which each switch is multi-drop-connected in parallel and in a matrix to an external access data bus and an external access address bus common to each time switch and accommodated in a communication path control circuit. A time-division digital electronic exchange comprising: