JPH022299A - Time switch circuit - Google Patents

Abstract

PURPOSE:To realize a large capacity of switch circuit with simple constitution by devising the replacement of time slots between plural time division multiplex lines by the constitution of one stage of time switch without provision of any spatial switch. CONSTITUTION:A data from plural incoming lines is written in a multiport data memory 1 from plural input ports by using an address generated by a write address generating means 2 without duplication as to all input data. On the other hand, data readout address outputted to plural outgoing lines from plural output ports of the mutli-port data memory 1 is set respectively to readout address setting means 31, 32,...3n. Through the setting of the readout address, since the plural output ports can access the data inputted from any of plural input ports, that is, the data inputted any of plural incoming lines, the replacement of the time slots between plural lines is attained.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to streamline the configuration and control of a time switch circuit that switches time slots of time-division multiplexed data. A time switch circuit for exchanging time slots is provided with a plurality of input/output ports, inputs and stores data from a plurality of input lines independently from the plurality of input ports, and inputs and stores the stored data from the plurality of input ports. A multiport data memory that is independently output from a plurality of output ports onto a plurality of output lines, and a write address to the multiport data memory are set so that they do not overlap for data input from all of the input ports. and read address setting means for setting a read address for data to be output from the multiport data memory onto the plurality of output lines.

(Industrial Application Field) The present invention relates to a time switch circuit that switches time slots of time-division multiplexed data.

-m uses a time switch and a space switch as replacement digital switches.

A time switch changes the temporal order of time slots of time-division multiplexed data, and a space switch switches connections between incoming and outgoing lines using spatially placed electronic gate switches. This is what we do.

Time switches are mainly used as replacement digital switches because they can economically construct large-capacity switches using memory circuits, but as the number of time slots increases, replacement digital switches with one stage・As it becomes difficult to configure switches, we are trying to expand the circuit network by using a multi-stage configuration in which these time switches are connected by space switches.

However, in the configuration in which the time switch and the space switch are connected in multiple stages as described above, the scale of the switch increases and the control system becomes complicated.

Therefore, there has been a need for a technology that realizes a large-capacity switch circuit with a simple configuration.

[Prior art and problems to be solved by the invention]

A conventional time switch has a memory circuit having one input/output port and an address control memory for setting time slot exchange information, and transmits time-division multiplexed data from the input port of the memory circuit. The time slots are exchanged by sequentially writing data using addresses generated by a counter or the like, and reading these written data using addresses set in the address control memory.

Therefore, by using a large-capacity memory circuit, a large-capacity switch can be realized economically, but when the number of time slots exceeds the capacity of the memory circuit, or when the time slots are swapped between multiple time division multiplex lines. In order to do this, it was necessary to construct a multi-stage switch circuit combining the above-mentioned time switch and space switch.

FIG. 5 shows an example of the configuration of a switch network using a multi-stage connection combining conventional time switches and space switches, and shows how time slots are exchanged between four time division multiplex lines and four time division multiplex lines. This figure shows the configuration of a switch circuit network for this purpose.

In FIG. 5, the space switch circuit is indicated by SSW, and the time switch circuit is indicated by TSW. Further, ACM is an address control memory. For example, incoming lines 1 to 4 and outgoing bits t to 4 are each 51
Assuming that a frame consists of two time slots and each time switch circuit TSW has a 512-byte memory circuit, in order to exchange time slots between multiple lines, the procedure shown in FIG. In order to achieve this, it is necessary to provide four time switch circuits TSW, and to provide space switch circuits before and after the four time switch circuits TSW.

At this time, as shown in FIG. 5, it is necessary to provide an address control memory for each of the above-mentioned 12 time switch circuits and spatial switch circuits in order to set the time slot switching information for each of the circuits. .

As described above, the conventional switch circuit has a problem in that the configuration and control become complicated when the number of time slots is large or when time slots are exchanged between a plurality of time division multiplex lines.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a large-capacity time switch circuit whose structure and control are simplified.

[Means to solve the problem]

FIG. 1 is a basic configuration diagram of the present invention. In this figure, 1
2 is a multi-port data memory, 2 is a write address generation means, and 31, 3□, . . . 37 is a plurality of read address setting means.

The multiport data memory 1 has a plurality of input/output ports, inputs and stores data from a plurality of input lines independently from the plurality of input ports, and inputs and stores the stored data from the plurality of output ports. Outputs independently from a port onto multiple outgoing lines.

The write address generating means 2 generates write addresses to the multiport input/output data memory 1 for all input data without duplication.

The read address setting means 32, 3□, . . . 31 are as follows:
Read addresses for data to be output from the multiport data memory 1 onto the plurality of outgoing lines are set respectively.

[For production]

Data from a plurality of input lines are written from a plurality of input ports to a multiport data memory 1 according to an address generated by a write address generation means 2 so that there is no duplication of all input data.

On the other hand, read address setting means 3++3g+...
In 37, read addresses of data to be outputted from a plurality of output ports of the multiport data memory 1 onto a plurality of outgoing lines are respectively set.

By setting the above read address, the plurality of output ports can access data input from any of the plurality of human power ports, that is, data input from any of the plurality of input lines. Therefore, time slots can be exchanged even between multiple lines.

As described above, according to the configuration shown in FIG. 1, it is possible to exchange time slots between multiple time division multiplex lines by using a single-stage time switch configuration without providing a space switch in either the preceding or subsequent stages. Become.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention.

In FIG. 2, 10 is a multiport data memory, 20 is an address counter, 30-1°30-2.
...30-n is address control memory, 41 1.
41-2.・ ・ 41-n is a memory area specification selector, 42-1.42-2. ...42-n is a memory addressing selector.

The multiport data memory 1o is a random access memory that has a plurality of input/output ports and can input and output data independently from each input/output port.

Corresponding input lines and output lines are connected to these plurality of input/output ports, respectively.

The address counter 20 receives the above multi-volume data.
It generates an address when writing data to the memory 10, and repeatedly outputs a number that counts the time slot for one frame of data on the corresponding large line, and the output is sent to the memory address designation selector 42. -1.42-2
．． . . 42n is applied to one of two data input terminal groups to be described later.

Address control memory 30-1.30-2. ...3
0-n output addresses of read data from each of the plurality of output ports of the multiport data memory 10. As will be described later, the most significant bits of each of these read addresses are assigned to memory area designation selectors 41-1, 41-2, . ...41-n to one input terminal of the corresponding one, and the bits lower than the most significant bit of each of the read addresses are:
The above memory address designation selector 42-1.42-2
．． . . . is applied to the other data input terminal group of the corresponding ones of 42-n. The address control memory 30-1.3
0-2. .=30-n is set with an address of the multiport data memory 10 in which data of time slots to be sequentially outputted from the corresponding one of the plurality of output ports is written.

Memory area specification selector 41-1.41-2゜...4
1-n outputs the most significant bit of the address in the multi-port data memory 10 during writing and reading, and this output specifies a large division of the memory area in the multi-port data memory 10. It is something to do. The memory area specification selector 41-1
゜41-2. ...41-n each has two input terminals, and "0", '1', ... "n-1" are applied to one of the two input terminals in order, respectively,
The most significant bits of the outputs of the address control memories 30-1, 302, . . . 30-n are applied to the other of the two input terminals in sequence. And memory area specification selector 411.41-2. ...41-n is
At the time of data fortune-telling, "0" and "
1”.

... n-1", and when reading data,
The address control memory 30-1, 302, . . . 30
-n selects and outputs the most significant bit of the address output.

Memory addressing selector 42-1.42-2.・
・・42-n is the above multiport data memory 1
0, the bits lower than the most significant bit of the address during writing and reading are output, and it has two data input terminal groups, and one of the two data input terminal groups has the address counter. 20 outputs are applied to the other, respectively, the address control n
Memory 30-1.30-2. . . . Apply the bits lower than the most significant bit of the address output by 30-n. and memory addressing selector 42 1.
42-2. 42-n outputs the output of the address counter 20 when reading data, and outputs the address control memory 30-1, 30-2゜...30-n when outputting data. Atl outputted by
Select and output the bits lower than the most significant bit of the female.

A more specific example of the operation of the configuration of the embodiment of the present invention as described above will be described below with reference to FIGS. 3A, 3B, and 3C.

FIG. 3B corresponds to the configuration of FIG. 2, and includes two input ports, first and second, connected to the first and second two input lines, respectively, and two input ports, the first and second input ports, respectively. A dual port memory 11 having two output ports, first and second, connected to two output lines of the address counter 21, an address control memory 30-1.
30-2, memory area specification selector 41-1.41-2
, and memory addressing selector 42-1°4
2-2.

The memory area of the dual port memory 11 consists of two areas each having a capacity of 512 bits, and each area has an address whose most significant bit is "0" or "0".
1”.

The most significant bits of the seven addresses are output from memory area designation selectors 41-1 and 41-2.

The memory area designation selector 41-1 and memory address designation selector 42-1 designate a write address for data input from the first input port when inputting data, and designate a write address for data input from the first output port when outputting data. Specify the read address of the data to be read. The memory area designation selector 41-2 and the memory address designation selector 42-2 designate a write address for data manually entered from the second input port when inputting data, and output from the second output port when outputting data. Specify the read address of the data to be read.

As in the configuration of FIG. 2, memory addressing selectors 42-1 and 42-2 each output bits lower than the most significant bit of the address.

Further, as in the configuration shown in FIG. 2, the memory area specifying selectors 41-1 and 41-2 each have two input terminals, and one of the input terminals has "0" and "1", respectively. is applied, and the most significant bi-soto of the addresses output by the address control memories 30-1 and 30-2 is applied to the other one of the two.

The memory addressing selectors 42-1 and 42-2 each have two data input terminal groups, and the output of the address counter 21 is applied to one data input terminal group of each. The bits lower than the most significant bit of the address output by the address control memories 30-1 and 30-2, respectively, are applied to the other terminal of each.

The memory area designation selectors 41-1 and 41-2 respectively select the above "θ" and "l" when writing data.
Also, when reading data, the uppermost via outputted by the address control memories 30-1 and 30-2 is selected and output.

The memory address designating selectors 42-1 and 422 respectively output the output of the address counter 21 when writing data, and output the address control 'I'll memory 30-1, 30-2 when outputting data. selects and outputs the bits lower than the most significant bit of the address output by .

Each of the two input ports of the dual port memory 11 receives time-division multiplexed data consisting of 512 time slots per frame from the 0"4M connected to each input port. A specific example of the data is shown in Fig. 3A.The data of time slot No. 1.2°3, . . . 512 is sent from the first large line, and the data of time slot No. ．．
Data of 514°515, . . . 1024 is input.

The above-mentioned manual data corresponds to the output of the memory area designation selector 41-1, 41-2 at the time of writing, and the data from the first large line is dual-ported.
The data from the address 0 to 511 area of memory 11 and from the second large line is stored in dual port memory 1.
1 is written in the area of addresses 511 to 1024.

The write address in each area is the memory
Output 000.001 of address counter 21 applied via addressing selector 42-1.42-2
．． 002. ...IFF (hexadecimal numbers) are written in the order in which they were input, as shown in FIG. 3B.

On the other hand, in the address control memory 30-1, the time slot NO6 to be output from the first output port is 1.0.
．． 514.3.518.7.516.5. ...
, and NOo of the time slot to be output from the second output port is stored in the address control memory 30-2 as “
513,512°2.3.6,519,4.517''.

When reading data from the dual port memory 11, the output of the address counter 21 is 000.001.
．． 002. ...IFF is address control memory 30-1
and 30-2 as a read address. Accordingly, the address control memory 30-1
and 30-2 are read out, and the contents of memory area specification selector 41-1 and address specification selector 4 are read out.
2-1 is also applied as the address of the dual port memory 11 via the memory area designation selector 41-2 and the address designation selector 42-2. Thus, from the first and second output ports of the dual port memory 11, respectively, as shown in FIG. 3C,
Data whose time slots have been swapped according to the contents of the address control memories 30-1 and 30-2 is output.

As described above, according to the time switch circuit having the configuration shown in FIG. 3B, it is possible to change the time slots of time division multiplexed data between a plurality of input lines using a single stage time switch circuit.

The configuration shown in FIG. 2 described above is a generalization of the number of input/output ports from two to two in the configuration of the time switch circuit shown in FIG. 3B described above, and the operation of the configuration shown in FIG. 3
The operation is exactly the same as that of the configuration shown in Figure B.

FIG. 4 shows a specific example of how the time slots of time-division multiplexed data manually inputted from one large circuit such as -C are replaced.

Data from one line is stored in data memory 1.
is written to the corresponding area within 2. At the time of output, these written data can be accessed from any output port, and are read according to the settings of the access control memory corresponding to each output port, and are connected from the corresponding output port. output on the outgoing line.

As explained above, according to the time switch circuit of the present invention, a multi-stage configuration with a conventional space switch circuit is required.
Swapping of time slots on multiple lines is realized by a single stage time switch circuit. As is clear from a comparison with the configuration shown in FIG. 5 described above, the amount of hardware can be greatly reduced by eliminating the need for space switch circuits and the access control memory associated with them.

In addition, in the conventional time switch circuit, one frame N
If the switching operation performed as a timesloft is divided into N time slots into n ports and switching is performed using the time switch circuit according to the present invention, if the memory access time is equal, the switching operation will be reduced to 1/n of the conventional one. The process can be done in a time of . This means that the data input/output speed can be increased to n times the conventional speed, and when the data input/output speeds are equal, the clock frequency of the time switch circuit can be reduced to 1/n, so for example , which allows the use of C-MOS logic with low speed but low power consumption.

〔Effect of the invention〕

According to the time switching circuit of the present invention, the configuration and control can be simplified, and a larger amount of time-division multiplexed data can be processed at higher speed.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIGS. 3A, 3B, 3C, and 4 are specific examples of the time switch circuit of the present invention. FIG. 5 is a diagram illustrating an example of the configuration of a conventional Swiss/Sochi circuit by multi-stage connection of a conventional spatial switch/7chi circuit and a time switch circuit. [Explanation of symbols] I...Multi-port data memory, 2...Old address generation means, 31.3□, ~3n...Read address setting means,
10.11...Multiport data memory, 20
．． 21...Address counter, 30-1.30-2
．． ...30-n...address control memory, 41-1. 41-2. ...41-n-memory area specification selector, 42-1.42-2.・ ・ 42-n-・-Memory address specification selector.

Claims (1)

[Scope of Claims] 1. A time switch circuit for exchanging time slots of time-division multiplexed data, including a plurality of input/output ports, and transmitting data from a plurality of input lines independently from the plurality of input ports. a multi-port data memory (1) for inputting and storing data into a plurality of output ports, and outputting the stored data independently onto a plurality of output lines from the plurality of output ports; ) write address generation means (2) for generating write addresses to the multi-port data memory (1) so as not to overlap for data input from all of the input ports; Read address setting means (3_1, 3_2,...
3_n).