JPS63220695A - Half-fixed line housing system in time division line switching system - Google Patents

Half-fixed line housing system in time division line switching system

Info

Publication number
JPS63220695A
JPS63220695A JP5462087A JP5462087A JPS63220695A JP S63220695 A JPS63220695 A JP S63220695A JP 5462087 A JP5462087 A JP 5462087A JP 5462087 A JP5462087 A JP 5462087A JP S63220695 A JPS63220695 A JP S63220695A
Authority
JP
Japan
Prior art keywords
memory
control
semi
fixed line
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5462087A
Other languages
Japanese (ja)
Inventor
Tomoyoshi Shimizu
清水 知義
Tatsuo Kobayashi
小林 達生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5462087A priority Critical patent/JPS63220695A/en
Publication of JPS63220695A publication Critical patent/JPS63220695A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To shorten time required for the release-connection of a half-fixed line by supplying the data reading address of the channel memory of a time division switch with the aid of the output of a selection circuit and composing a line indicated by a half-fixed line control device to be housed in a time division switching system as the half-fixed circuit. CONSTITUTION:Data held by a second control memory 4 is written by a man- machine interface 8 and the half-fixed line control device 7 without using a call control device 6. Therefore by the interface 8 and the device 7, the address of the channel memory 1 which needs half-fixed connection is stored in a second control memory 4 and '1' is stored in the high rank bit of the memory 4 and in a first memory 3, only the address of the channel memory 1 associating with a normal call is stored by the call control device 6. Thus all the required channels are set by the address of the channel memory 1 read from the first control memory 3 or the second control memory 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は時分割回線交換機に関し、特に時分割回線交換
機内に半固定接続の回線を収容する方式〔従来の技術〕 従来、時分割交換機に半固定回線を収容する場合、時分
割通話路スイッチの制御メモリに対し、交換機の初期設
定時あるいは、手動による半固定回線の設定時に呼制御
装置から半固定回線の接続データを時分割通話路スイッ
チの制御メモリに書込み、この接続データをタイムスロ
ットごとに読出して通話路メモリを制御している。した
がって制御メモリのデータが書換えられない限り、同じ
入線は同じ出線と接続されて通信データが転送される。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a time-division line switch, and in particular, a system for accommodating semi-fixed connection lines in a time-division line switch. When accommodating a semi-fixed line, the connection data of the semi-fixed line is transferred from the call control device to the control memory of the time-division channel switch during the initial setup of the exchange or when manually setting up the semi-fixed line. The communication path memory is controlled by writing this connection data into the control memory and reading it out every time slot. Therefore, unless the data in the control memory is rewritten, the same incoming line is connected to the same outgoing line and communication data is transferred.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半固定回線収容方式は、交換機の初期設
定時あるいは手動による半固定回線の設定時に呼制御装
置から半固定回線の接続データを設定する方式となって
いるので、呼制御装置のプログラムに半固定回線制御の
プログラムを組み込む必要がある。また、通話路中に含
まれる共通線信号回線や長期間接続の重要回線などは上
記のような接続データの設定において呼制御装置が正常
に動作して制御メモリに必要なデータが書込まれるまで
、待たねばならない、特に呼制御装置の障害時には半固
定回線の復旧接続に時間がかかるという欠点がある。
In the conventional semi-fixed line accommodation method described above, connection data for the semi-fixed line is set from the call control device at the time of initial setting of the exchange or manual setting of the semi-fixed line. It is necessary to incorporate a semi-fixed line control program into the system. In addition, common line signal lines included in the call path and important lines connected for a long period of time are set up as described above until the call control device operates normally and the necessary data is written to the control memory. However, there is a drawback that it takes time to restore the semi-fixed line, especially when there is a failure in the call control device.

したがって本発明が解決しようとする問題点、換言すれ
ば本発明の目的は半固定回線の設定手段を独立に設ける
ことによって上記の問題点を改善することにある。
Therefore, the problem to be solved by the present invention, in other words, the purpose of the present invention is to improve the above-mentioned problem by independently providing a semi-fixed line setting means.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の時分割回線交換機における半固定回線収容方式
は、呼制御装置によって呼ごとに書換えられる通話路の
接続データを格納する第1の制御メモリと、前記第一の
制御メモリより1ビット多いビット幅を有して半固定的
な通話路の接続データおよび制御信号を格納する第2の
制御メモリと、前記第2の制御メモリに接続データおよ
び制御信号を設定するための半固定回線制御装置と、前
記第2の制御メモリの制御信号に従って前記第1の制御
メモリの接続データまたは前記第2の制御メモリの接続
データのいずれが一方を選択する選択回路とを有し、前
記選択回路の出力にょって時分割スイッチの通話路メモ
リのデータ読み出しアドレスを与え、前記半固定回線制
御装置が指示した回線を半固定回線として時分割回線交
換機に収容するようにして構成される。
The semi-fixed line accommodating system in the time division line exchange of the present invention includes a first control memory that stores communication path connection data that is rewritten for each call by a call control device, and a bit that is one bit larger than the first control memory. a second control memory for storing connection data and control signals of a semi-fixed call path having a width; a semi-fixed line control device for setting connection data and control signals in the second control memory; , a selection circuit that selects either the connection data of the first control memory or the connection data of the second control memory according to the control signal of the second control memory, and the output of the selection circuit selects one of the connection data of the first control memory and the connection data of the second control memory. A data read address of the communication path memory of the time division switch is given, and the line designated by the semi-fixed line control device is accommodated in the time division line exchange as a semi-fixed line.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

同図において時分割回線交換機の時分割通話路スイッチ
は2チヤネルの入ハイウェイ9と出ハイウェイ10とに
接続されたシーケンシャル書込みランダム読出しの通話
路メモリ1と、この通話路メモリ]に選択回路2を介し
て通話路メモリ1の読出しアドレスを与える第1の制御
メモリ3および第2の制御メモリ4と、クロック信号に
もとづき通話路メモリ1の書込アドレスや上記の制御メ
モリ3および4の読出しアドレスを発生するカウンタ5
と、第2の制御メモリ4に接続された半固定回線制御装
置7およびマンマシンインタフェース8とを有して構成
され、さらに第1の制御メモリ3に呼制御装置6が接続
されている。
In the figure, the time-division channel switch of the time-division line exchange includes a sequential write/random read channel memory 1 connected to an incoming highway 9 and an outgoing highway 10 of two channels, and a selection circuit 2 in this channel memory. A first control memory 3 and a second control memory 4 provide a read address of the communication path memory 1 through a clock signal, and a write address of the communication path memory 1 and a read address of the above-mentioned control memories 3 and 4 are provided based on a clock signal. Counter 5 generated
, a semi-fixed line control device 7 and a man-machine interface 8 connected to a second control memory 4 , and a call control device 6 further connected to the first control memory 3 .

通話路メモリ1は通常の例えば読出し側制御の通話路メ
モリて2″のチャネルを持つ。また第1の制御メモリ3
は通常のnビット幅2アドレスの保持メモリである。さ
らに第2の制御メモリ4はn+1ビット幅2′″アドレ
スの保持メモリであり、半固定的に接続を行なう出チャ
ネルに対応するアドレスの下位nピッI〜に通常の制御
メモリドと同じくタイムスロツ1〜を入替える通話メモ
リのアドレスを記憶し、上位1ビツトにはその出チャネ
ルにおいて第1の制御メモリ3の出力にもとづいて通話
路接続を行なう場合には” o ’を、第2の制御メモ
リ4の出力にもとづいて通話路接続を行なう場合には“
1゛°を記憶する。
The communication path memory 1 is a normal communication path memory, for example, for reading side control, and has 2'' channels.
is a normal n-bit wide 2-address holding memory. Furthermore, the second control memory 4 is a holding memory with an n+1 bit width 2'' address, and the lower n bits I~ of the address corresponding to the output channel to which the connection is made semi-permanently are stored in time slots 1~1~ as well as the normal control memory memory. The address of the communication memory to be exchanged is stored, and the upper 1 bit is set to ``o'' when the communication path is connected based on the output of the first control memory 3 in the output channel. When connecting the communication path based on the output of “
Remember 1゛°.

選択回路2は第2の制御メモリ4がらの読出しデータの
上位1ビツトが1″であると第2の制御メモリ4からの
読出しデータを通話路メモリ1に送り、」1位1ビット
がo″であると第1の制御メモリ3からの読出しデータ
を通話路メモリ]に送る。
The selection circuit 2 sends the read data from the second control memory 4 to the channel memory 1 when the high-order 1 bit of the read data from the second control memory 4 is 1'', and the 1st bit of the read data from the second control memory 4 is o''. If so, the read data from the first control memory 3 is sent to the channel memory].

第2の制御メモリ4が保持するデータはマンマシンイン
タフェース8および半固定回線制御装置7によって呼制
御装W6を使用することなく書込まれる。
The data held in the second control memory 4 is written by the man-machine interface 8 and the semi-fixed line control device 7 without using the call control device W6.

したがってマンマシンインタフェース8および半固定回
線制御装置7によって第2の制御メモリ4に半固定的な
接続を要する通話路メモリ1のアドレスと上位1ビツト
に“′1″′とを記憶させ、第1の制御メモリ3には通
常の呼に対応する通話路メモリ1のアドレスのみを呼制
御装置6によって格納することにより、第1の制御メモ
リ3まなは第2の制御メモリ4がら続出された通話路メ
モリ1のアドレスによって必要なすべての通話路が設定
される。
Therefore, the man-machine interface 8 and the semi-fixed line control device 7 store the address of the communication path memory 1 which requires a semi-fixed connection in the second control memory 4 and "'1"' in the upper one bit. By storing only the address of the communication path memory 1 corresponding to a normal call in the control memory 3 of the call control device 6, the communication path that has been sequentially output from the first control memory 3 or the second control memory 4 is stored. All necessary communication paths are established by the addresses in memory 1.

また第1の制御メモリ3の内容が記憶されない、すなわ
ち呼制御装置6が動作していない時でも、カウンタ5が
正常に動作すれば第2の制御メモリ4を介して半固定の
通話路の接続は確保される。
Furthermore, even when the contents of the first control memory 3 are not stored, that is, when the call control device 6 is not operating, if the counter 5 operates normally, a semi-fixed communication path is connected via the second control memory 4. is guaranteed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は時分割回線交換機において
呼制御装置の呼処理プログラムから独立した半固定回線
制御装置によって特定の通話路が設定できるので、交換
機自身のプログラム格納を遠隔地から特定の通話路を介
して実行したり、共通線信号用の通話路の設定・変更、
長期間接続の重要回線の通話路設定などが呼処理プログ
ラムから独立して実行できる効果がある。
As explained above, the present invention allows a specific call route to be set by a semi-fixed line control device that is independent from the call processing program of the call control device in a time-division line switch. setting and changing communication paths for common line signals,
This has the advantage that communication path settings for important lines that will be connected for a long period of time can be executed independently from the call processing program.

【図面の簡単な説明】[Brief explanation of the drawing]

第1゜図は本発明の一実施例のブロック図である。 1・・・通話路メモリ、2・・・選択回路、3・・第1
の制御メモリ、4・・・第2の制御メモリ、5山カウン
タ、6・・・呼制御装置、7・・・半固定回線制御装置
、8・・・マンマシンインタフェース、9・・・入ハイ
ウェイ、10・・・出ハイウェイ。
FIG. 1 is a block diagram of one embodiment of the present invention. 1... Call path memory, 2... Selection circuit, 3... First
control memory, 4... second control memory, 5-mount counter, 6... call control device, 7... semi-fixed line control device, 8... man-machine interface, 9... input highway , 10...Exit Highway.

Claims (1)

【特許請求の範囲】 呼制御装置によって呼ごとに書換えられる通話路の接続
データを格納する第1の制御メモリと、前記第一の制御
メモリより1ビット多いビット幅を有して半固定的な通
話路の接続データおよび制御信号を格納する第2の制御
メモリと、前記第2の制御メモリに接続データおよび制
御信号を設定するための半固定回線制御装置と、前記第
2の制御メモリの制御信号に従って前記第1の制御メモ
リの接続データまたは前記第2の制御メモリの接続デー
タのいずれか一方を選択する選択回路とを有し、 前記選択回路の出力によって時分割スイッチの通話路メ
モリのデータ読み出しアドレスを与え、前記半固定回線
制御装置が指示した回線を半固定回線として時分割回線
交換機に収容することを特徴とする半固定回線収容方式
[Scope of Claims] A first control memory that stores communication path connection data that is rewritten for each call by a call control device; a second control memory for storing connection data and control signals of a communication path; a semi-fixed line control device for setting connection data and control signals in the second control memory; and control of the second control memory. a selection circuit that selects either the connection data of the first control memory or the connection data of the second control memory according to a signal, and the output of the selection circuit selects the data of the channel memory of the time division switch. A semi-fixed line accommodating method characterized in that a read address is given and the line instructed by the semi-fixed line controller is accommodated in a time division line exchange as a semi-fixed line.
JP5462087A 1987-03-09 1987-03-09 Half-fixed line housing system in time division line switching system Pending JPS63220695A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5462087A JPS63220695A (en) 1987-03-09 1987-03-09 Half-fixed line housing system in time division line switching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5462087A JPS63220695A (en) 1987-03-09 1987-03-09 Half-fixed line housing system in time division line switching system

Publications (1)

Publication Number Publication Date
JPS63220695A true JPS63220695A (en) 1988-09-13

Family

ID=12975781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5462087A Pending JPS63220695A (en) 1987-03-09 1987-03-09 Half-fixed line housing system in time division line switching system

Country Status (1)

Country Link
JP (1) JPS63220695A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0738929A (en) * 1993-06-28 1995-02-07 Nec Corp Time switch device
JPH0759183A (en) * 1993-08-13 1995-03-03 Oki Electric Ind Co Ltd Control system for time division time switch

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979697A (en) * 1982-10-27 1984-05-08 Fujitsu Ltd Control method of channel memory
JPS60257699A (en) * 1984-06-04 1985-12-19 Hitachi Ltd Time division switch controller

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979697A (en) * 1982-10-27 1984-05-08 Fujitsu Ltd Control method of channel memory
JPS60257699A (en) * 1984-06-04 1985-12-19 Hitachi Ltd Time division switch controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0738929A (en) * 1993-06-28 1995-02-07 Nec Corp Time switch device
JPH0759183A (en) * 1993-08-13 1995-03-03 Oki Electric Ind Co Ltd Control system for time division time switch

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