JPH0514983A - Time division channel switch - Google Patents

Abstract

PURPOSE:To execute the exchange at an exchange speed being a half of a basic exchange speed without change in the exchange at the basic exchange speed by selecting upper half communication information or lower half communication information of basic exchange unit communication information and reading the selected information. CONSTITUTION:A control memory 3 and an expansion control memory 4 store upper/lower selection information of communication information in the basic unit of exchange and a read address in a pair form and output them at an output time of an outgoing highway. In this case, even numbered/odd numbered plane selection circuits 6, 7 select the information in a pair form as to an even numbered/odd numbered plane stored in the memories 3, 4 in response to frame information and give the selected information to time division switches 1, 2. Then a selection circuit 8 outputs alternatively upper half information or lower half information of the circuits 1, 2 in response to the frame information, upper half/lower half selection information read from the circuits 6, 7 and information read from an expansion control memory validity command memory 5. Thus, the exchange processing system as to a half communication speed of the basic exchange unit is built up.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division speech path switch capable of maintaining a switching function at a basic switching speed and performing the switching function at half the switching speed.

[0002] With the diversification of communication media exchanged via the communication exchange network, it is required that the communication exchange network has an exchange function for communication media of various bands. Moreover, the provision of such a switching function is intended to be realized on the extension of the switching speed of 64 Kbps which is the basic switching speed in the existing telecommunication switching network. The present invention is also an invention made based on such a technical basis.

[0003]

2. Description of the Related Art A conventional time-division exchange type speech path switch has a time-division memory of 8 × m bits (the number of accommodating terminal positions) because it is based on the exchange speed of 64 Kbps as described above. However, this time division memory is switched by a sequential write-random read method to generate a required exchange operation.

As means for achieving a wideband exchange of 64 Kbps × n, (1) a method (double buffer method) in which the time division memory is configured as two sides to prevent loss of order in call information (2) Connect the time division memories in series, compare the read and write addresses of both time division memories, and lose the order of the call information due to the presence or absence of the insertion of 1-frame delay by the time division memories in the subsequent stage. There is a method to prevent being exposed. In both of these systems, the exchange rate of 64 Kbps is the basis as described above, and in the case of the wide band exchange of 64 Kbps × n, the rewriting control of the 2n (for bidirectional) control memories is used to achieve the desired value. You have achieved your purpose.

As a means of providing a 32 Kbps exchange function on the extension of the above-mentioned basic system, (a) a system in which the time-division memory has a configuration of 4 × 2 m (m is the number of accommodating terminal positions), (b) ) It is conceivable to use 4 bits out of 8 bits on the main link in vain and use the sub-switch of the trunk image.

FIG. 7 shows a configuration under the above-mentioned method (a). In FIG. 7, the call information (b) input from the incoming highway 60 is the write control circuit (WCTL).
Depending on 61, a sequential write-random read type time division switch circuit 63 ₀ (hereinafter also referred to as # 0 surface) or a time division switch circuit 63 ₁ (hereinafter also referred to as # 1 surface).
Written in. Both the time-division switch circuit 63 ₀ and the time-division switch circuit 63 ₁ are 4-bit (32 Kbps) wide time-division memories. (C-1) and (c-2) in the figure are the time-division switch circuit 63 ₀ and the time-division switch circuit 63, respectively.
Write to ₁ Indicates call information. The control of which is written is performed by the frame information (a) output from the frame generation circuit (FG) 62.

Reading from the time-division switch circuit 63 ₀ and the time-division switch circuit 63 ₁ is performed simultaneously by the address (f) from the control memory 64. (D- in the figure
1) and (d-2) show the call information read from the time division switch circuit 63 ₀ and the time division switch circuit 63 ₁ , respectively. Transmission of these two read call information (d-1) and (d-2) onto the outgoing highway 67 is performed by the frame selection circuit 66.

The frame selection circuit 66 selects the call information (d-2) when the frame information received from the frame generation circuit 62 indicates the # 0 plane, and the frame information is
When the # 1 side is shown, the call information (d-1) is selected. This is also shown in FIG. 8. For example, in frame 0, writing is performed on the # 0 surface and reading is performed on the # 1 surface.

[0009]

Even in the speech path switch shown in FIG. 7, the order of the speech information is disturbed when the time divisional switch circuit having the one-sided structure is used (FIG. 9).
Although it is possible to exchange 32 Kbps while avoiding the above (see arrow), it is necessary to control the rewriting of the control memory 64 to exchange 32 Kbps. In other words, it is not the exchange control program for 64 Kbps exchange, but 3
A switching control program for 2 Kbps switching is required. This means that the control memory must be rewritten twice as much.

The present invention was created in view of the above technical problem, and is a time division method which can achieve the exchange function at half the exchange speed while utilizing the exchange system at the basic exchange speed. Its purpose is to provide an exchange system.

[0011]

FIG. 1 shows a principle block diagram of an invention according to claim 1, and FIG. 2 shows a principle block diagram of an essential part of the invention according to claim 2.

According to the invention of claim 1, as shown in FIG. 1, the communication information of the basic switching unit of the incoming highway is composed of two planes in response to the frame information. Of the corresponding sequential write-random read type time division switch circuit, input to the time division communication path switch, the upper / lower selection information of the communication information of the exchange basic unit and the read address are stored in a pair format,
A control memory 3 which outputs at the output time to the output highway,
Extended control memory 4 that stores the upper / lower selection information of communication information of the exchange basic unit and the read address in a pair format and outputs at the output time to the output highway, and the extended control memory valid that stores the extended control memory valid information Instruction memory 5
And an even number plane selection circuit 6 which is connected to the control memory 3 and the extended control memory 4 and selects both pieces of information in the pair format in response to the frame information and supplies them to the even number plane time division switch circuit. An odd number plane selection circuit 7 which is connected to the control memory 3 and the extended control memory 4 and selects both pieces of information in the pair format in response to the frame information and supplies them to the odd number time division switch circuit. Responsive to the frame information, the upper / lower selection information read from the even number plane selection circuit 6 and the odd number plane selection circuit 7, and the extended control memory valid information read from the extended control memory valid instruction memory 5. Then, the upper half information and the lower half information of the even-numbered time-division switch circuit 1, the upper half information of the odd-numbered time-division switch circuit 2, and the upper half information of the lower half information, Characterized in that a selection circuit 8 which outputs a low half information alternatively.

The invention according to claim 2 is, as shown in FIG. 2, a selection circuit 8 for a time division speech path switch according to claim 1.
Is connected to the following configuration requirements, that is, the upper half information output and the lower half information output of the even-numbered surface time division switch circuit 1,
In response to the upper / lower selection information output from the even-numbered surface selection circuit 6, the upper half information or the lower half information output from the even-numbered surface time division switch circuit 1 is selectively output. Connected to the lower / half selection circuit 10 and the upper half information output and the lower half information output of the odd-numbered surface time division switch circuit 2, and is odd in response to the upper / lower selection information output from the odd-numbered surface selection circuit 7. Number half time output switch circuit 2 outputs the upper half information or the lower half information alternatively, the odd number side upper / lower selection circuit 11 and the even number side time division switch circuit 1 outputs the upper half information. , And the upper half information output of the odd number side time division switch circuit 2, and the output of the even number side upper / lower selection circuit 10 and the odd number side upper / lower selection circuit 11, and the frame information and the extended control memo. A frame upper half information selection circuit 12 that outputs upper half information in response to the extended control memory valid instruction information read from the valid instruction memory 5, a lower half information output of the even-numbered surface time division switch circuit, and an odd number. It is connected to the lower half information output of the plane time division switch circuit and the outputs of the even-numbered upper / lower selection circuit 10 and the odd-numbered upper / lower selection circuit 11, and from the frame information and the extended control memory validity instruction memory 5. And a frame lower half information selection circuit 13 which outputs lower half information in response to the read extended control memory valid information.

[0014]

In the invention according to claim 1, the generated call is in the basic unit of the exchange, and a communication path is formed between the calling and called subscribers for the call. At that time, the extended control memory is effective. The extended connection memory valid display information, for example, “0” is written in the display memory 5.

Then, the input communication information is sequentially written alternately to the even-numbered surface time-division switch circuit or the odd-numbered surface time-division switch circuit according to the frame information.

In this way, the random read from the even-numbered surface time-division switch circuit or the odd-numbered surface time-division switch circuit in which the communication information is written is carried out even in the even-numbered surface time-division switch circuit or in the odd-numbered surface. Also in the time division switch circuit, the upper half information and the lower half information of the communication information of the exchange basic unit are read at the same read timing. Now, assuming that the exchange in the exchange basic unit is 64 Kbps and therefore the communication information is 8 bits, as shown in Table 1, in the even frame, the upper 4 bits of the communication information from the odd number side time division switch circuit ( # 1High) and the lower 4 bits (# 1Low) are read at the same time, and the 8 bits are sent to the output highway. This read relationship is the same for the odd-numbered frames, and as a result, in the time division speech path switch, 64
Kbps will be exchanged. In addition, dc in Table 1 is "0"
It also indicates that it may be either "1" or "1".

[0017]

[Table 1]

Next, referring to FIG. 3, for the exchange at half the speed of the basic exchange unit, for example, the exchange at the half speed when the speed of the basic exchange unit is 64 Kbps, that is, the exchange of 32 Kbps. Explained.

A call is generated from one of the subscribers accommodated in the accommodating terminal position 1 High (A) and the subscriber accommodated in the accommodating terminal position 4 Low (H) on the time axis, and a call is generated between them. A call path is formed, a call between both subscribers is started, and a subscriber accommodated at accommodation terminal position 1Low (B) and a subscriber accommodated at accommodation terminal position 3High (E) on the time axis It is assumed that a frame as shown in FIG. 3 is input in a state in which a call is generated from one of the subscribers, a call path is formed between them, and a call between both subscribers is started. To do. Stored in the extended control memory valid bit stored in the extended control memory valid instruction memory 5 necessary for causing this exchange operation, upper / lower selection information and read address stored in the control memory 3, and extended control memory 4. The selected upper / lower selection information and the read address are written as values shown in FIG. 3 under the control of the main controller (not shown) in response to the occurrence of the corresponding call.

At any read timing, in the frame immediately before the read from the control memory 3 and the extended control memory 4 at the read timing, the communication information input through the input highway (see FIG. 3). 100) are sequentially written (sequentially written) in the memory of the time divisional switch circuit determined according to the frame information at that frame time (see 101 in FIG. 3).

Therefore, for the convenience of explanation, if the reading of the communication information thus written is caused at the read timing corresponding to the accommodation terminal position 1 on the time axis in the output highway, first, the control memory 3 is read. When the write content to be read, that is, the information “1” indicating the lower side in the upper / lower selection information and the read address 4 are selected by the plane selection circuit, for example, the even number plane selection circuit 6, and the read address corresponds The communication information is read out by being supplied to the division switch circuit. The read content is communication information-H. This communication information-H is accommodated on the outgoing highway because it is in the frame information, the upper / lower selection information "1" read from the control memory 3, and the extended control memory valid instruction information "1". It is transmitted as the upper half information H in the terminal position 1. The process of exchanging communication information in the opposite direction will be described below.

At the read timing 4, the extended control memory 4 is read, so that communication information is exchanged in the opposite direction. However, the read content is the upper / lower selection information and the upper side. The read address 1 is the information "0" indicating ". Therefore,
If the read address is used to read to the accommodating terminal position on the time axis, the write content AB of the corresponding time division switch circuit (accommodating terminal position 1) is read. The communication information AB thus read is in the frame information, “0” of the upper / lower selection information read from the extended control memory 4 and “1” of the extended control memory valid instruction information, as described above. As a result, the lower half information A in the accommodating terminal position 4 on the outgoing highway is sent out, so that the above-mentioned exchange process of the communication information in the reverse direction is completed.

The description of the call between the other two subscribers shown in FIG. 3 will be omitted, but it will be apparent that the call can be performed according to the above description. Thus, with respect to the state in which the exchange processing at half the basic exchange rate, for example, 32 Kbps, is stored in the system configured as the basic exchange rate, for example, 64 Kbps,
It has been successfully integrated and incorporated.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 is a block diagram of a time division switching system for carrying out the invention according to claims 1 and 2. In FIG. 4, reference numeral 20 is a speech path switch installed at station A and having a basic exchange rate of 64 Kbps according to the embodiment of the present invention. 21 is 64
It is a trunk line trunk of Kbps and is connected to station B. 23
Is a 64Kbps trunk trunk connected to station C.
22 is a subscriber circuit of 64 Kbps. 24 is 32 from 64 Kbps
A compression trunk that performs compression to Kbps. FIG. 4 shows an exchange mode when the time-division speech path switch 20 has a basic exchange speed of 64 Kbps, but the time-division speech path switch 20 is operated at 32 Kbps according to the present invention. That is, the call information a from the subscriber circuit 22 is compressed and output to the upper 4-bit call information by the compression trunk 24 through the time division call path switch 20. This compressed call information a ′ of 32 Kbps is sent to the time division speech path switch 20.
The call information b ′ (call information of 32 Kbps) of the upper 4 bits inserted from the trunk line trunk 21 into the upper 4-bit position of the frame transmitted to the trunk line trunk 23 is the call information in the time division call path switch 20. It is inserted in the lower 4 bit positions in the same frame in which a'is inserted and sent to the trunk 23.

FIG. 5 shows a detailed view of the time division speech path switch of the embodiment of the present invention which performs such exchange processing. In FIG. 5, reference numeral 30 is an input highway and is selectively connected to a time divisional switch circuit (TSW # 0) 33 ₀ or a time divisional switch circuit (TSW # 1) 33 ₁ via a write control circuit 32. The output is indicated by the reference characters (c-1) and (c-2). Output (c
-1) is supplied to the time divisional switch circuit 33 ₀ and output (c-
2) is supplied to the time divisional switch circuit 33 ₁ . This alternative connection control is performed by the frame information of the frame generation circuit 31.
It is done by (a). The time division switch circuit 33 ₀ also
Further, the time divisional switch circuit 33 ₁ is also sequentially written-
It is a random read type time division switch circuit, and its access unit is constituted by 8 bits.

Reference numeral 34 is an extended control memory 37 under the control of a main control unit (hereinafter referred to as CPU) in response to the occurrence of a call.
It is a CPU bus which transfers a valid instruction bit (hereinafter referred to as ECM), a read address, and upper / lower instruction information. The CPU bus 34 is an ECM effective instruction memory (hereinafter referred to as EEM) and a control memory 36.
(Hereinafter referred to as CM), and the ECM 37. Outputs of the CM 36 and the ECM 37 are connected to an address selection circuit (ASEL # 0) 38 and an address selection circuit (ASEL # 1) 39.

The address selection circuit 38 outputs a read address (f-1) for reading TSW # 0. The most significant bit of the read address (f-1) is supplied to the selection control input of the High / Low selection circuit 40 ₀ . The address selection circuit 39 reads the read address (f-
2) is output. The most significant bit of the read address (f-2) is supplied to the selection control input of the High / Low selection circuit 40 ₁ .

40 ₀ is an upper 4-bit / lower 4-bit selection circuit (HLSE) for the time division switch circuit 33 _0.
L # 0), which will be referred to as a High / Low selection circuit 40 ₀ below.

[0029] The select input of High / Low select circuit 40 _0, the most significant bit output of the address selection circuit 38 are connected. High / Low select circuit 40 ₀ selection criteria, Table 2
Follow Reference numeral 40 ₁ denotes an upper 4-bit / lower 4-bit selection circuit (HLSEL #) for the time divisional switch circuit 33 _1.
1), which will be referred to as a High / Low selection circuit 40 ₁ below. The most significant bit output of the address selection circuit 39 is connected to the selection control input of the high / low selection circuit 40 ₁ . Table 3 shows the selection conditions of the High / Low selection circuit 40 ₁ . High / Low select circuit 40 ₀ may also High / Low selection circuit 4
0 _{1 is} also read from the corresponding time division switch circuit 8
The upper 4 bits or the lower 4 bits of the bit call information are selected, and the reference character (d-1) is added to the 4-bit information selected by the High / Low selection circuit 40 ₀ .
The reference character (d-2) is attached to the 4-bit information selected by the High / Low selection circuit 40 ₁ .

[0030]

[Table 2]

[0031]

[Table 3]

41H is the upper 4 bits output of the time division switch circuit 33 _{0 and} the upper 4 bits of the time division switch circuit 33 ₁ .
Bit output, High / Low select circuit 40 _0, and High / Low
A frame upper 4-bit selection circuit 41H (FSEL-H) that selects 4 bits from the selection circuit 40 ₁ and outputs them as the upper 4 bits on the output highway 42, and will be referred to as a frame selection circuit High 41H hereinafter. Table 4 shows the selection conditions of the frame selection circuit High 41H. or,
41 L is a lower 4 bit output of the time division switch circuit 33 _0, a lower 4 bit output of the time division switch circuit 33 _1, a 4 bit output from the High / Low selection circuit 40 ₀ , and
This is a frame lower 4-bit selection circuit 41L (FSEL-L) that selects the 4-bit output from the gh / Low selection circuit 40 ₁ and outputs it as the lower 4-bits on the output highway 42. refer.
Table 5 shows the selection conditions of the frame selection circuit Low 41L.

[0033]

[Table 4]

[0034]

[Table 5]

In FIG. 5, the time divisional switch circuit 33 _0,
33 ₁ corresponds to division switch circuits 1 and 2 when in FIG. 1 and FIG. 2, the control memory 36 corresponds to the control memory 3 of FIG. 1 and FIG 2. The extended control memory 37 corresponds to the extended control memory 4 of FIG. 1 and FIG.
5 is the extended control memory valid instruction memory 5 of FIG. 1 and FIG.
Corresponding to. The address selection circuit 38 corresponds to the even-numbered surface selection circuit 6 of FIGS.
Corresponds to the odd-numbered surface selection circuit 7 in FIGS. Hi
The gh / Low selection circuit 40 ₀ corresponds to the even-numbered-surface upper / lower selection circuit 10 in FIGS. 1 and 2, and the High / Low selection circuit 40 ₁
Corresponds to the odd number upper / lower selection circuit 11 of FIGS. The frame selection circuit Low 41L corresponds to the frame lower half information selection circuit 13 in FIGS. 1 and 2, and the frame selection circuit High 41H corresponds to the frame upper half information selection circuit 12 in FIGS.

Next, the operation of the speech path switch according to the embodiment of the present invention will be described. Under the conditions similar to those described in the section [Means for Solving the Problems], it is possible to achieve the 32 Kbps exchange control while following the 64 Kbps exchange control system.

It is assumed that time-series input frames as shown in FIG. 3 are sequentially input to the write control circuit 32 via the input highway 30. Each of the input frames is accommodated in each of accommodating terminal positions 1, 2, 3, 4, 5 on the time axis, and between the accommodating terminal position 1High and the accommodating terminal position 4Low on the time axis. It is assumed that those frames have been input during a call and a call between the accommodation terminal position 1Low and the accommodation terminal position 3High on the time axis.

In this call state, the call information A, is stored in the upper 4 bits and the lower 4 bits of the accommodation terminal position 1.
B has call information E in the upper 4 bits of accommodating terminal position 3.
However, the call information H is inserted in the lower 4 bits of the accommodation terminal position 4. The call information A, B, E, and H inserted in the accommodating terminal positions 1, 3, and 4 is the call information H in the upper 4 bits of the frame accommodating terminal position 1 on the time axis of the outgoing highway 42, and the lower order thereof. The call information E is switched to 4 bits, the call information B is switched to the upper 4 bits of the accommodation terminal position 3 on the time axis of the outgoing highway 42, and the lower 4 of the accommodation terminal position 4 on the time axis of the outgoing highway 42 is switched. It is necessary to switch the call information A to the bit.

The extended CM effective bit stored in the ECM effective instruction memory 35 necessary for causing this switching and the most significant bit stored in the control memory 36 are the upper / lower selection instruction bits ([[solve the problem] [Means for Solving]], the read address as the upper / lower selection information) and the most significant bit stored in the ECM 37 are the upper / lower selection instruction bits ([Means for solving the problem]).
It is assumed that the read address, which is the upper / lower selection information in the item (1), has already been written as a value as shown in FIG. 3 under the control of the above-mentioned CPU in response to the occurrence of the corresponding call.

There is no essential part of the present invention in the method of creating the exchange control program used for this write control, and the exchange control program is created in accordance with a known technique and stored in advance in a main storage device (not shown). In response to the occurrence of a call as described above, only the process of storing required data, for example, each data as shown in FIG. 3 in each memory is performed.

Now, each memory as described above, that is, ECM
When each input frame as indicated by reference numeral 100 in FIG. 3 is sequentially input from the input highway 30 in a state where the writing to the valid instruction memory 35, the CM 36, and the ECM 37 is completed, the following processing is performed. It is taken in sequence. Incidentally, in the accommodating terminal positions 1, 2, 3, 4, 5 on the time axis attached to the input frame shown in FIG. 3, data is read out or written corresponding to these accommodating terminal positions in time. , The time division switch circuit 33 ₀ ,
Time division switch circuit 33 ₁ , ECM effective instruction memory 3
5, the memory locations of the control memory 36 and the ECM 37 are also given the same reference numerals 1, 2, 3, 4, 5 for the convenience of the following description.

Each input frame is represented by 10 in FIG.
1, the frame information of the frame generation circuit 31
It is input to the time divisional switch circuit 33 ₀ or the time divisional switch circuit 33 ₁ via the write control circuit 32 which is switched according to (a) and is written. That is, the frame information “0” from the frame generation circuit 31 (see (a) of FIG. 6).
Is output to the time division switch circuit 33 ₀ , and when the frame information “1” is output, it is written to the time division switch circuit 33 ₁ .

Then, the time divisional switch circuits 33 ₀ and 3 3
The reading of the information written in 3 ₁ at the read timing 1 (corresponding to the accommodation terminal position 1) on the time axis will be described.
The lower order selection instruction bit is "1" indicating the lower order as shown by 103 in FIG. 3, and the read address is 103 in FIG.
Since it is "4" as shown in, the time division switch circuit 3
The lower 4 bits to come read from the 3 _0: H, the lower 4
It is output through the High / Low selection circuit 40 ₀ which is supplied with the upper / lower selection instruction bit “1” (see Table 2) for instructing the bit read, and the frame information “1” (from the frame generation circuit 31). Supply (see Table 4),
And a frame selection circuit receiving an extended CM valid bit "1" (see Table 4) from the ECM valid instruction memory 35.
It is sent to the upper 4 bits on the outgoing highway 42 via High 41H (see 105 in FIG. 3).

Similarly, since the upper / lower selection instruction bit read from the ECM 37 is "0" indicating the upper side as shown by 104 in FIG. 3 and the read address is "3", the time axis is on the time axis. The upper 4 bits read from the time division switch circuit 33 ₁ at the read time of read timing 1 (corresponding to accommodation terminal position 1): E
Is supplied with an upper / lower selection instruction bit “0” (see Table 2) that instructs reading of the upper 4 bits.
It is output through the gh / Low selection circuit 40 ₁ and then the frame information “1” is output from the frame generation circuit 31 (see Table 4).
, And the extended CM valid bit “1” (see Table 5) from the ECM valid instruction memory 35, and is output via the frame selection circuit Low 41L.

Thus, at the accommodating terminal position 1 on the time axis of the output highway 42, H is set as the upper 4 bits.
Also, E is inserted as the lower 4 bits. At the read timing 3 on the time axis (corresponding to the accommodation terminal position 3),
Reading similar to the reading timing 1 is performed. That is, at the read time of read timing 3, the lower 4 bits read from the time divisional switch circuit 33 ₀ : B
Is a High / Low selection circuit 40 ₀ and a frame selection circuit
It is sent to the exit highway 42 via Low 41L.

Read timing 4 (accommodating terminal position 4
Corresponding to. ), The same reading as the reading timing 1 is performed. That is, at the read time of read timing 4, the upper 4 bits: A read from the time divisional switch circuit 33 ₁ pass through the high / low selection circuit 40 ₁ and the frame selection circuit High 41H, and exit highway 42.
It is sent upward (see 105 in FIG. 2).

As described above, a call between the accommodating terminal position 1High and the accommodating terminal position 4Low on the time axis,
And accommodation terminal position 1Low and accommodation terminal position 3Hi on the time axis
FIG. 6 is a time chart collectively showing the call status with gh.

Also, as described in Table 1 for the conditions for performing the above-mentioned 32 Kbps exchange processing, "0" (see Table 1) is set in the ECM valid instruction memory 35 in response to the occurrence of a call. If this is done, the exchange function of the call path switch will be 64
You can return to the exchange process at Kbps.

[0049]

As described above, according to the present invention, in the communication path switch of the basic exchange unit, the upper half communication information and the lower half communication information of the basic exchange unit communication information are stored in the communication path switch. Since the control whether to read from the memory of the basic exchange unit is used, the communication speed of half of the communication speed in the basic exchange unit can be set in the communication path switch without breaking the basic part of the communication path switch. It is possible to construct an exchange processing system of.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the invention according to claim 1.

FIG. 2 is a principle block diagram of the invention according to claim 2;

FIG. 3 is an explanatory view of the principle of the invention according to claim 1 and claim 2;

FIG. 4 is a configuration diagram of a time division exchange system for carrying out the invention according to claims 1 and 2.

FIG. 5 is a diagram showing an embodiment of the invention according to claim 1 and claim 2;

6 is a diagram showing a time chart of the embodiment shown in FIG.

FIG. 7 is a configuration diagram of a conventional speech path switch.

FIG. 8 is a diagram showing a time chart in the case of configuring a time divisional switch circuit with two surfaces.

FIG. 9 is a diagram showing a time chart in the case where the time divisional switch circuit is configured by one surface.

[Explanation of symbols]

1, 2 Sequential write-Random read type time division switch circuit 3 Control memory 4 Extended control memory 5 Extended control memory valid instruction memory 6 Even surface selection circuit 7 Odd surface selection circuit 8 Selection circuit 10 Even surface upper / lower Selection circuit 11 Odd number upper / lower selection circuit 12 Frame upper half information selection circuit 13 Frame lower half information selection circuit 33 _0, 33 ₁ Sequential write-random read type time division switch circuit 35 Extended CM effective display memory 36 Control memory 37 Extended control memory 38, 39 Address selection circuit 40 _0, 40 ₁ High / Low selection circuit 41L Frame selection circuit Low 41H Frame selection circuit High

Claims (2)

[Claims] 1. Corresponding one of a sequential write-random read type time division switch circuit (1, 2) composed of two planes in response to communication information of an input highway exchange basic unit in response to frame information. A control memory that stores the upper / lower selection information and the read address of the communication information of the exchange basic unit in a pair format in the speech path switch for time-division exchange input to the time-division switch circuit and outputs it at the output time to the output highway. (3), extended control memory (4) that stores the upper / lower selection information of the communication information of the exchange basic unit, and the read address in a pair format and outputs at the output time to the output highway, and the extended control memory valid information An extended control memory validity instruction memory (5) for storing the frame, and a frame connected to the control memory (3) and the extended control memory (4). An even-numbered plane selection circuit (6) for selecting both pieces of information in the pair format for the even-numbered plane in response to the information and supplying them to the even-numbered plane time division switch circuit (1), and the control memory (3), And an extended control memory (4) for selecting both pieces of information in the pair format for odd number planes in response to the frame information and supplying them to the odd number side time division switch circuit (2). From the circuit (7), the frame information, the upper / lower selection information read from the even-numbered plane selection circuit (6) and the odd-numbered plane selection circuit (7), and the extended control memory validity instruction memory (5) Upper half information of the even-numbered surface time divisional switch circuit (1) in response to the read extended control memory valid information,
And the lower half information, the upper half information of the odd numbered time divisional switch circuit (2), and the upper half information of the lower half information and the selection circuit (8) for selectively outputting the lower half information. A time division speech path switch characterized by being provided. 2. The time division speech path switch according to claim 1, wherein the selection circuit (8) is connected to the upper half information output and the lower half information output of the even numbered time division switching circuit (1), and an even number. Even number which selectively outputs the upper half information or the lower half information output from the even number surface time division switch circuit (1) in response to the upper / lower selection information output from the number selection circuit (6) Number upper / lower selection circuit (1
0) and the upper half information output and the lower half information output of the odd number side time division switch circuit (2), and in response to the upper / lower selection information output from the odd number side selection circuit (7). An odd-numbered surface upper / lower selection circuit (11) which selectively outputs upper half information or lower half information output from the odd-numbered time-division switch circuit (2), and an even-numbered time-division switch circuit (11). 1) upper half information output, odd number side time division switch circuit (2) upper half information output, and even number side upper / lower selection circuit (1
0) and the output of the odd number upper / lower selection circuit (11), and the upper half information in response to the frame information and the extended control memory valid information read from the extended control memory valid instruction memory (5). A frame upper half information selection circuit (12) for outputting the lower half information output of the even-numbered time-division switch circuit, the lower half information output of the odd-numbered time-division switch circuit, and an even-numbered upper / lower selection circuit (10) and in response to the extended control memory valid information read from the frame information and the extended control memory valid indication memory (5), which is connected to the output of the odd number upper / lower selection circuit (11). A time division speech path switch comprising a frame lower half information selection circuit (13) for outputting lower half information.