JPS62248397A - Time division exchange system - Google Patents

Abstract

PURPOSE:To prevent the deterioration in the processing capacity of a CPU due to a queuing by setting change data a channel converting control memory which is not used at present from a channel interface side only to an address to be changed of the channel converting control memory by the connection of a calling. CONSTITUTION:When the connection request of the calling is generated in a frame in the data of a data buffer control memory 20, all the address are copied from the channel converting control memory 30 to a memory 31. Then, selectors 44, 49 are changed over to the channel interface circuit 6 side and the change data is set asynchronously with the reading and writing cycle of a data buffer memory 1 with respect to the address of the channel converting control memory 31 to be changed. The selectors 44-49 are changed over at the leading of the optional frame after the setting is completed. Thereafter, the exchange operation is kept by using the channel converting control memory 31. Accordingly, the set data of the channel converting control memory is not required and the queuing is not required for setting the data to the channel converting control memory.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a time division exchange system, and more specifically, in terms of a data buffer memory that stores communication information for one frame.
The present invention relates to a time-division switching system that quickly sets channel conversion data without waiting in a time-division switching system that allows the channel position of a call to be moved during communication.

[Conventional technology]

For example, TDMA (Ti+*a Di
In the (multiple access) method, each channel in one frame is divided into a block of multiple channels, and the channels within a block can be shared only by members included in the group assigned to that block. , and other groups use time division multiplexing such that the channels within that block cannot be used.

In such a system, in order to improve line efficiency, for example, by calling from group γ, the number of channels in the block allocated to group α is reduced, and the number of channels is reduced by that amount. In order to increase the number of channels of blocks allocated to group γ, it is necessary to move the position of each block and the channel position of the call in progress to connect the call. On the other hand, in a normal T single-stage switch (sequential write random read or random write sequential read), the sixth
If you move the channel position of a call during communication as shown in the figure,
The data buffer memory may be overwritten or read blankly, resulting in a momentary interruption of communication.

Conventionally, in order to realize this channel movement of a call during communication without momentary communication interruption, a communication path configuration as shown in FIG. 7 has been proposed (Japanese Patent Application No. 46165/1982). In FIG. 7, 1 is a data buffer memory that stores communication information for one frame; 2 is a data buffer memory that stores communication information for one frame;
゜ and 21 are two-sided data buffer control memories that control read/write addresses of data buffer memory 1, and 3゜ and 31 are two-sided channel conversion controls that store channel conversion data on time division multiplex transmission paths. It is a memory, 4° to 4g are selectors, 5 is a counter, 6 is a communication path interface circuit, and 7 is a clock generation circuit. In addition, selectors 44, 4. Although there is an initial setting circuit for initial setting, it is omitted in FIG. Data buffer control memory 2°.

Address 21 is equivalent to the outgoing channel number.

The data is equal to the address number of the data buffer memory 1, and the channel conversion control memory 3°.

The address of 3□ is equivalent to the incoming channel number, and the data is equivalent to the outgoing channel number. However, when only one of the channel conversion control memories 3 and 31 is used to change the channel for one active call, the channel conversion data after the movement is set in the channel conversion control memory that is not in use. Channel conversion control memory is switched and used at the time of movement.

FIG. 8 shows an example of the exchange operation in the configuration of FIG. 7. Channel clock CHCK generated from clock generation circuit 7
Accordingly, the counter 5 receives a channel number signal CH-- for sequentially specifying the read address of the data buffer control memory 2 and channel conversion control memory 3, and a frame for switching each selector 4° to 4□ every frame. Generates clock FCK. In the initial setting, first, the selectors 47 to 41 degrees are set to the channel conversion control memory 3 degree side by the switching control line So from the communication path interface circuit 6. Further, the initial setting circuit 8 is activated by the initial setting circuit, and the selector 4. ．． 4. is set to the initial setting side, and channel numbers 0, 1, 2, . Set... In this configuration, the initial setting is completed in two frames, and thereafter the selectors 44, 4 . Switch each to the opposite side and start the exchange operation.

First, the two-sided data buffer control memory 2°.

21, the address of one data buffer control memory 2.degree. is specified by a channel number signal CH-N.alpha. Then, the communication information written in the previous frame is read from the address of the data buffer memory 1 specified by the data read from the data buffer control memory 2o, and the communication information of the current frame is written to the same address.The communication information of each channel is , the communication information of the previous frame is read and written to the empty address, so the write address is different for each frame. Therefore, in order to memorize the address where the communication information was written and output the written communication information to the specified output channel in the next frame, the data read from the data buffer control memory 2° (=the address where the communication information was written) is stored. data buffer memory 1
address) is the address of the channel conversion control memory 3° that is equal to the address value of the data buffer control memory 2° from which the data was read (=the incoming channel number that contained the communication information written in the data buffer memory 1). The data (=the channel number to which the communication information written in the data buffer memory 1 is to be output in the next frame) is stored in the address of the other data buffer control memory 21 (=the channel number to be output in the next frame). I'll keep it.

The above operation is repeated for one frame, and in the next frame, selectors 4° to 4. After that, data is sequentially read from the data buffer memory 21 and the same operation as in the previous frame is repeated. 6, write data to any address in the channel conversion control memory 3°, and selector 4.
11 is for channel movement of 4 active calls.

In order to set the moved channel conversion data in the channel conversion control memory 31, the switching control line Sc is used to connect the address lines A, 1 to the channel conversion control memory 31.

In the example of FIG. 8, calls A, B, and C are placed in the incoming channel order A,
,B,C, the outgoing channel order B,C.

In order to convert into #n, the data buffer memory 1 stores the communication information of each channel at lower addresses A, .
, , reads communication information B 11-1 of frame #n-1 stored at address "2" of data buffer memory 1, and reads communication information An of frame #n.
The caller writes the incoming channel number 4601g, as indicated by the channel conversion control memory 3°.

Perform channel conversion for channel number “3”, therefore,
Address “2” of data buffer memory 1 in frame #n
The communication information An written in " is.

Data “2” read from the data buffer control memory 2° so as to be output to the output channel “3n” in frame #n+1 is changed by the data 11311 contained in the address It OUT of the channel conversion control memory 3°. Address “3” of one data buffer control memory 21
” is written.

By repeating the above operations for one frame, all the data in the data buffer control memory 21 is created, and in the ninth frame, the functions of the data buffer control memory 2 are switched and the same operations are repeated.

FIG. 9 shows an example of operation when moving the incoming channel position of a call in progress in the configuration of FIG.
This is an example in which the channel positions of each person are moved so that empty channel #1 is closed. Even after the channel change, call B must be converted to outgoing channel #0, so the data it
Set O#j. Similarly, data '11 It' is stored at the address "2" zt 3 t+ of the channel conversion control memory 3□.

Set "'2". Furthermore, for call A that does not undergo channel movement, the data in the channel conversion control memory 3 is set to the same address in the channel conversion control memory 3 as is.

FIG. 10 shows the initial setting of the channel conversion control memory 3 and the data setting method at the time of connection. (1) is the initial setting, and data equal to the address value is set in each address of the channel conversion control memory. (2) shows a method of setting data in the channel conversion control memory when connecting call A from the initial setting state. Call A is incoming channel #
In order to convert from O to output channel #3, the data at address "0" in the channel conversion control memory is changed to "3", and the address "0" containing data equal to output channel number #3 is changed to "3".
Change the data of “3” to “0”.

(3) further shows a method of setting data in the channel conversion control memory when connecting call B. Similarly to (2), call B
changes the data at address “2” of the channel conversion control memory to “0” in order to convert input channel #2 to output channel #0, and changes the data at address LL3II containing data equal to output channel number #0 to “0”. Change the data to 812 II.

Generally, when converting from input channel #i to output channel #j, address 11 i of channel conversion control memory
” and the address “k” containing data Z.
Set data to the location address. As shown in FIG. 11, there are three possible positional relationships between the two write addresses and the read address to the channel conversion control memory.

FIG. 11(1) shows two write addresses i.

This is the case where the read address value m is read out, and the channel conversion control memory address “i PI, 11 #j
Since the newly set data "j" u Q ## is read from the next frame, the conversion from input channel #i to output channel #j is performed from the next frame.

FIG. 11 (2) shows that the write address value i at two locations is ≧
This is the case of the read address value m, and the newly set data ゛tjt'', ``Ω''' at the addresses ``i''p, 11klt of this channel conversion control memory are read out during the current frame, so the input channel # The conversion from i to outgoing channel #j is performed from the current frame.

FIG. 11 (3) shows a case where the lower positioning address value i ≦ the readout address value m is less than the upper positioning address value, and data "j" set at address 41 "i" is read from the next frame, Data “2” set to address “k”
” is read from the current frame. Therefore, during the current frame, the same data “
a” is read out, which means that after the data at address 41 i” of one data buffer control memory 2 is written to address “Q” of the other data buffer control memory 21, the data buffer control memory 2 is read out. Data buffer control memory 2 is stored at the same address “Q jt” in memory 2□.
The data at address “k” in ゜ is overwritten, and the data at address “k” in data buffer control memory 2゜ is overwritten.
Nothing is written to the address "j" of the data buffer control memory 2□ where the data of "k" should be written.
The data from two frames ago remains, and from the next frame onward, this failure spreads to all addresses in the data buffer control memories 2° and 21.

[Problem that the invention seeks to solve]

As can be seen from the above explanation, in the call configuration shown in FIG. 7, when data is set in the channel conversion control memory for call connection, each time conversion control information for one channel is set. Figure 11 (1).

It is necessary to wait until the relationship (2) is satisfied, and the channel interface circuit has a buffer that temporarily stores data to be set in the channel conversion control memory, a read address of the channel conversion control memory, and a buffer that temporarily stores the data set in the channel conversion control memory. It is necessary to have a circuit that compares the position with the write address to be set, and usually in order for the central control circuit (CPU) to recognize the success or failure of completing the data setting to the channel conversion control memory, There is a drawback that waiting for data setting causes a decrease in the processing capacity of the CPU.

It is an object of the present invention to solve the problem of conventional channel conversion control in a time-division switch channel configuration having a data buffer memory that stores communication information for one frame, two-sided data buffer control memory, and two-sided channel conversion control memory. Requires a buffer for data to be set in the memory and a position comparison circuit between the read address and the write address, and solves the problem that the processing capacity of the CPU is reduced due to waiting for data to be set in the channel conversion control memory. The purpose is to provide a split exchange method.

[Means and effects for solving the problem] The present invention sets channel conversion control information in the channel conversion control memory that is not in use even when a call is connected, and switches the channel conversion control memory for use. This is the most important feature. In this case, change data is set from the channel interface side to the channel conversion control memory that is not currently in use only for addresses that should be changed in the channel conversion control memory due to call connection, and for addresses that do not need to be changed. Copy data from the channel conversion control memory currently in use.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a time-division exchange communication channel configuration according to an embodiment of the present invention, in which 1 is a data buffer memory, 2° and 21 are data buffer control memories, 3o and 3□ are channel conversion control memories, and 4° to 21 are data buffer control memories. 4. 5 is a selector, 5 is a counter, and 6 is a communication path interface circuit.

The data in the data buffer control memory 2I specifies the read address (=write address) of the data buffer memory 1, and the data read from the data buffer control memory 2I is specified in the data in the channel conversion control memory 3. At the same time as writing to one data buffer control memory 21.

The data read from the channel conversion control memory 3 is transferred to the selector 4. ．． 4. The data is copied to the address of the other channel conversion control memory 31 that is equal to the address value of the channel conversion control memory 3° from which the data was read.

If a call connection request occurs during this frame, or if the channel position of the currently communicating call is to be changed, the above operations are repeated until the end of the frame, and the channel conversion control memory is transferred from channel conversion control memory 3° to 31, selectors 44, 4 . is switched to the channel interface circuit 6 side, change data is set to the address of the channel conversion control memory 31 to be changed asynchronously with the read/write cycle of the data buffer memory 1, and the change data of any frame after the setting is completed is set. At the beginning selectors 44-4. After that, the channel conversion control memory 31 is used to continue the exchange operation.

Note that the selectors 44 to 4. Although there are several possible methods of arranging and connecting the copy control methods other than the embodiment shown in FIG. 1, the same effect can be obtained as a copy control method.

FIG. 2 shows a time-division exchange channel configuration in another embodiment of the present invention. In the embodiment of FIG. 1, when changing the data in the channel conversion control memory, a request to change the data in the channel conversion control memory is After the occurrence, it is necessary to wait until the beginning of the next frame. The embodiment shown in FIG. 2 eliminates this waiting period of maximum one frame time. In FIG. 2, 1 is a data buffer memory, 2° and 21 are data buffer control memories, 311 and 3□ are channel conversion control memories, 4° to 411 are selectors, 5 is a counter,
6 is a communication path interface circuit, 9° and 91 are flag memories, and 10° and 1o□ are copy control gates. Flag memories 9° and 9□ are composed of 1 bit per address. Copy control gate 10°.

As shown in FIG. 3, 10□ is constituted by an AND circuit of the read/write clock R/W of the data buffer 1 and the data from the flag memory 9. However, in Figure 3, D0
~Dmax indicates a data line. This copy control gate is
If the copy permission data (for example, "0") is determined by 1-bit data in the flag memory, the copy control gate is opened;
Copy data for one address from one channel conversion control memo, and if copying is prohibited (for example, "1").

Close the copy control gate to prohibit copying.

In the embodiment of FIG. 2, selectors 44, 4 . 411 are switched in synchronization with the read/write cycle of the data buffer memory 1, and the change data setting cycle and one channel conversion control memory 3. Set data in the channel conversion control memory 3□ by time-sharing with the copy cycle from During the read cycle of data buffer memory 1 (at this point, selector 44°4 is set to 1).
It is set on the communication path interface circuit 6 side, and the selector 4
□. , 411 are connected directly to the channel conversion control memories 3°, 31 without passing through the copy control gates 10°, 101. ), channel conversion is performed by setting data for one address in channel conversion control memory 3 □ and setting copy-prohibited data “1゛′ in the address of flag memory 9 □ that is equal to the address value set with that data. Prevent data from being copied from the control memory 3° to this address in the channel conversion control memory 31. During the write cycle of the data buffer memory 1, data is read from the channel conversion control memory 3° and the address value from which the data was read is The above copying control is performed using the data at the address in the flag memory 91 equal to , and at the same time, the same address in the flag memory 9 is reset (that is, copy permission data "0" is written).

FIG. 4 shows a specific example of operation for setting data in the channel conversion control memory 31. First, in order to convert from input channel #0 to output channel #3.

Data "3" is set to address "O" of the channel conversion control memory 31, and data "1" is set to address "0" of the flag memory 91 (FIG. 4 (1)), and the next data buffer memory is set. In one read cycle, data “0” is written to address “3” of channel conversion control memory 3□.
'', and also set address 11 of the flag memory 91.
3" is set to data "1" (Fig. 4 (2)).

FIG. 5 shows an example of data copying from the channel conversion control memory 3° to the channel conversion control memory 31. Data “0” in the channel conversion control memory 3° is
Since the data at the address "0" of the channel conversion control memory 31 is "1", that is, new data is set at the address "0" of the channel conversion control memory 31, the copy control gate 101 prohibits copying. . At the same time, data is set to address “0” of flag memory 9° (fifth
T! I (1)), and the data "1" at address "1" in the channel conversion control memory 3 is stored in the flag memory 9. Since the data at address “1” is “O”, that is, the address “1” of channel conversion control memory 31
Since no new data is set in , it is copied through the copy gate 10□. At the same time, data “0” is set to address “1” of flag memory 9° (
Figure 5 (2)).

When the setting of data to the channel conversion control memory 31 is completed, the selector 4. ~4. Switch.

Switch the channel conversion control memory and continue the exchange operation. Selector 4 from this communication path interface circuit 6
．． In order to eliminate the switching designation of selectors 4 to 41, regardless of whether data is set in the channel conversion control memory, selector 4. ~4. are switched and used every frame, and channel conversion control memories 3° and 3□ each are further
As a surface composition.

When changing the channel position of one active call as in the conventional configuration shown in FIG. , channel conversion control memory 3°, 3
1 and continue the exchange operation.

In the embodiment shown in FIG. 2, copy control is performed by a flag memory and a copy control gate added to the channel conversion control memory on the side to be copied.

A similar effect can be obtained with a configuration in which copy control is performed using a flag memory and a copy control gate added to the channel conversion control memory on the copying side.

Furthermore, various methods can be considered for the arrangement and connection of the various selectors, but they all provide the same effect.

〔Effect of the invention〕

As explained above, according to the present invention, in a time-division exchange communication path configuration having a data buffer memory for storing communication information for one frame, two-sided data buffer control memory, and two-sided channel conversion control memory. , there is no need for a buffer for setting data in the channel conversion control memory, and there is no need to wait based on the positional relationship between the read address and the write address in order to set data in the channel conversion control memory.
This has the advantage of avoiding a decline in processing capacity.

The communication path configuration of the present invention is applicable to fields where TSSI of multiple calls is guaranteed, fields where weight, power consumption, and reliability are issues,
For example, it is effective when applied to a satellite-mounted exchange necessary for multi-beam satellite communication.

[Brief explanation of drawings]

1 is a diagram showing one embodiment of a time-division switch channel configuration according to the present invention, and FIG. 2 is a diagram illustrating another embodiment of the present invention.
FIG. 3 is a diagram showing a configuration example of a copy control gate, FIG. 4 is a diagram showing a specific example of data setting at the time of call connection in the time-division call path configuration of the present invention, and FIG. 5 is a diagram showing a time-division call configuration of the present invention. FIG. 6 is a diagram showing a specific example of data copying of the channel conversion control memory in FIG. Diagram showing movement. FIG. 7 is a diagram showing the communication path configuration of a conventional time-division switch; FIG. 8 is a diagram showing the switching operation in the configuration of FIG. 7; and FIG. 9 is a diagram showing the channel change of a call in progress in the configuration of FIG. 10 is a diagram showing the data setting method of the channel conversion control memory at the time of initial setting and call connection.
FIG. 1 is a diagram showing the positional relationship between data write addresses and read addresses of a channel conversion control memory. 1... Data buffer memory, 2°, 21... Data buffer control memory, 3°, 3
□...Channel conversion control memory, 4° to 411...
Selector, 5... Counter, 6... Call path interface circuit. 7... Clock decoration circuit, 8... Initial setting circuit. 9゜9□...Flag memory, 10,. 10□...Copy control gate. 1+ 10° Low INl'Q Low Nr'1 0-~h Figure 10 (N light: Lie Figure 11)

Claims (2)

[Claims] (1) A data buffer memory that stores data for one frame on a time division multiplex transmission path, and a two-sided channel conversion control memory that stores channel conversion data on the input and output time division multiplex transmission paths of the exchange; and a two-sided data buffer control memory that alternately controls the read and write addresses of the data buffer memory for each frame, and the control data read from the one-sided data buffer control memory causes the data buffer memory to be After reading the communication information written in the frame onto the time-division transmission path, the communication information of the current frame is written to the same address, and the control data read from the data buffer control memory is used to control the data buffer on the other side. In a time-sharing exchange method in which the data buffer control memory is set to an address (=channel conversion data) read from the channel conversion control memory on one side of the memory and the data buffer control memory is switched every frame, before setting new channel conversion data, After copying the current channel conversion data stored in the conversion control memory to the other channel conversion control memory, new channel conversion data is set in the copied channel conversion control memory, and the channel conversion control memory is switched. This is a time-sharing exchange method characterized by continuous exchange operation. (2) In the time division exchange method according to claim 1, a flag memory designating permission or prohibition of copying for each address between the channel conversion control memories and data read from the flag memory enable copying; It is equipped with a copy control gate that performs prohibition control, and when setting new channel conversion data by copying the channel conversion data read from the channel conversion control memory on one side to the channel conversion control memory on the other side, the new channel conversion data is copied. is set in the channel conversion control memory to be copied, and at the same time, copy prohibition data is set in the flag memory, and only the address where the new channel conversion data is set is prohibited from being copied by the control of the copy control gate based on the data in the flag memory. This is a time-division exchange method that creates channel conversion data for all channels, including new channel conversion data, and continues the exchange operation.