JPH01161950A - Buffer memory control system - Google Patents

Abstract

PURPOSE:To simultaneously attain access of write and readout and to suppress the increase in the memory capacity by jumping a write pointer to the next memory block when a readout pointer designates the memory block designated by the write pointer. CONSTITUTION:When a readout pointer 25 moves and designates the same memory block as the memory block designated by a write pointer 24, e.g., 22-1, a control is implemented to jump the write pointer 24. That is, since the write pointer 24 and the readout pointer 25 always exist in different memory blocks, the write access and readout access are applied simultaneously to attain high speed accessing. In case of jump of the write pointer 24, the address in the jumped original memory block is stored and the readout pointer 25 uses an address as an index to be jumped to the next memory block, then no contradiction takes place. Thus, the increase in the memory capacity is minimized.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a control method that allows high-speed access to buffer memory used in ATM switching channels, etc., which allows simultaneous write and read access and minimizes the increase in memory capacity. In this buffer memory, data is written to a write address indicated by a write pointer, and the data is read by indicating a read address by a read pointer in the writing order, and each write or read operation is independently performed. A plurality of accessible memory blocks are prepared, each of the write pointer and the read pointer is circulated asynchronously among the plurality of memory blocks to designate an address within each memory block, and the address specified by the write pointer is specified. When the read pointer points to a memory block, the write pointer is jumped to the next memory block to perform control so that write and read accesses do not occur simultaneously on the same memory block.

[Industrial application field]

The present invention is an ATM (^5ynchronize Tr).
(ansferMode; asynchronous transfer type) A control method that allows high-speed access to buffer memories used in switching communication paths, etc. [Prior technology] ATM line multiplexing method transfers packet data from each subscriber to a predetermined channel on a time-division highway. By time-division multiplexing, fixing the route, and performing exchange using hardware switching, real-time performance is much higher than that of normal packet communication, and communication speed conversion, data communication between different types of subscribers (terminals), This method also provides various services such as formant conversion and information storage function.

In the ATM exchange channel, fixed-length packet data (cells) with a tag containing the destination of the outgoing highway 2 are time-division multiplexed onto any channel on any incoming highway 1 shown in FIG. It is necessary to time-division multiplex it to any channel on any outgoing highway 2. in this case,
In each channel on the outbound highway 2, data 6 (cells) written from the inbound highway 1 are transferred to the first inlet corresponding to the outbound highway 2 determined by the tag so that the cells from the inbound highway 1 do not compete (collide).・
First-out type buffer memory (hereinafter referred to as F
(referred to as IFO) and accumulates them. And each F
The cells stored in the IFO 3 are read out as read data 7, time-division multiplexed onto a desired channel on the output highway 2, and cells are exchanged between the input and output highways. Here, writing the write data 6 to the FIFO 3 or reading the read data is performed by providing a write pulse 8 or a read pulse 9, respectively, from the write pulse line 4 or the read pulse line 5, which are connected to a control circuit (not shown). To do this.

The FIFO 3 in the ATM exchange channel is required to perform faster processing in order to efficiently process high-speed information.

FIG. 7 shows the configuration of a first conventional example of the FIFO 3 shown in FIG. Since this FIFO uses the memory 10, the write data 6 is written into the first-generation flip-flop 11 according to the write pulse 8, and the write pulse 8 is also input to the cent terminal S of the flip-flop 12 and held there. Then, when the read pulse 9 is not input, the AND gate 13 is turned on, and the write pulse sent to the flip-flop N2 is transferred from the output terminal Q to the memory 1.
Enter 0. As a result, the write data 6 held in the flip-flop 11 is written to the memory IO. On the other hand, during reading, the read pulse 9 is applied to the memory 10.
The read data 7 is read out. That is, write and read accesses to the memory 10 are not performed simultaneously.

Next, FIG. 8 shows the configuration of a second conventional example of the FIFO 3 shown in FIG. In this example, the memory has a two-sided structure, as shown by the dashed lines 14 and 15. For example, memory 1 on the plane 14
If the write pointer 18 is on the 6 side and the write data 6 is being written, the read pointer 19 is placed on the memory 17 on a different side 17 and the read data 7 is read out (solid line 20). , the same operation is performed by switching the plane indicated by the write pointer 18 and the read pointer 19 (broken line 21).

Note that the write pulse 8, read pulse 9, etc. in FIG. 5 are omitted.

[Problem that the invention seeks to solve]

However, in the above conventional examples, first, in the first conventional example shown in FIG. 7, even though write and read access can be performed asynchronously externally, writing and reading cannot be performed simultaneously internally, There is a problem in that the access speed for writing or reading from the outside is half of the access speed for IO.

On the other hand, in the second conventional example shown in FIG. 8, writing and reading accesses are always performed on different surfaces, so the access speed of the memory 16 or 17 can be maintained as it is for external writing or reading. The access speed can be increased, and the access speed can be increased. However, as shown in Figure 8 16 and 17, the memory capacity must be twice the required amount, especially when a large number of FIFO3s are required, such as the ATM exchange channel in Figure 6. , which had the problem of high cost.

Both the first and second conventional examples have similar problems when attempting to use FIFO in a channel other than the ATM exchange channel shown in FIG.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, it is an object of the present invention to provide a buffer memory control method that allows simultaneous write and read access and minimizes the increase in memory capacity.

[Means for solving problems]

FIGS. 1(al) and 1(bl) show diagrams explaining the principle of the present invention.

The present invention is composed of a plurality of memory blocks 22-θ to 22-N, and data 23 (shaded area) is written to a write address indicated by a write pointer 24, and a read address is indicated by a read pointer 25 in the writing order. Read data 23.

At this time, each of the write pointer 24 and the read pointer 25 is asynchronously circulated between the memory blocks 22-θ to 22-N as shown at 26 and 27 in ta+ in FIG. 22-N.

If the read pointer 25 moves as shown at 28 in Figure 1) and points to the same memory block as the write pointer 24, for example 22-1, the write pointer 24 is Control is performed to jump as shown in FIG.

[For production]

With the above configuration, the write pointer 24 and the read pointer 25 always exist in different memory blocks, so
Write access and read access can be performed simultaneously, and access speed can be increased.

At this time, when the write pointer 24 jumps as shown at 29 in Figure 1), the address in the memory block from which it jumped is held, and the read pointer 25 uses this address as an index to jump to the next memory block. If you do this, inconsistent behavior will not occur.

In addition, if the number of memory blocks at this time is N that corresponds to the required memory capacity, then if N1,010 are prepared, the required amount of data can always be held, and write and read access can be performed at the same time. I can do it.

This makes it possible to minimize the increase in memory capacity.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail.

In the embodiment of the present invention, an example will be shown in which the present invention is applied to a first-in, first-out type buffer memory (FIFO) used in an ATM switching channel. Since the overall configuration of the ATM exchange channel is the same as that explained in FIG. 6, its explanation will be omitted.

Next, FIG. 2 is a diagram showing an embodiment of the FIFO 3 of FIG. 6 according to the present invention. This embodiment has four memories 30 #0 to #3 having the same memory capacity, and the memory capacity required to hold the write data 6 is three of the memories 30.
It is an individual portion. In other words, it is configured with one more piece.

The written data 6 from the input highway 1 (Figure 6) is
The data is written to any one of memory registers #0 to #3 of the memory 30 selected by the write pointer WP from the write counter 32. Further, read data 7 is read out from any one of the memory addresses #0 to #3 of the memory 30 selected by the read pointer RP from the read counter 33, and the read data 7 is read out from the output highway 2 (FIG. 6). is read out.

Next, the write counter 32 and the read counter 33 are
Write pulse 8 from write pulse vA4 (Figure 6)
and read pulse 9 from read pulse line 5 (FIG. 6)
It is controlled by a pointer control section 31 that operates according to the following. Also, from the pointer control unit 31, the memory 3 of #0 to #3
0 is a write-protection flag Full (hereinafter referred to as Full).
l flag), and a read prohibition flag Emp.
ty (hereinafter referred to as F, mp ty flag) is supplied.

The operation of the embodiment having the configuration shown in FIG. 3 will be explained below. First, FIGS. 3(al) and (b) are diagrams showing the address structure of the write pointer WP1 from the write counter 32 in FIG. 2 and the read pointer RP from the read counter 33. Pointer W
P consists of the upper 2 bits of the write memory number address configuration A and the other lower focused part of the write memory address WPA. There is a decoder (not shown) in the memories 3o of #0 to #3 in FIG. 2, and the decoder decodes the write memory number address WPI4 in the write pointer WP,
Only the memory 3o that matches #3 has the write pointer WP
The write address in the memory is specified by inputting the write address WPA in the memory.

Similarly, in FIG. 3 (bl), the read pointer RP is the read memory number address RP of the upper 2 bits, and the read memory address RPA of the other lower focused part.
Consisting of Then, the decoders #0 to #3 in the memory 30 in FIG.
Only the memory 30 that matches #3 has the read pointer WP
The read address in the memory is specified by inputting the address RPA in the read memory.

According to the address structure shown in FIG. 3, if memory 30 #1 is specified by the write memory number address wp of the write pointer WP, the write counter 32 is incremented, and the write memory address WPA of the write pointer WP specifies #1. When the write memory address WPA is incremented to the final address of the memory 30 #1 and then further incremented by +1, the write memory address WPA becomes O and the write memory number address WPM is incremented by +1, so the process moves to the start address of the memory 30 #2. Furthermore, if the address is further incremented by 1 after being incremented to the final address of the memory 30 of #3, both the write memory internal address WP^ and the write memory number address W P M become 0, so the start address of the memory 30 of #0 is Move. As described above, the write pointer WP is circulated by the write counter 32 in the order of #O-#1→#2-#3→#O→... in the memory 30. That is, the write memory address WP.

has the number of bits that can just specify the internal address of each memory 30 #0 to #3, and the write memory number address WPM has the number of bits that can just specify the memory numbers #0 to #3, that is, the size of 2 bits. It is. The above function is the same for the read pointer RP.

Also, the address W in the write memory of the write pointer WP
PA and write memory number address WP0, read memory address RP of read pointer RP, and read memory number address RP.

is rewritten as described below by controlling the write counter 32 and read counter 33 from the pointer control unit 31.

Below, the specific operation in Figure 2 will be explained in Figure 4 ta+~
The explanation will be given using the operation explanatory diagram of (3) and the operation flowchart of FIG. 5(a) and fbl. In addition, Fig. 4 (al
-01 is a diagram showing the states of the memories 30 #0 to #3 in FIG. In the following, unless otherwise specified, the hardware is shown in Figure 2, and the operation sequence of Sl, 82, etc. is shown in Figure 5 (al, fb
See l.

First, in the initial state, since both the write counter 32 and the read counter 33 are cleared, both the write memory number address WP1 of the write pointer WP and the read memory number address RP of the read pointer RP shown in FIG. As shown in FIG. 4 (al), memory 30 #0 is specified, and write memory address WPA and read memory address RPA indicate the start address of memory 30 #0. At this time, the Empty flag output from the pointer control unit 31 is "l", and the Full flag and Jump flag are both "0".When the Empty flag is "l", the memory #0 to #3 Since no data is held in any of the 30 addresses and data cannot be read, the read operation is prohibited.

If the Empty flag is "0", reading is possible.

Further, when the Full flag is '1', all addresses #0 to #3 of the memory 30 are filled with data, and data cannot be written, so the write operation is prohibited. If the Full flag is "0", writing is possible. Ju
The mp flag will be described later.

Now, in state B1 of FIG. 4 (al), since the Empty flag is "1", only a write operation is possible.

In this case, route 1 is selected in the operation flowchart of FIG. 5011.

Route l is 5l-32-33-34→S in Figure 5 011
The operation sequence is 5→S7→S8.

That is, when the write pulse 8 is input to the pointer control unit 31 in state 1 of FIG. 4 (Sl), the write pointer W
Write memory address WPA of memory 30 of #0 selected by P's write memory number address WP)l
Write data 6 is written to the start address indicated by (S2).

After that, the pointer control unit 31 increments the write power counter 32 and the old write pointer WP is increased by +1 (S3
), the Empty flag is set to 0'' (S7 via S4 and S5), and the state waits for input of the next write pulse 8 (S8).

By repeating route 1 above, Figure 4! As shown by diagonal lines in state 2 of al, write data 6 is written to memory 30 #0 while address WP^ in the write memory is sequentially incremented.

When it comes to the state B2 of FIG. 4(a) or (bl), Emp t
Since the y flag has become "0", reading becomes possible, and when the read pulse 9 is input to the pointer control unit 31, path 2 is selected in the operation flowchart of FIG. 5 (011).

Route 2 is from 59-3IO → 311 → 51 in Figure 5 (bl)
The operation sequence is 4-S15→516→317→S20.

That is, when the read pulse 9 is input to the pointer control unit 31 in state 2 of FIG. 4 [b] (S9), first the write operation is performed in the #0 memory 30 selected by the read memory number address RP of the read pointer RP. Memory address W
Read data 7 from the start address indicated by PA
is read out (S10).

After that, the pointer control unit 31 increments the read counter 33 and the read pointer RP is incremented by 1 (3
514 via 11).

Further, the pointer control unit 31 controls the write count 32 to set the write memory number address w of the write pointer WP.
p, is +1, the address WPA in the write memory is set to O, and the write pointer WP is jumped to the start address of the memory 30 of #1 as shown in state 3 of FIG. 4 (bl).At this time, the Jump flag is set to The jump is recorded as "1", and the address in the memory 30 of #0, which was indicated by the write memory address WPA at the time of the jump, is stored as the jump source address WPo (S15
．． (via 316 to 317), and after this operation, it enters a state of waiting for input of the next read pulse 9 (320).

As described above, since the memory number of the memory 30 indicated by the write memory number address WPM of the write pointer WP and the read memory number address RP of the read pointer RP changes, from now on, the write operation of the write data 6 and the read data file read operations can be performed independently and asynchronously for different memory numbers.

For example, in state B3 of FIG. 4(b) or (e), when the readout pulse 9 is input to the pointer control unit 31, the fifth
Route 3 is selected in the operation flowchart of FIG. 3(b).

Route 3 is shown in Fig. 5 (BL S9→5IO-5ll→S1
The operation sequence is 2→S14→315→S18→320.

That is, when the read pulse 9 is input to the pointer control unit 31 in state 3 of FIG. Memory address RP
Read data 7 is read from the address indicated by a (
S10).

After that, the pointer control unit 31 increments the read counter 33 and the read pointer RP is increased by +1 (Sl
l, 314 via S12), waits for input of the next read pulse 9 (520 via S15.318),
Note that since the Full flag is originally "θ", 318 in Fig. 5 (mountain) has no special meaning. 318 will be described later.

On the other hand, in state 3 of TCI in FIG. 4, when the write pulse 8 is manually applied to the pointer control unit 31 in parallel with the read pulse 9, path 4 is selected in the operation flowchart of FIG. 5(a).

Route 4 is 5l-32-33-34-3 in Figure 5 (al.
The operation sequence is 8.

That is, first, in state 3 of FIG. 4 tc), the pointer control unit 3
When the write pulse 8 is input to 1 (Sl), the write memory number address wp of the write pointer WP, and the write memory internal address WPA of the #1 memory 30 selected by 4.
Write data 6 is written to the address indicated by (S2
).

After that, the pointer control unit 31 increments the write counter 32 and the write pointer WP is increased by +1 (S3
), it enters a state of waiting for input of the next write pulse 8 (S8 via S4).

As described above, the write operation of the write data 6 and the read operation of the read data 6 are performed independently for each of the #1 and #O memories 30.

Next, in state 4 of FIG. 4(C), the path 3 is repeated, and the address #0 in the memory 30 indicated by the read memory address RPA of the read pointer RP is changed to the jump source address WP6 (see FIG. 4). (Refer to bl) When a new read pulse 9 is input after moving one position before the
Route 5 is selected in the operation flowchart of FIG. 5(b).

Route 5 is S9→310-S9→310 in Fig. 5 (bl)
The operation sequence is -S13→315→S16→517→S20.

That is, in state 4 of FIG. 4(C), after the address RPA in the read memory has moved one place before the jump source address WP0 (not specifically shown), the pointer control unit 3
When the read pulse 9 is input to 1 (39), the read memory address RPa of the #0 memory 30 selected by the read memory number address RPM of the read pointer RP =
Read data 7 is read from WPo 1 (S
IO).

As a result, the data stored in the memory 30 of #0 becomes empty, so the pointer control unit 31 controls the read counter 33 to increase the read memory number address RP of the read pointer RP by 1 and read the memory address RP.
A is set to 0, and the read pointer RP is jumped to the first address of the memory 30 #1 as shown in state 5 of fd+ in FIG. At this time, the Jump flag is returned to "θ" (513 via 311 and S12).

Through the above operation, the read memory number address RP14 of the read pointer RP and the write memory number address WP14 of the write pointer WP point to the same memory 30 of #1, so the pointer control unit 31 controls the write counter 32 to set the write pointer WP. The write memory number address WPM is +1 and the address WPA in the write memory is O.
Then, as shown in FIG. 4 (state 6 of dl), the write pointer WP is jumped to the start address of the #2 memory 30. At this time, the Jump flag is set to 'l' again and the jump is memorized. , memory 30 of #l pointed to by address WP in write memory when jumping.
The address within is stored as the jump source address wp (517 via S15.316). After this action,
Waiting for input of next read pulse 9 (S20)
.

As described above, when the read pointer RP moves to the #1 memory 30 where the write pointer WP exists,
By immediately jumping the write pointer RP to the next #2 memory 30, the write operation of the write data 6 and the read operation of the read data can be performed independently again.

As a result, when the read pulse 9 is input to the pointer control unit 31 in the state Li6 of FIG. 4(d), as shown in FIG.
Similarly to the case of C1, the path 3 is selected in the operation flowchart in FIG.
When the write pulse 8 is inputted in parallel with this, the path 4 is selected in the operation flowchart of FIG. 5 Tal as in the case of FIG. 4(C). , write data 6 are sequentially written into the #2 memory 30, and the state changes as shown in B7 in FIG.

In addition, in state s7, the write memory address WPA of the write pointer WP is incremented by the write counter 32, and the write memory number address WP6 is incremented by 1 beyond the final address of the memory 30 of #2, and the write memory address WPA is Because it becomes 0 (Fig. 3 (
al), the write pointer WP has moved from #2 to #3 memory 30.

Then, as shown in state 7 of FIG. 4(e), the address in the memory 30 of #1 indicated by the read memory address RP^ of the read pointer RP is the jump source address WPo.
(After moving one position in front of FIG. 4 (see dl), when a new read pulse 9 is input, path 6 is selected in the operation flowchart of FIG. 5 (bl).

Route 6 is S9 → 310 → 311 → S1 in Figure 5 tb)
The operation sequence is 2→S13→315→S18→S20.

That is, in state 7 of FIG. 4 (el), after the readout memory address RPA has moved one place before the jump source address WPo, when the readout pulse 9 is input to the pointer control unit 31 (S9), the readout pointer RP changes. The read data 7 is read from the read memory address RPa = WPo -1 of the #0 memory 30 selected by the read memory number address RP, 4. (SIO).

As a result, the data stored in the #1 memory 30 becomes empty, so the pointer control unit 31 controls the read counter 33 to increase the read memory number address RP of the read pointer RP by 1 and read the memory address RP.
A is set to 0, and the read pointer RP is jumped to the first address of the memory 30 of #2 as shown in B8 of FIG. via 513).

In the above operation, the read memory number address RP of the read pointer RP and the write memory number address WPo of the write pointer WP still point to different memory numbers #2 and #3 of the memory 30, so the pointer control unit 31 continues to the next step. It enters a state of waiting for input of read pulse 9 (520 via S15 and S18).

Therefore, when the write pulse 8 is input to the pointer control unit 31 in the state B7 shown in tel of FIG. 4 in parallel with the above operation, the path is 4 is selected, write data 6 is sequentially written to the memory 30 of #3, and as shown in FIG.
The shape of el changes as shown in B8.

From state B8 in FIG. 4(e), a write pulse 8 is further input to the pointer control unit 31, and the address WPA in the write memory of the write pointer WP is incremented by the write counter 32. When the address is exceeded, the 2-bit write memory number address WPH is incremented by 1, exceeds 3 (corresponding to #3), and becomes 0 (#3).
(corresponding to 0), and write memory address WPA also returns to O.
Therefore, the write pointer WP moves from #3 to the memory 30 of #0. Furthermore, in the same way, cross #O and #1
The state is moved to the memory 30, and changes as shown in state 9 in FIG. 4(f).

Also, in parallel with this, when a read pulse is input to the pointer control unit 31 in state 8 of FIG. 4(e), the fourth
The read data 7 is read out from the #2 memory 30 in the same manner as in the case shown in FIG. In this case, unlike the case of TO+ in Figure 4, the Jump flag is 0'', so the jump flag in Figure 5 (bl
In the operation flowchart, the following route 7, which is slightly different from the route 3 described above, is taken.

In other words, route 7 is shown in Figure 5 (bl(7)S 9-310
The operation sequence is →S11 →S12 →S14 →S15 →S18 →S20.

The only difference between this route 7 and the route 3 described above is that S11→S14 in FIG.

The change from state B8 in FIG. 4(e) to state 9 in FIG. 4(f) occurs more frequently in write access than in read access, and the write pointer WP moves to the read pointer R.
It is now catching up with P. And Fig. 4 (fl
In state 9, the address indicated by the write memory address WPA of the write pointer WP is the memory 3 of #1.
It shows the final address of 0. In this state, when a write pulse 8 is further input to the pointer control section 31, path 8 is selected in the operation flowchart of FIG. 5 (al).

Route 8 is 5l-82-33-84→S in Figure 5+al.
The operation sequence is 5→S6→S8.

That is, when the write pulse 8 is input to the pointer control unit 31 (Sl) in state B9 of FIG.
Write data 6 is written to the final address of the memory 30 indicated by the write memory address WPA (S2).
.

After that, when the pointer control unit 31 increments the write counter 32 and the write pointer WP is incremented by 1 (S3), the write memory number address WPM is incremented by 1 and the address in the write memory is exceeded because it exceeds the final address of the memory 30 of #1. When WPA becomes 0, write pointer WP moves to #2 memory 30 where read pointer RP exists.
It moves to . As a result, the pointer control unit 31
Set the ull flag to “1” (S6 via S4 and S5)
, enters the input waiting state (S8).

As the Full flag becomes “l”, #0 to #
Subsequent writing to all memories 30 of 3'
Read operations are inhibited to prevent memory 30 from overflowing.

After the write operation is inhibited in state 10 of FIG. 4(f), when the read pulse 9 starts to be input to the pointer control unit 31, the read data 7 is changed to #2 in the same manner as in the case of C1 in FIG. 4 (gl
It changes like O-state all. In this case, unlike the case of FIG. 4 (C1), the Full flag is "1" and the read memory number address RP.

- Since the write memory number address is WP9, in the operation flowchart of FIG. 5 (bl), unlike the route 3, the following route 9 is taken.

That is, route 9 is S9→310→311 in FIG.
The operation sequence is →S14→S15→S16→S20.

This route 9 is different from the route 3 described above because 315→S18→S20 in FIG.
20, but the actual operation is the same.

FIG. 4 (In the phantom state e, 11, the read pointer R
The address indicated by the read memory address RPA of P is:
The final address of the memory 30 of #2 is shown. In this state, when the read pulse 9 is further input to the pointer control unit 31, path 7 is selected in the operation flowchart of FIG. 11, when the read pulse 9 is input to the pointer control unit 31 (S9), the read pointer RP
The read data 7 is read from the final address indicated by the read memory internal address RPA of the #2 memory 30 selected by the read memory number address RP (SIO
).

Thereafter, when the pointer control unit 31 increments the read counter 33 and the read pointer RP is increased by 1 (
514), the final address of the memory 30 of #2 is exceeded, so RM is +1 and the read memory internal address RPA becomes 0, and as shown in FIG. 4 (phantom state 12), the read pointer RP moves to the #3 memory 3o, which is different from the #2 memory 30 where the write pointer WP exists.

As a result, the pointer control unit 31 sets the Full flag to 1.
818), the write prohibition is canceled, and the state is set to wait for input (3.20).

As a result of the above operations, there is enough room to write the write data 6 into the memory 30, so that the write operation of the write data 6 and the read operation of the read data 7'' can be performed independently again.

As a result, when the read pulse 9 is input to the pointer control unit 31 in the phantom state 12 of FIG.
Similarly to the case of state 9 of 1, the path 7 is selected in the operation flowchart of FIG.
are sequentially read out from the memory 30 of #3, and when the same write pulse 8 is input in parallel with this, as shown in FIG.
In the operation flowchart of In), the path 4 is selected, and the write data 6 is sequentially written into the memory 30 of #2, changing as shown in FIG. 4 (state 13 of hl and state 113i14).

Furthermore, in a similar manner, the state 15 of FIG. 4(1) changes, and the address RP in the read memory of the read pointer RP changes.
The address indicated by A indicates the final address of the memory 30 of #2, and is changed from state 13.14 in FIG. 4(b) to state 13.14 in FIG.
) to state 15 occurs more frequently for read accesses than for write accesses, and the change of read pointer RP to state 15 occurs more frequently for read accesses than write accesses.
has caught up with the write pointer WP. In this state, when the read pulse 9 is further input to the pointer control section 31, the path 10 is selected in the operation flowchart of FIG. 5(b).

Route 10 is S9→310→S11→3 in FIG. 5(b).
The operation sequence is 14→S15→316→319→S20.

That is, in state 15 of FIG. 4(1), the pointer control unit 31
When the read pulse 9 is manually applied (39), the read memory number address RPM of the read pointer RP selects #
The read data 7 is read from the final address indicated by the read memory internal address RPA of the memory 30 of No. 2 (S
10).

Thereafter, when the pointer control unit 31 increments the read counter 33 and the read pointer RP is increased by 1 (
514), the read memory number address RP is +1 and the read memory internal address RPA becomes O because it exceeds the final address of the memory 30 of #2.
The read pointer RP matches the write pointer WP on the memory 30 of #3. As a result, pointer control unit 3
1 sets the Empty flag to "l" (519) via S15 and S16, and enters an input waiting state (S20).

As the Empty flag becomes “1”, #O~
Subsequent read operations for all the memories 30 in #3 are prohibited to prevent empty data from being read from the memories 30.

In state 16 of FIG. 4 (11), only the write operation is possible. Therefore, when write pulse 8 is input to the pointer control unit 31 in this state, as in the case of FIG. In the operation flowchart, the path 1 is selected and the write data 6 is written to the memory 30 of #3.
are sequentially written into the state, and change as shown in state 17 in FIG. 4(J). At this time, Emp t is set by S7 of Tal in FIG.
The y flag is returned to "0" and the read prohibition is canceled.

When the state Li17 in FIG. 4 ('') is reached, reading becomes possible again, and when the read pulse 9 is input to the pointer control unit 31, the 5
In the operation flowchart of FIG. As shown in state alB, the write pointer WP is jumped to the first address of the memory 30 of #O, the Jump flag is set to 111, and the jump source address wp is stored.

Thereafter, the first-in/first-out write/read operations are controlled by repeating the same operations as in FIGS. 4(a) to 4(J). At this time, as described above, the pointer control unit 31 performs control so that the read pointer RP and write pointer WP always exist at different memory numbers. As a result, write access and read access can always be performed independently, so each memory 3o from #0 to #3
External write and read accesses can be performed asynchronously at an access speed of .

At this time, if the amount of buffering data required in each FIFO 3 in FIG. 6 is three memories 30 in FIG.
If there are four of 3, it is possible to control the read pointer RP and write pointer wP so that they always exist at different memory numbers.

Therefore, in the present invention, the increase in memory capacity can be minimized compared to the second conventional example shown in FIG. 8, etc.

Note that the operation flowcharts (a) and (b) in FIG. 5 can be executed at high speed compared to accessing the memory 30, so the processing in FIG. Even if the pointer control section 31 shown in FIG. and Fig. 5 f
If the processing at and (b) are performed separately, further speeding up can be achieved.

The pointer control unit 31 shown in FIG. 2 includes a small CPU and a program ROM for executing the operation flowchart shown in FIG.
, the Empty flag, the Full flag, and the jump source address WP0, so it can be easily integrated into a single chip, as in the second conventional example shown in FIG. It can be realized at low cost and in a small space compared to the case where twice the memory capacity is required.

The embodiment shown in FIG. 2 is an example of application of the ATM switching channel shown in FIG. 6 to the FIFO 3, but the present invention is not limited to this and can be applied to other data processing devices.

〔Effect of the invention〕

According to the present invention, write and read accesses can be performed simultaneously at memory access speeds, and first-in, first-out type data input/output control can be performed at high speed.

At this time, since the increase in the amount of memory can be minimized, the hardware scale can be reduced and costs can be kept low.

[Brief explanation of the drawing]

Figure 1 fat, (bl is a diagram explaining the principle of the present invention, Figure 2
The figure is a block diagram of an embodiment of the present invention.
Fig. 4 (al to fil are explanatory diagrams of the operation of the present invention, Fig. 5 fa) and (b) are diagrams showing an operation flowchart of pointer control, and Fig. 6 is a configuration diagram of a communication path for ATV exchange. , FIG. 7 is a block diagram of the first conventional example, and FIG. 8 is a block diagram of the second conventional example. 22-0 to 22-N... memory block, 23...
Data, 25...Read pointer.

Claims (1)

[Claims] 1) Write data (23) to the write address indicated by the write pointer (24), and read the data (23) by indicating the read address with the read pointer (25) in the writing order. In the buffer memory of this method, a plurality of memory blocks (22-0 to 22-N) each independently accessible for writing or reading data are prepared, and the write pointer (24) and read pointer (25) are provided.
) to each of the plurality of memory blocks (22-0 to 22-22).
-N) to specify addresses within each memory block (26, 27), and when the read pointer (25) points to the memory block pointed to by the write pointer (24). (2
8) A buffer memory characterized in that control is performed so that write and read accesses do not occur simultaneously on the same memory block by jumping the write pointer (24) to the next memory block (29). control method. 2) when the write pointer is caused to jump to the next memory block due to the read pointer pointing to the memory block pointed to by the write pointer;
Claim 1, characterized in that the address in the memory block from which the jump was made is held, and the read pointer is controlled to jump to the next memory program tag using the address as an index. buffer memory control method. 3) The buffer memory control method according to claim 2, wherein the number of the plurality of memory blocks is one more than the number corresponding to the required memory capacity. 4) The buffer memory control method according to claim 2 or 3, wherein the data is packet data on an ATM switching channel.