SU1138834A1 - Asynchronous shift register - Google Patents

Abstract

ASYNCHRONOUS REGISTER OF SHIFT, containing memory cells of six elements OR NOT, forming two symmetric chains, and in each chain the output of the first element OR is NOT connected to the first inputs of the second and third elements OR NOT, the output of the second element OR NOT of each chain connected to the second input of the second element OR NOT another chain of the same memory cell, the first input of the first element OR NOT of each chain is its information input, and the output of its third element OR NOT is an information output, and the inputs of the chains of each memory cell, except the first one, are connected to the information outputs of the chains of the previous memory cell, the information inputs of the chains of the first memory cell are the information inputs of the register, and the information outputs of the chains of the last memory cell are its information outputs; In order to increase the speed of the asynchronous shift register, in each chain its information input is connected to the second input of the third OR-NOT element, and the output of the second OR-NOT element is connected The second input of the first OR-NOT element is the control output of the chain and in all memory cells except the first is connected to the third input of the second element OR of the same name of the previous one (L of the first memory cell controlling the outputs of the chains the first cells of the memory are the first and second control outputs of the register, and the third inputs of the second elements SH-NOT of the chains of the last memory cell — the first and second control inputs of the register; the information outputs of the chains of each memory cell, except for, are connected to the third entrances the third 00 elements OR NOT the corresponding zeo 00 buds of the previous memory cell, the information outputs of the first memory cell of the first memory cell are the third and. the fourth control outputs of the register, and the third inputs of the third elements OR-NOT of the chains of the last memory cell are the third and fourth control inputs of the register.

Description

one

The invention relates to automation and computing and can be used in the construction of digital computing devices.

A known asynchronous shift register on NAND elements containing memory cells, each of which consists of a three-stable trigger on three elements and an auxiliary element, the first inputs of the first two elements of the three-stable trigger, and the first inputs of its third and auxiliary elements are combined and are the control input of the Cell, the outputs of the first two elements of the three-stable trigger are the information outputs of the cell, and the output of its third element is connected to The second input of the auxiliary element, the output of which is the control output of the cell, the information and control inputs of the fifth cell, are connected respectively to the information and control inputs (1-1) of the second cell, the two inputs of the first two elements of the three-stable trigger 1- The second cell and the third input of its auxiliary element are connected respectively to the information and control outputs of the (1 + 1) -th cell, and the third and fifth inputs of the auxiliary element of the i-th cell are connected to the information outputs of the (1 + 2) -th cell. The register is characterized by high speed: information is shifted by one bit in it for an independent time of 61, where is the delay of one AND-HE element ClJ.

The disadvantage of this register is the redundancy of the equipment necessary to store one bit of information.

The closest to the proposed technical entity is the shift register on the AND-NOT elements, consisting of memory cells, each of which consists of six elements that form two symmetric chains such that the first elements of both chains form the main one, and the second - auxiliary The RS flip-flops, with the first, second and third inputs of the first element of each chain being its information, first and second control inputs, and the output connected to the first inputs

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The second and third elements, the second input of which is connected to the output of the second element, and the output is the information and control 5 output of the chain, and the information output and the first control output of each chain of the | th memory cell are connected to the information input and control output of the corresponding O chain (in-1) -y of the register cell, and its second control input - with the control output of the opposite chain (i-f1) -th cell of register 2. However, the known register is characterized by low speed: a shift by one bit P oiskhodit of time, underlying, depending on the information recorded in the register in the range 4 - BHP, where the delay of one of the AND-NO; n is the number of register cells.

The purpose of the invention is to increase the speed of the shift register.

This goal is achieved by the fact that 5 in an asynchronous shift register containing memory cells of six OR-NOT elements forming two symmetric chains, and in each chain the output of the first element 0 OR-NOT is connected to the first inputs of the second and third elements OR -NO, the output of the second element OR NOT of each chain is connected to the second input of the second element OR NOT of another chain j of the same memory cell, the first input

the first element OR NOT of each chain is its information input, and the output of its third element OR NOT the information output, and the information inputs of the chains of each memory cell, except the first one, are connected to the information outputs of the chains of the previous memory cell, information inputs the chains of the first memory cell 5 are the information inputs of the register, and the information outputs of the chains of the last memory cell are its information outputs, in each chain its information input is connected to the second input the third element, and the output of the second element IPI-NOT, connected to the second input of the first element OR-NOT, is the control output of the chain and in all memory cells, except the first, is connected to the third input of the second element OR-NOT of the same name of the previous cell the memory controlling the outputs of the chains of the first memory cell are the first and second control outputs of the register, and the third inputs of the second OR elements of the chains of the last memory cell — the first and second control inputs of the register, information outputs of the chains This memory cell, except for the first one, is connected to the third inputs of the third element OR NOT the corresponding chains of the previous memory cell, the information outputs of the chains of the first memory cell are the third and fourth control outputs of the register, and the third inputs of the third elements of the ALINE chain memory cells are the third and fourth control inputs of the register. FIG. 1 shows the scheme of the proposed shift register; Fig. 2 is a circuit for connecting a register to a source and receiver of information. Register 1 contains 2 memory cells, each of which consists of two symmetric chains 3 formed by three OR-NOT 4 elements in each chain 3 the output of element 4 is connected to the first inputs of elements 5 and 6, the output of element 6 is connected to the first input of element 4 The second input of element 4, connected to the second input of element 6, is the information input 7 of chain 3, and the output of element 6 is its information output 8. Between the chains 3 of each cell 2 there is a trigger connection formed by the connection of output and element 5 each chain 3 with w eye in element 5 of the other chain 3. The output of element 5 of each chain 3 is its control output 9, and the third inputs of elements 5 and 6 are the first 10 and second 11 control inputs. The information inputs of both chains 3 of each cell 2, the first one, are connected to the information outputs 8 of the corresponding chain 3 of the previous cell 2, and the information outputs 8 of both chains 3 of each cell 2, except the last one, are connected to information inputs 7 corresponding to chains 3 of the previous cell 2. The information inputs 7 of chains 3 of the first cell-2 are the first 12 and second 13 information inputs of register 1, and the information outputs 8 of the chains 3 of the last cell 2 are its first 14 and second 15 information outputs. The control outputs 9 of the chains 3 of each cell 2, except the first one, are connected to the first control inputs 10 of the corresponding chains 3 of the previous cell 2, and the control inputs 10 and 11 of the chains 3 of each cell 2, except the last one, are connected respectively to the control 9 and The informational 8 outputs of the corresponding chain 3 of the previous cell 2. The control outputs 9 of the chains 3 of the first cell 2 are the first 16 and second 17 control outputs of the register 1, and the informational ones. outputs 8 are his third 18 and fourth 19 control outputs. The control inputs 10 of the chains 3 of the last cell 2 are the first 20 and second 21 control inputs of register 1, and the control inputs 11 are its third 22 and fourth 23 control inputs. The circuit (Fig. 2) includes a register 1, information source 24, information receiver 25 and an auxiliary element OR NOT 26. Information outputs 27 and 28 of source 24 are connected respectively to first mm 12 and second 13 information inputs of register 1. Control the input 29 of the source 24 is connected to the output 30 of the auxiliary element 26, the first, second, third and fourth inputs of which are connected respectively to the first 16, second 17, third 18 and fourth 19 control outputs of register 1. Information outputs 14 and 15 of register 1 are connected respectively with the first 31 and second 32 information inputs of the receiver 25. The control inputs 20 and 21 of register 1 are combined into one control input 33 connected to the control output 34 of receiver 25. The control inputs 22 and 23 of register 1 are connected to a constant signal source A. In a stable state of register 1, each of the chains of 3 cells 2 can be either in a working state or in a state of quenching. The working state corresponds to the availability of information in the chain 3 (combination 001 at the outputs of elements 4-6), and the quenching state corresponds to the lack of information (combination 100 31 at the outputs of elements 4-6). A trigger connection between elements 5 of two chains of 3 cells 2 prevents information 3 in two chains from writing simultaneously to 2 cells. If chain 3 of the i-th cell 2 is in working condition, the signals at its information 8 and control 9 outputs prohibit recording information in the same chain of 3 (1-1) -th cell 2 Therefore, the following one after the other information units (zeros) cannot be in register 1 in chains 3 of two adjacent cells 2, but are necessarily separated by chain 3 located in quenching states, and the chain 3 is symmetric to it The same cell 2 can be either quenched or in working condition, i.e. keep information. Thus, the following one after the other information units (zeros) in the register (in its stable state) through the discharge (Loose), and alternating 01010 - in the next bits (Tight). In case of a loose filling, two cells 2 are required for storing one bit, one cell 2 is required for dense filling. We can assume that one bit of information takes an average of 1.5 cells 2, and to call the storage method semi-dense. The shift of information in the register occurs as follows. The unit recorded in the jth cell 2 of register 1 is moved to (; + 1) -th cell 2, if. (1-I) is cell 2 and the corresponding chain 3 (| +2) -th cell 2 is in quench condition. At the same time, at the informational 8 and control 9 outputs of the chain of 3 (+1) -th cell 2, there are information recording permission signals. The information signal from the output of the element 6 of the chain 3 of the i-th memory cell through the bus 8 is fed to the input 7 of the same-name chain 3 (f + 1) -th cell 2, causing alternate switching of the elements of these chains 3 i-th and (1 + 1) -and cells 2 in the following sequence: 4 - - 5 j + i-5 4 -6 -6- (the index at the element number indicates the number of the cell 2, which includes this element) .. As a result, the chain 3 (+1) th cell is set to the working state (011 at the outputs of elements 346, 4., 5j, 6,), and the chain 3 of the i-th cell is put to quenching (100 at the outputs of elements, 5, 60). m ,, the information shift time by one bit is in the proposed register 6f, where t is the average delay of the element OR NOT, and does not depend on the number of register cells. Sequential switching of the chain elements ensures the stability of the information advancement process, as it makes it independent on the values of the delays of the elements and their ratios. As you progress through the register, the information is automatically distributed tightly or loosely depending on the internal states of the cells and the states of their inputs. . The interaction of the first cell 2 of register 1 with the source 24 of information and the receiver 25 of information is carried out according to the principle of coordinated exchange or the principle of Request Response. At the same time, information and control signals of register 1, as well as information signals of source 24 and information receiver 25, are represented in a paraphase code. The phase signals at the control outputs 16-19 are converted into a single-phase signal at the output 30 of the element 26, which controls the transmission of information from the receiver to the register. In the initial state, information source 27 and 28 is set to phase code 00 (no information), register 1 is empty (all chains 3 are in the blanking state), signal O at output 30 of element 26 means for the source permission of setting information code (01 or 10) at outputs 27 and 28. The information code enters the inputs 12 and 13 of register 1 and is fixed through 3f one of the chains 3 of the first cell 2, as evidenced by the appearance of signal 1 at the output 30 of element 26. This signal gives source 24 should translate information output 27 and 28 in the state of blanking (00), which means permit the second forwarding information. cell 2 register 1. The second day is able to respond to this transition after 2 (switching times of elements 4 and 6,). Then, during time 51, the five elements of the same chains 3 of the first and second cells 2 are sequentially switched, after which element 26 is switched to the state O. This signal means for the source 24 the permission to be set on the outputs 27 and 28 of the new information code. If the next transmitted bit is different from the previous one, then it is accepted into the register immediately after it appears on information inputs 12 and 13 of register 1, since the previous bit is transmitted on the other side of the register. If the next transmitted bit coincides with the previous one, then another 4f passes before its reception. This time is necessary for the previous bit of information to be fixed in the third cell 2, and the corresponding chains 3 of the first to the second cells 2 are transferred to. quenching condition. The first cell 2, when receiving information, always passes through the blanking network, and then the information is distributed automatically in the register, regardless of the source. The period of the following information signals Tj at the input of register 1 at dense filling is determined by the formula Tz (2v) + 5V + i: l where is the time of switching the source to the state T ° - the same, but to the state MOM or 01. At T Ch2Gi,. In the case of a loose filling of Tz Zg + max (, 2t) - (- 5t + max (or Tz 14Tp T; °; 2ggy.) In the process of reading information from register 1, receiver 25 controls the transmission of information using a signal at control output 34, which is fed to the control input 3 of register 1. In the initial state, when the receiver 25 cannot receive information, the signal 1 at the output 34 prevents the last 2 register of the register 1 from transitioning to the working state. the first recorded in the register 1 bit is stored in the penultimate slot 2. At information output 14 and 15 of register 1, the code 0 is set 0 (no information). The constant signals O at inputs 22 and 23 of register 1 do not prevent the switching of elements 6 of the last cell 2, the signals 1 to, the control inputs 20 and 21 of register 1 support both chains 3 of the last cell 2 If receiver 25 is ready to receive information, it sets on output 34 a signal O allowing the switching of one of the chains 3 of the last cell 2, which after 5 T comes to the working state. At the same time, code 10 or 01 is set up at information outputs 14 and 15 of register 1. Next, receiver 25 receives information and changes signal at output 34, which causes blanking of the corresponding chain 3 of the last cell 2 of register 1 during time: I :. After the last cell 2 of register 1 is quenched, receiver 25 can re-send a read request signal (a change in output 34 from 1 to O in time). Thus, when reading information from a tightly filled register, the period of the information signals is expressed by the formula T, 5Eg + T ° -; + Zsch-t; - °, or t YAHGT-iTj t t -P IC, with i fif, -i fjp -U. When the register is not full, when the following bits are separated by chain 3, which is in the quench state, additional time is required during which the register is prepared to react to a signal change at the output 34 of the receiver 25. Therefore, the time TJ p can be increased to 2V and up to 4C. The formula for T ;; takes the form 5С- + тах (Т ° -, 2Г) + 3С + тах (), or at t, рЧ2гг and 4t, Txx compared to the known proposed asynchronous shift with the same number of bits n gives a proportional The performance gains because the shift time of a bit of information by one bit in the proposed register does not depend on the number of bits n. The characteristics of the cell complexity of the known and proposed registers are the same and equal to 22 (the total number of inputs and outputs of the OR-NOT elements in the so-called cell).

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Claims (1)

ASYNCHRON SHIFT REGISTER containing memory cells of six OR-HE elements forming two symmetric chains, and in each chain the output of the first OR-NOT element is connected to the first inputs! of the second and third OR-NOT elements, the output of the second OR-NOT element of each chain is connected to the second input of the second OR-NOT element of another chain of the same memory cell, the first / input of the first OR-NOT element of each chain is its information input, and its output the third element OR NOT - an information output, and the information inputs of the chains of each memory cell, except the first, are connected to the information outputs of the chains of the previous memory cell, the information inputs of the chains of the first memory cell are information inputs and, register, and the information outputs of the chains of the last memory cell are its information outputs, characterized in that, in order to increase the speed of the asynchronous shift register, in each chain its information input is connected to the second input of the third OR-NOT element, and the output of the second element OR NOT connected to> the second input of the first element OR NOT, is the control output of the chain and in all memory cells except the first one is connected to the third input of the second element - that OR NOT the same chain of the previous memory cell These control outputs of the chains of the first memory cell are the first and second control outputs of the register, and the third inputs g of the second elements OR NOT chains of the last memory cell are the first and second control inputs of the register, the information outputs of the chains of each memory cell, except the first, are connected to the third inputs of the third elements OR NOT corresponding chains of the previous memory cell, the information outputs of the chains of the first memory cell are the third and fourth control outputs of the register, and the third inputs of the third ele ENTOV NOR chains last memory cell are the third and fourth control register inputs.