JPS61193594A - Time switching circuit - Google Patents

Abstract

PURPOSE:To guarantee a bit pattern of unsed bit position in an outgoing highway by clearing all bits of a reading address just after sequential reading is carried out. CONSTITUTION:With respect to a memory clear timing 2091, '11111111' is written in an address of a channel memory 12. Namely, in memory clear timing a lead 2091 becomes '1', an output 2051 of a data clear circuit 17 becomes '11111111', and simultaneously a writing control circuit 207 also becomes '11111111'. At this time, '01' is supplied to an address 218 of a channel memory 12 by an output 214 of a counter 15 through a selector circuit 17, and '11111111' is written in an address 1 of the channel memory 12, while the address 1 of the channel memory 12 is cleared by means of '11111111'. Thus this makes it possible to guarantee that the bit pattern of the unused bit position in the outgoing highway becomes a specified value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a time division switch in a time division exchange, and particularly to a time switch circuit for not only time slot replacement but also speed conversion and multiplexing or demultiplexing.

[Prior art]

In current digital telephone networks, voice signals have a period of 1
It is exchanged and transmitted as a 64 kb/s digital signal of 25 μs and 8 data bits/cycle. Therefore, time division switches used in digital telephone networks generally operate at 64kb/s.
It has been developed to be exchanged in units.

On the other hand, 64K such as facsimile communication, data communication, etc.
8kb/sXN (however, N=1
．． There is a strong desire to realize a multi-component digital network that can handle multi-component speeds of 2, 4, and 8).

As a communication channel configuration of a multiplex exchange applied to such a multiplex digital network, a switch circuit as shown in, for example, IEICE technical research report 1N33-8J has been proposed.

A block diagram of this switch circuit is shown in Part 5.

The detailed operation of this switch circuit is detailed in the above-mentioned document and will therefore be omitted. An input highway 201 in which data of 8.times.Nkb/s is converted into 64 kb eight universal signals is converted into serial/parallel data in units of 8 bits by a serial/parallel conversion circuit 100.

The data after this serial/parallel conversion is bit-selected and written into the random write/sequential read communication path memory 12. After sequential reading, the data is parallel-to-serial converted by the parallel-to-serial conversion circuit 14 and outputted as bearer multiplexed output highways 2 and 08. This makes it possible to realize a multiple exchange function.

Note that the control of writing to and reading from the communication path memory 12 is as follows.
counter 15, holding memory 16, write control circuit 13,
This is done by the selection circuit 18. That is, the count output 215 of the counter 15 specifies the address of the holding memory 16. Holding memory 16 specifies the address of channel memory 12. Data 205 is written to the communication path memory 12 at a write address 218 selected by the select circuit 18 based on a write command (bit write command) 207 from the write control circuit 13 . This write address 218 is
This is the readout output 217 of the holding memory 6. Access to the holding memory 16 is performed by the counter 15. That is, the holding memo 1/6 is accessed according to the count value of the counter 15, and among the read outputs, output 217 is selected by the select 18 and becomes the write address 218;
Among the read outputs of 6, the output 216 is the write control circuit 13.
Enter it.

This becomes a write command 207 which is a bit selection command. Upon receiving this write command 207, the data 205 is written in bit correspondence to the write address 218.

On the other hand, during reading, the count value 214' of the counter 15 is input to the select circuit 18 and selected, and becomes the read address 218. The contents of the channel memory 12 specified by the read address 218 are read out and sent to the parallel-serial circuit 14. Since this reading uses the count value of the counter 15 as an address, sequential reading is performed.

According to this conventional switch circuit, the basic function of multiple exchange is satisfied, but there is room for improvement in the following points. That is, in the switch circuit, one channel memory 1
2, writing is random writing by bit selection, and reading is sequential reading. Therefore, unless all bits are selected and written at each address in the channel memory 12, the previously written data remains in the unwritten bits. As a result, in the bearer multiplexed nine output highway, the residual data is output as is to the unused bit position, and it is not guaranteed whether the unused bit position of the output highway will be 11011 or 1''.

For this reason, in an application where it is necessary for the unused bit positions of the output highway to be all "1"', the unused bit positions are further added to the output of FIG. 5 as "It I It". There is a problem in that an additional circuit is required to do this.

[Purpose of the invention]

An object of the present invention is to provide a time switch circuit that guarantees the bit pattern of unused bit positions on the output highway.

[Summary of the invention]

The present invention guarantees the bit pattern of unused bit positions on the output highway by clearing all bits of the subsequent address immediately after sequential readout.

[Embodiments of the invention]

FIG. 1 is a diagram showing an embodiment of the time switch circuit of the present invention. The time switch circuit consists of an 8-bit shift register, 10.8-bit register, 11.8-bit, 4-word channel memory, and 12. Write control circuit 13.8-bit register 14, counter 15.7-bit/16-word holding memory, data clear circuit 1 consisting of 8 OR circuits
7. Consists of a selector circuit 18 and an OR circuit 19.

Here, the data clear circuit 17 sets all DOI to DO8 to "1" when the D input is "1", and the data clear circuit 17 sets all DOI to DO8 to "1" when the D input is "0".
”, DIO to DI8 are output as they are to D01 to I)08. Also, the select circuit I8 has an S input of 1.
When it is 70'', Do is output to DO, and when it is 1'', Dl is output to DO.The operating waveforms are shown in Figure 2. Identical symbols indicate identical content.

The input highway 201 is a highway to 1024 kb in which, for example, 16 time slots TSO to TS15 of 8 bits each are multiplexed at a cycle of 8 kHz. That is, the input highway 201 carries a signal with a frame period of 8 kHz, one frame consisting of 16 slots, and one slot consisting of 8 bits.

The shift register 10 is a kind of serial-to-parallel converter circuit, and has 8
After shifting the bits by one time slot, they are set in parallel in the register 11 by the clock 203.

For the input highway 201 data set in the register 11, the holding memory 16 stores a write address to the communication path memory 12 and a write mode that specifies the bit position and speed class to be written, corresponding to the time slot of the input highway 201. do.

The counter 15 sends out a count value synchronized with the time slot number of the input highway 201 to address lines 214 and 215. A write address when writing to the communication path memory 12 is performed using the address line 215. At this time, the address line 21
5 does not directly serve as the write address, but the holding memory 16 is accessed by the address M 215 and its read output 216, 217 becomes the write address. However, the output 216 enters the write control circuit 13 and is used for bit selection, and the output 217 becomes the original write address. Output 216 also serves as a write command. Writing via this holding memory 16 results in variable addressing.

A read address for reading data written into the channel memory 12 is provided from the address line 214 of the counter 15. The count output of this address line 214 is selected by the select circuit 18 and becomes a read address 218.

By specifying this read address 218, the communication path memory 12 is read, and the contents of that address are output 206.
Read by. Since this readout is based on the count value of the counter 15, a fixed address is specified, and is a so-called sequential readout method. Setting to the register 14 is performed using clocks 2101 and 2100.

Data is written to the holding memory 16 at a time other than when the counter 15 accesses the address line 215. The data to be written into the holding memory 16 is the address of the communication path memory 12 (more precisely, address correspondence information). This data is sent from the higher level via the data bus 211. The address to which this data is to be written, ie, the write address of the holding memo Shogetsu 6, is designated by the address bus 212. When writing, write enable signal (clock)
Input 213 and use the timing to write.

To clear the channel memory 12, the data clear circuit 17 and the write control circuit 13 operate at memory clear timing 2091 immediately after the read data is set in the register 14 by the clock 210 (2101, 2100).

All "1"s are written to the address.

Next, time slot TSO,T of input highway 201
A signal with a bearer speed of 16 kb/s and converted to a 64 kb/s universal signal is assigned to the SI.

Exit this signal at highway 20g time slot TSL
The operation of the time switch circuit will be explained in more detail, taking as an example the case where the time switch circuit multiplexes and outputs the data.

FIG. 3 is a format diagram of the connection command, and shows the format of the connection command sent to the holding memory 16. FIG. 4 is a truth table of the write control circuit. The write mode and enable terminal signal status are shown for each speed. still,
In FIG. 4, the mark rXJ means that it does not matter whether it is "1" or '0'.

The control device of the exchange, which is not shown in the figure, specifies the incoming time slot, outgoing time slot, and write mode (speed class, bit position specification) using the address bus 212 and data bus 211, and writes to the clock line 213. A connection command is written into the holding memory 16 by the signal. That is, the first connection command holds the memo 1J16 (7) “0000”.
Data "0101000" is written to the address, and data "0101001" is written to the address "OOO1" by the second connection command.

At the timing corresponding to the time slot TSI of the input highway 201, the stored content "0101000" at the address "0000" of the holding memory 16 is read out, and the upper two bits 0102="01" corresponding to the output time slot are read out via the select circuit 18. Write address A of communication path memory 12
It is input to DI,2.

In addition, the upper 2 bits of the above data (01, 02) 01"
corresponds to a bearer speed class of 16 kb/s, for example, "OO" corresponds to a speed class of 8 kb/s,
'10'' corresponds to the 32 kb/s speed class, and 11'' corresponds to the 64 kb/s speed class.
゛In addition, the lower 5 bits 03 to 07 corresponding to the write mode
= “01000” is the control input C of the write control circuit 13
Input in 1 to C5.

The write control circuit 13 sets "1" to the enable terminals Gl and G5 of the communication path memory 12 according to the truth value shown in FIG.
2. G3. G4. , G6. G7. Output "0" to G'8.

Data of the time slot TSI of the input highway 201 is stored in inputs 1 to 8 of the communication path memory 12.
aaaa” is given, but the corresponding enable signal 0
1 to G8 are only 111” bits, that is, data “acI”
Only t is written to address 1 of the channel memory 12 at write timing 2090.

Similarly, in response to the second connection command, the input highway 201
data of time slot TSI” b b dd d
Even-numbered bit data 11 bd in d d d
17 is written to address 1 of the channel memory 12.

On the other hand, prior to writing the data described above, "11111111" is written to address 1 of the 1-channel memory 12 at memory clear timing 2091. That is, in FIG. 1, the lead 2091 becomes 1'' at the memory clear timing, and the data clear circuit 17
The output 2051 becomes "11111111", and at the same time, the write control circuit output 207 also becomes "l 1111111".
becomes. At this time, the address 218 of the communication path memory 12
output 214 of the counter 15 via the selector circuit 17.
1101” is supplied, and the “11111111” is written to address 1 of the communication path memory 12.
As a result, address 1 of the communication path memory 12 becomes "11".
111111”.

As a result of the above, address 1 of the channel memory 12 contains data obtained by bearer multiplexing the 16 kb/s data of the above time slots TSO and TSI.
11” will be written.

The above contents of address 1 of the communication path memory 12 are read out at a timing corresponding to the time slot TS1 of the outgoing highway 208. In addition, reading the communication path memory is as follows:
Not all addresses need to be sequential;
It can also be applied when some areas are sequential.

〔Effect of the invention〕

According to the present invention, in a time switch circuit for multiple communication paths, it is possible to guarantee the bit pattern of unused bit positions on the outgoing highway to a specific value, for example, 1'', and to Alternatively, it is possible to provide a multi-way switch circuit that can be applied even in applications where it is necessary to guarantee the bit pattern of unused bit positions on a subscriber line.

[Brief explanation of drawings]

Fig. 1 is a diagram of an embodiment of the time switch circuit of the present invention, Fig. 2 is a time chart, Fig. 3 is a format diagram of a connection command, Fig. 4 is a diagram showing a truth table, and Fig. 5 is a diagram of a conventional example. It is. 10... shift register, 11... register, 1
2... Call path memory, 13... Write control circuit, 1
4...Register, 15...Counter, 16...Holding memory, 17...Data clear circuit, 18...Selector circuit, 19...OR circuit. Representative Patent Attorney Tadashi Akimoto Figure 2 202 Niyo Kuniyama…” −−−−−1209+: 2101 −−−−1−−−−Royu Dori Entrance A−−
--Third cause Figure 5

Claims (1)

[Claims] 1. A communication path memory provided between an incoming highway and an outgoing highway, a write address holding memory that stores address correspondence information of the communication path memory into which data for each time slot on the incoming highway should be written, and a communication path memory. a read address generating means for generating a fixed read address corresponding to each time slot of the highway, and accessing the holding memory when writing to the channel memory; means for writing the data of each time slot from the input highway into the communication path memory according to the bit designation and address from the address correspondence information read out, and reading the data from the communication path memory. A time switch circuit comprising a clear circuit that later clears the contents of the read address.