KR980013134A - Time switching system and control method thereof for synchronous high-speed transmission device - Google Patents

Abstract

An object of the present invention is to optimize system configuration and operation by processing data in a single board by reducing memory requirement for data switching by switching data in consideration of characteristics of data input to a transmission system There is.

In order to accomplish the above object, a time switching system of a synchronous super high-speed transmission apparatus includes frame control information means for generating a signal at a start time of a frame and storing information about a data type stored in the frame, A switching memory address generating means for generating an address for storing the data bit stream at a predetermined position of the switching storing means; And switching control means for generating an address for reading the stored data.

According to the present invention, data switching is performed in consideration of the characteristics of data input to the transmission system. Therefore, the memory requirement for data switching can be reduced. Therefore, data switching can be processed in a single board, It is effective.

Description

Time switching system and control method thereof for synchronous high-speed transmission device

In particular, the present invention relates to a time switching system of a synchronous high-speed transmission apparatus that reduces the amount of memory required for the switching because it switches in consideration of characteristics of data input to a synchronous super high- And a control method thereof.

In recent years, research and development on information and communication networks have been promoted. One area of research and development is related to B-ISDN (Integrated Services Digital Network).

B-ISDN (Integrated Services Digital Network) consists of User Network Interface ("UNI") for realizing broadband service.

The communication scales used in the above two interfaces were divided into American and European scales. In 1990, different scales were integrated into SDH (Synchronous Digital Hierarchy). SDH multiplexes and transmits data of subscribers to the communication lines of STM-1 (Synchronous Transport Modules (STM)) to STM-4, and data switching is performed in accordance with SDH. Are multiplexed in order by 8 bits (1 byte). Such a multiplexing method is called byte interleaving.

In such a digital network, voice data typically transmits 8000 (1-byte) information at 8000 (Kbps) speed. In the case of voice, this 8-bit unit represents a line. In this case, the time for transmitting one byte is called a time slot. In the digital network, a plurality of lines are multiplexed in order every 8 bits. 1 shows that four lines are multiplexed to transmit data, and one byte is transmitted in a cycle of four times. The period of multiplexing and returning to the initial state is referred to as a frame period T0. Since the multiplexed signals are queued in order for each line, data exchange is performed if the sequence number is changed by a predetermined method. For example, as shown in Fig. 1, the input digital signal is temporarily stored in the memory, and the data is sequentially read out to the output port designated by a signal such as a dial number and then output.

2 shows the configuration of PM5371 TUDX system of PMC-Sierra, a general digital exchange apparatus.

A switching unit (22) for temporarily storing the input stream to switch the input stream; and a control unit (22) for reading the data stored in the switching unit (22) And an output formatter 25 for rearranging the data read by the sequence control unit 24 to output the data to an output stage (not shown). At this time, the switching unit 22 needs memories 23 corresponding to the square of the number of input ports of the bit stream.

The operation of the general digital switching system of FIG. 2 will be described below.

(1-byte) input data to be exchanged continuously, and temporarily stores the data in the memories 23 in the switching unit 22. [

The order control unit 24 then inputs control signals for the data to the switching unit 24 and the output formatter 25 in order to exchange the input data and inputs the control signals to the output formatter 25, Reads the data stored in the memory 23 of the memory 22 and outputs it to an output terminal (not shown).

Referring to FIG. 3, a basic algorithm of the applied switching will be described. When the input EPO data temporarily stores A, B, C, D, ... in the switching unit 22, The switching unit 22 reads the stored data according to the read address value and outputs the read data.

That is, when the input is in the order of A, B, C, and D as shown in FIG. 3, it is stored in the input order, and when read in the order of D, C, B, and A, B are exchanged in C and output respectively. Performing with such an algorithm is called a time switch.

Currently used transmission devices switch data in the same manner as described above. The number of input ports (IN #) of the transmission apparatus when exchanging data using the transmission apparatus and the amount of memory required according to the number of input ports will be described below.

For example, as shown in FIG. 4, if a 4-foot switch is configured using a conventional two-port PMC chip, four chips are required. That is, the storage capacity in order to configure a 4-port switch with two ports for the chip ^22, the chip in as much as is required if the default size of the data input to the respective chip port of N bytes N × ² bytes Required for each chip.

As described above, as the number of input ports and the size (N) of the input data increase, the capacity of the memory for storing input data increases, making it impossible to integrate the necessary amount of memory in one chip .

Therefore, when using the conventional switching method for receiving and switching 270 bytes in STM-1, a memory of 270 × IN # ² bytes is required. Accordingly, since a plurality of chips must be used, the memory can not be configured on a single board .

Accordingly, it is an object of the present invention to provide a system and a method for processing data in a single board by reducing the memory requirement for data switching by switching data in consideration of characteristics of data input to the transmission system, .

Fig. 1 is a conceptual diagram showing transmission of data by multiplexing four circuits,

2 is a block diagram showing the configuration of PM5371 TUDX system of PMC-Sierra, which is a general digital exchange apparatus;

3 is a conceptual diagram showing time switching of input data,

4 is a block diagram showing the construction of a 4-port switch using a reference 2-port PMC chip;

FIG. 5 is a block diagram showing a unit frame composed of 9 × 270 bytes transmitted in a period of 125 μs in the STM-1 transmission system and a procedure for reading the unit frame,

FIG. 6 is a conceptual diagram illustrating a process of reading a bit stream stored in one frame of FIG. 5 for transmission on the same path per 84 bytes when the data is to be transmitted to the TU-11;

FIG. 7 is a conceptual diagram illustrating a process of reading a bit stream stored in one frame of FIG. 5 for transmission on the same path per 63 bytes when the data is to be transmitted to the TU-12;

FIG. 9 is a block diagram illustrating a time switching system of a synchronous full-speed transmission apparatus according to the present invention.

FIG. 9A is a flowchart illustrating a process of inputting a bitstream to a time-swinging system of a synchronous high-speed transmission apparatus according to the present invention;

FIG. 9B is a flowchart illustrating a process of exchanging bit streams stored in a time switching system of a synchronous high-speed transmission apparatus according to the present invention; FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

21: Bitstream input unit 22: Switching memory

23: storage units 24:

25: Output Formatter A to D: Data

81: Frame control information section 82:

83: Address of the switching memo generator 84:

85: Frame start control section 86: Data type storage section

A, B: Memory modules 89: Switching memory control information storage unit

90: recording address generating section 91: connection information memory section

92: Read address generating section 100:

In order to achieve the above object, a time switching system of a synchronous high-speed transmission apparatus includes frame control information means for generating a signal at a start time of a frame and storing information about a data type stored in the frame, A switching memory address generating means for generating an address for storing the data bit stream at a predetermined position of the switching storing means; And switching control means for generating an address for reading the stored data.

In order to accomplish the above object, there is provided a control method of a time switch system of a synchronous high-speed transmission device, including a frame input step of storing data for storing data for controlling the switching storage means and waiting for an input signal of a frame, A step of receiving an input signal of the frame and a predetermined amount of data and storing the data type of the frame; waiting for a predetermined time according to the data type; A data storing step of storing data in the address, and a data exchange step of generating an address for reading out the switching storing means and outputting data corresponding to the address to an output terminal.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

As described above, a typical time switch stores data in a switching memory (hereinafter referred to as SM) sequentially when data is input and stores information for switching the data in a connection memory Hereinafter referred to as " CM "), and then the switching information is sequentially read and used as an address of the data memory to carry out an exchange operation.

In STM-1, which is a 155.52 MHz high-speed transmission device, data frames transmitted by multiplexing three identical data are transmitted in a repeating form of one-third of input data.

The details are as follows.

FIG. 5 shows a unit frame composed of 9 × 270 bytes transmitted in a period of 125 μs in the STM-1 transmission method and a procedure of reading the unit frame. As shown in the figure, the actual data among the 9 × 270 bytes is 84 × 3 × 9, and the remainder consists of information for data transmission, and the transmission system reads the frames as described above one line at a time Lt; / RTI >

When the frame of FIG. 5 is transmitted according to the network node interface (NNI) multiplexing method of the SDH, switching is performed by storing the data in the switching memory SM for each line (270 bytes) for switching the respective data.

At this time, if the bit stream stored in the above-mentioned frame is data to be transmitted to the TU-11, which is a Japan-US transmission system, as shown in FIG. 6, it is transmitted on the same route per 84 bytes.

On the other hand, if the bit stream stored in the above-mentioned frame is data to be transmitted to the TU-12, which is the European transmission scheme, it is transmitted on the same path per 64 bytes as shown in FIG. In other words, the pure data of the subscriber in one frame configured as shown in FIG. 5 is composed of 252 × 9 = 2268 bytes. That is, the data to be switched is 2268 bytes in one frame. On the other hand, the data stored in the frame is composed of 27 bytes x 84 (= 2268 bytes) when branched to TU-11 and 36 bytes x 63 (= 2268 bytes) when branched to TU-12.

In this case, the data to be branched into the TU-11 and the TU-12 are constructed by reading the input frame as shown in FIGS.

Each line in FIG. 5 is a multiplexed data of three identical types, and data such as TU-11 and TU-12 are mixed and transmitted according to a certain rule. In this case, the basic unit of data to be mixed and transmitted is 4 pieces of TU-11 and 3 pieces of TU-12 are multiplexed and transmitted. Therefore, when the two pieces of time are multiplexed, 3 pieces of TU-11 and 4 pieces of TU- , That is, the two least common multiple numbers 12 are multiplexed in a basic unit.

As described above, since the data frames transmitted by the STM-1, which is an ultra high-speed transmission apparatus, are multiplexed and transmitted by three identical data, the input data is operated in a repetitive manner so that the data switching can be switched in units of 84 bytes .

[Equation 1]

Switching memory (SM) = 84 × 3 × square of input port number (IN # ² )

&Quot; (2) "

Switching memory (SM) = 84 × square of the number of input ports (IN # ² )

Accordingly, unlike the conventional method requiring the switching memory SM according to Equation (1), since the present invention is switched in units of 84 bytes for TU-1 and 63 bytes for TU-2, A switching memory is required. At this time, the TU-11 is 1.544 MHz data and the TU-12 is 2,048 MHz data.

Therefore, the present invention can reduce the memory size required by the present invention to one third by utilizing the characteristics of the data structure.

FIGS. 6 and 7 illustrate a case where the structure of data input to the switching system is a single structure. In general, TU-11 / TU-12 data are mixed in an input frame and input to the switching system.

Therefore, if the data is stored in the switching memory SM in the order in which the data (bit stream) is input as in the present invention, there is a problem that the input data is mixed into various types. Accordingly, in the present invention, the input data (bit stream) is stored in the switching memory SM on the basis of an address driven by a certain rule according to the type of input data (i.e., AU-3 or AU-4) . At this time, the AU (Administrative Unit) is a unit used when constructing the hierarchy.

8 is a block diagram illustrating a time switch system of a synchronous high-speed transmission apparatus according to the present invention.

A frame control information section 81 for generating a signal at a start point of a frame and storing information about a data type stored in the frame, a switching memory section 82 for storing a data bit stream corresponding to the frame, A switching memory address generating section 83 for generating an address for storing a bit stream in a predetermined position in the switching memory section 82; And a switching control section 84.

The frame control information unit 81 includes a frame start control unit 85 for generating and transmitting a frame start signal to the switching memory address generating unit 83 and the switching control unit 84, And a data type storage unit 86 for storing the data type.

Also, the switching memory unit 82 requires memory modules A and B as many as the square of the number of input ports (IN # ² ).

The switching memory address generating unit 83 includes a switching memory control information storing unit 89 storing control information for storing the bit stream of the data in the switching memory unit 82, And a write address generating unit 90 for generating a write address for storing the bit stream in the switching memory unit 82 in accordance with the write information stored in the write address storage unit 89. [

The switching control unit 84 includes a connection information memory unit 91 in which switching information is stored and a read address generating unit 92 for reading out the connection information memory unit 91 and generating an address for reading the switching memory storage unit 82. [ (92).

9A is a flowchart illustrating a process of inputting a bitstream to a time switch system of a synchronous high-speed transmission apparatus according to the present invention.

First, information for controlling the switching memory (SM) 82 is received from the central processing unit 100 and stored in the switching control unit 84 (step 101).

Next, it is determined whether input of a frame is started (step 102). That is, the frame start control unit 85 waits for the frame start signal to be outputted.

If it is determined that the input of the frame is started, if the input of the frame is started, a predetermined amount of bitstream is transmitted through the communication line (not shown) (step 103).

The data type stored in the input frame is stored in the data type storage unit 86 (step 106).

Then, according to the data type stored in the data type storage unit 86, after 5 clocks in case of AU3 and 11 clocks in case of AU4, a write address is generated to write the input data in the switching memory And approaches the switching memory 82 (step 106). In this way, data can be prevented from being mixed by performing delay recording according to the input data type.

After generating the recording address, a predetermined amount of bit stream is stored in the switching memory 82 corresponding to the recording address (step 107). It is determined whether a data bitstream corresponding to one frame has been transmitted (step 108).

If it is determined that the data bitstream corresponding to one frame has been transmitted, if the data bitstream corresponding to one frame has not been transmitted, the process returns to step 103 to receive the data bitstream.

9B is a flowchart illustrating a process of exchanging a bit stream stored in a time switch system of a synchronous high-speed transmission apparatus according to the present invention.

First, the read address generating unit 92 generates an address for reading the data to be exchanged stored in the switching memory unit 82 (step 110) using the switching information stored in the connection information memory 91, And reads data from the switching memory unit 82 in accordance with the address (step 111).

And outputs the read data to an output terminal (step 112).

As shown in FIGS. 9A and 9B, data to be exchanged through the switching memory unit 82 is recorded according to a predetermined rule, and the data is read out and output, so data exchange occurs

In this case, the switching memory unit 82 has two memory modules A and B, reads data stored in the memory module A while writing data to the memory module A, do.

At this time, each module has a memory capacity of 84 bytes.

As described above, according to the present invention in which the data switch is performed in consideration of the characteristics of data input to the transmission system, the memory requirement for data switching can be reduced, so that data switching can be processed in a single board, It has the effect of optimizing the operation.

Claims (9)

Frame control information means for generating a signal at a start point of a frame and storing information about a data type stored in the frame, switching storing means for storing a predetermined amount of a data bit stream corresponding to the frame, And a switching control means for generating an address for reading out the data stored in the switching storage means, characterized in that the switching control means A time switching system of a high-speed transmission device. 2. The apparatus according to claim 1, wherein the frame control information means includes frame start control means for generating a start signal of a frame to the switching memory address generating means and the switching control means, And a storage unit. The time switching system of the synchronous high-speed transmission apparatus includes: 2. The apparatus according to claim 1, wherein the switching memory address generating means comprises switching memory control information storing means for storing control information for storing the bit stream of the data in the switching storing means, And a write address generating means for generating a write address for storing the bit stream in the switching storage means in accordance with the control signal. The apparatus according to claim 1, characterized in that the switching control means includes a connection information storing means for storing switching information, and a read address generating means for reading out the connection information storing means and generating an address for reading the switching storing means A time switching system of a synchronous high-speed transmission apparatus. The time switching system of claim 1, wherein the predetermined amount is 84 bytes. A step of storing data for controlling the switching storage means and waiting for an input signal of a frame; receiving a predetermined amount of data from the input signal of the frame and storing the data type of the frame; A data storing step of generating an address for storing data in the switching storing means and storing data in the address, and a step of generating an address for reading out the switching storing means, And outputting the corresponding data to an output terminal. The method of controlling a time switching system of a synchronous high-speed transmission apparatus according to claim 1, 7. The method of claim 6, wherein the predetermined amount is 84 bytes. 7. The method of claim 6, wherein when the data type is AU3, a write address is generated by waiting five clocks. 7. The method of claim 6, wherein if the data type is AU4, a write address is generated by waiting five clocks. ※ Note: It is disclosed by the contents of the first application.