JP2937666B2 - Cross connect device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cross-connect device for cross-connecting transmission signals synchronously multiplexed over a plurality of digital path layers in a digital synchronous network.

[0002]

2. Description of the Related Art In recent years, with the diversification of communications, research and development of a broadband service integrated digital network (hereinafter referred to as "B-ISDN") capable of comprehensively providing various communication services have been actively conducted. I have.

In this B-ISDN, a synchronous digital hierarchy (hereinafter, referred to as a digital hierarchy) is used as a digital hierarchy.
"SDH"), and signals are synchronously multiplexed over all digital path layers.

Thus, in the B-ISDN, even when a low-order group signal is cross-connected, the high-order group can be cross-connected.

[0005] FIG. 707, G7
FIG. 08 is a diagram illustrating a multiplexing structure of SDH defined in G709.

In accordance with this recommendation, the digital path layers currently implemented in Japan include a layer for handling tributary unit (hereinafter referred to as "TU") 11 signals and an administrative unit (hereinafter referred to as "A").
U)).

The TU11 signal is a 1.5 Mb signal obtained by adding a path overhead (hereinafter referred to as “POH”) to a signal obtained by synchronously multiplexing a 64 Kbit / s signal for 24 channels.
It is a signal of it / s. Further, the AU3 signal is output from the TU11.
This is a 49 Mbit / s signal obtained by adding a POH to a signal obtained by multiplexing a signal for 28 channels. Here, the POH is a management information byte including management information on network operation.

When cross-connecting an SDH signal having such a multiplexing structure, a cross-connect device for each TU11 signal and a cross-connect device for each AU3 signal are required.

At present, such a cross-connect device has not been realized, but it is generally considered that a cross-connect for each TU11 signal and a cross-connect for each AU3 signal are realized by separate devices.

FIG. 3 is a block diagram showing the configuration of a cross-connect device when cross-connecting SDH signals in units of TU11 signals.

The illustrated apparatus includes a section overhead (hereinafter, referred to as "SOH") processing circuit 11, an AU pointer processing circuit 12, an AUPOH processing circuit 13, and a TU
A pointer processing circuit 14, a multiplexing circuit (MUX) 15,
Cross connect switch 16 and separation circuit (DMUX)
17.

Here, the SOH processing circuit 11 is a circuit for performing frame synchronization processing, error monitoring processing and the like of the SDH signal, and the AU pointer processing circuit 12 converts the SDH signal from the clock signal on the transmission line to the clock signal in the device. It is a circuit to change to.

The AUPOH processing circuit 13 is a circuit for performing an error monitoring process or the like at an upper layer level.
The U pointer processing circuit 14 is a circuit for changing the phase of the SDH signal from the phase of the transmission line to the phase in the device.

Further, the multiplexing circuit 15 is a circuit for multiplexing the SDH signals of a plurality of highways HW1 to HWn (n is an integer of 2 or more).
This is a circuit for exchanging the time slot of the DH signal for each TU11 signal, and the separating circuit 17 distributes the time slot converted multiplexed signal to each highway HWi (i = 1, 2,..., N) for each TU11 signal. Circuit.

FIG. 4 is a block diagram showing an example of the configuration of a cross-connect device for cross-connecting SDH signals in AU3 signal units.

The illustrated device comprises an SOH processing circuit 21 and A
A U pointer processing circuit 22, a multiplexing circuit 23, a cross connect switch 24, and a separating circuit 25,
The time slot conversion of the cross connect switch 24 is
The processing is performed in AU3 signal units.

[0017]

As described above, S
When configuring a cross-connect device used in a digital synchronization network based on DH, it is common to configure a separate device for each cross-connect unit.

However, such a configuration has a problem that a device must be developed for each cross-connect unit and a problem that a network change cannot be quickly dealt with.

Accordingly, an object of the present invention is to provide a cross-connect device which can be used for a plurality of required cross-connect units.

[0020]

To achieve the above object, the present invention provides a time slot conversion for converting a time slot of a transmission signal into a minimum cross connect unit among a plurality of required cross connect units. Means, and processing means for performing processing required for cross-connecting the transmission signal on a minimum cross-connect basis with respect to the transmission signal, and a cross-connect other than the minimum cross-connection unit from the processing means. Switching means for removing components unnecessary for cross-connecting on a unit basis or switching for inserting the unnecessary components into the processing means, and when cross-connecting a transmission signal in minimum cross-connect units Indicates that unnecessary components are inserted into the processing means, and cross-connect units other than this cross-connect unit are used. A switching operation control means for controlling a switching operation of the switching means so that unnecessary components are removed from the processing means, and an output of the processing means for cross-connecting a transmission signal in minimum cross-connect units. Split the signal into the smallest cross-connect units,
When the divided signals are time-division multiplexed for a plurality of highways and supplied to the time slot conversion means, and cross-connection is performed in a cross-connect unit other than the cross-connect unit,
Multiplexing means for virtually dividing the output signal of the processing means by the smallest cross-connect unit, time-division-multiplexing the divided signals for a plurality of highways, and supplying the resulting signal to the time slot conversion means, When cross-connecting in units of cross-connects other than units, time slot conversion is performed in units of this cross-connect,
The time slot conversion operation control means for controlling the time slot conversion operation of the time slot conversion means and the conversion output of the time slot conversion means are separated by the smallest cross-connect unit, and the separated output is processed by the processing means for each corresponding highway. And separating means for sorting.

[0021]

According to the above arrangement, when a transmission signal is cross-connected in minimum cross-connect units, the time slot conversion means and the processing means are used as they are.

On the other hand, when the transmission signal is cross-connected in units other than the minimum cross-connect unit, unnecessary components are removed from the processing means. Further, the output signal of this processing means is virtually divided by the smallest cross-connect unit, and time-division multiplexed with other highway signals. Further, the time slot conversion means is controlled so as to perform the time slot conversion in cross-connect units other than the minimum cross-connect unit.

Thus, one cross-connect device can be shared by a plurality of cross-connect units.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention.

In the following description, the present invention is referred to as SD
A case where the present invention is applied to a cross-connect device of a digital synchronous network based on H will be described as a representative.

In the following description, the present invention is referred to as a TU.
A description will be given of a case where a cross-connect of 11 signal units, a cross-connect of AU3 signal units, and a cross-connect of AU4 signal units are used as a representative.

This embodiment focuses on the following two points,
Using a cross-connect device for each TU11 signal, A
The cross connection is performed in units of U3 signals and AU4 signals.

A circuit for performing processing necessary for cross-connecting the SDH signal in units of TU11 signals is used for cross-connecting the SDH signal in units of AU3 signals or AU4 signals. Includes all circuits that perform the processing required to perform

Even a cross-connect switch that converts a time slot in TU11 signal units can be controlled to convert this time slot in AU3 signal units or AU4 signal units.

That is, in FIG. 1, reference numeral 30 denotes an input terminal to which an SDH signal to be cross-connected is applied, and reference numeral 31 denotes an output terminal to which a cross-connected SDH signal is led.

SDH supplied to these terminals 30 and 31
The signal is, for example, an STM (synchronous transfer module) -1 signal obtained by adding an SOH including management information on network operation to the AU3 signal or AU4 signal described above.

An SOH processing circuit 32 performs frame synchronization processing, error monitoring processing, SOH addition processing, and the like.
Reference numeral 33 denotes an AU pointer processing circuit that transfers the SDH signal from the clock signal on the transmission line to the clock signal in the device, or performs the reverse transfer.

Reference numeral 34 denotes an AUPOH processing circuit which performs error monitoring processing in the upper layer, POH addition processing, and the like.
Reference numeral 35 denotes a TU pointer processing circuit that switches the phase of the SDH signal from the phase of the transmission line to the phase in the device, or reverses the phase. The TU pointer processing circuit 35 includes a TU pointer processing unit 351 and a bit buffer 352.

Reference numeral 36 denotes a plurality of highways HW1 to HWn.
This is a multiplexing circuit that time-division multiplexes (n is an integer of 2 or more) SDH signals in TU11 signal units. 37 is a multiplexing circuit 3
6 is a cross-connect switch for switching the multiplex output time slots in TU11 signal units. Reference numeral 38 denotes a separation circuit that distributes the output of the cross-connect switch 38 to each highway HWi (i = 1, 2,..., N) in TU11 signal units.

Reference numeral 39 denotes a switching circuit for performing switching for inserting or removing the AUPOH processing circuit 34 from the apparatus. The switching circuit 39 includes a switch 391 arranged on the input side of the AUPOH processing circuit 34 and a switch 392 arranged on the output side. The switches 391 and 392 are configured to switch in conjunction with each other based on a control signal output from a control circuit described later.

Reference numeral 40 denotes a switching circuit for performing switching for inserting or removing the TU pointer processing unit 351 from the apparatus. The switching circuit 40 includes a switch 401 disposed on the input side of the TU pointer processing unit 351 and a switch 402 disposed on the output side. Both switches 401 and 402 are configured to switch in conjunction with each other based on a control signal output from a control circuit described later.

A control circuit 41 controls the operation of the switching circuits 39 and 40 and the operation of the cross-connect switch 37 based on, for example, an instruction from a network management device (not shown).

In this case, the movable contacts a of the switches 391, 392, 401, 402 of the switching circuits 39, 40 are:
In the case of performing a cross-connect for each TU11 signal, the signal is connected to the fixed terminal b. Thereby, in this case, all the circuits 32 to 35 necessary to execute the cross connect in the unit of the TU signal are connected between the input terminal 30 and the multiplex circuit 36.
And it is inserted between the separation circuit 38 and the output terminal 31.

On the other hand, AU3 signal unit or AU3 signal unit
When cross-connecting in units of four signals, the fixed terminal c
Connected to. Thus, in this case, only the circuits 32 and 33 necessary to execute the cross connect in the AU3 signal unit or the AU4 signal unit are provided between the input terminal 30 and the multiplexing circuit 36 and between the separation circuit 38 and the output terminal 31. It will be inserted in between.

However, with respect to the TU pointer processing circuit 35, only the TU pointer processing section 351 is removed, and the bit buffer 352 stores the data delay time in the cross connect in units of TU11 signals and the cross connect in units of AU3 signals (or AU4 signals). Is left as it is as a delay circuit for adjusting.

As described above, the conversion unit of the cross connect switch 37 is set for each TU11 signal, but the conversion direction is determined for each cross connect.

The cross-connect switch 37
Is constituted by, for example, a one-stage time switch. The time switch has a data memory for storing input data, and performs time slot conversion by controlling writing or reading of the data memory.

Here, the basic configuration and operation of the time switch will be described for reference with reference to FIG.

FIG. 5 is a block diagram showing the principle configuration of the time switch. The illustrated time switch performs time slot conversion by controlling reading of the data memory.

That is, in the figure, reference numeral 51 denotes an input common line for inputting a multiplex signal. 52 is a data memory (DM) for storing the multiplexed signal on the input common line 51. This data memory 52 is constituted by a random access memory.

An address control memory (ACM) 53 generates a read address of the data memory 52. An address counter (AC) 54 generates a write address of the data memory 52 and a read address of the address control memory 53. Reference numeral 55 denotes an output common line for outputting the time-slot-converted multiplexed signal.

The operation of the above configuration will be described. Data A, B, C, contained in the multiplexed signal on the input common line 51,
D is sequentially written to the data memory 52 based on the sequential write address output from the address counter 54.

When the writing is completed, the read address of the data memory 52 is written to the address control memory 53. This writing is performed by the control circuit 41 of FIG.
Made by

When the writing is completed, the read addresses of the data memory 52 are sequentially read from the address control memory 53 based on the sequential write addresses output from the address counter 54.

As a result, data A, B, C, and D are read from data memory 52. Therefore, if the contents stored in the address control memory 53 are set in accordance with the order in which the data A, B, C, and D are to be read, a desired time slot conversion can be executed.

In the example shown, the read addresses 1, 2, 3, and 4 are stored in the address control memory 53 as 4 → 1 → 2.
→ Since data is stored in the order of 3, data A, B, C, D
Are read out in the order of D → A → B → C.

The principle of the time switch has been described above. In this embodiment, the contents stored in the address control memory 53 are set by the control circuit 41 so that the conversion direction of the time slot is determined on a cross-connect basis. .

For example, when performing a cross-connect in AU3 signal units, a plurality of signals in TU11 signal units obtained from a certain AU3 signal are always stored in the address control memory 53 so as to be output in the same direction. Is set.

The configuration of one embodiment has been described above. Next, the operation of the above configuration will be described.

(1) First, the operation in the case of performing the cross-connect for each TU11 signal will be described.

In this case, the switches 391, 392, 40
Each of the movable contacts 1 and 402 is connected to the fixed contact b. Thereby, in this case, all the circuits 32 to 35 required for the cross connection in units of the TU11 signal are inserted between the input terminal 30 and the multiplexing circuit 36 and between the separation circuit 38 and the output terminal 31.

In such a state, the AU3 signal or the AU4 signal is input to the input terminal 30 as an upper layer signal.
An SDH signal including a signal is input. FIG. 6 shows this SD
It is a figure showing the structure of the H signal. As shown in the figure, the SDH signal includes an SOH, an AU pointer (PTR), and a payload. Management information necessary for network operation is inserted in the SOH. In the payload, three AU3 signals or one AU4 signal is inserted.

The SDH signal is supplied to the SOH processing circuit 32, where it is subjected to frame synchronization processing for frame synchronization and error monitoring processing for checking whether an error has occurred. These processes are performed based on a frame synchronization bit and an error detection bit included in the SOH.

By this processing, the SOH is extracted from the SDH signal as shown in FIG. The SDH signal from which the SOH has been extracted is supplied to the AU pointer processing circuit 33, and is replaced with a clock signal in the device from a clock signal on the transmission line. The SDH signal after this transfer is
Since the movable contact a of the switch 391 is connected to the fixed terminal b, it is supplied to the AUPOH processing circuit.

FIG. 8 is a diagram showing the structure of the VC3 signal or VC4 signal included in the SDH signal supplied to the AUPOH processing circuit 34. As shown, this VC3 signal or VC4 signal is composed of a POH and a payload.

Management information necessary for network operation is inserted in the POH. This POH is T for the AU3 signal.
It has the number of bytes for two U11 signals. In contrast, A
In the case of the U4 signal, the number of bytes is six for the TU11 signal. In the case of an AU3 signal, 28 TU11 signals are inserted in the payload. On the other hand, in the case of the AU4 signal, 84 TU11 signals are inserted.

The SD supplied to the AUPOH processing circuit 34
The H signal is subjected to an error monitoring process or the like in an upper layer.
That is, it receives an error monitoring process at the AU3 signal or AU4 signal level. This error monitoring processing is performed by A
This is performed based on an error detection bit or the like included in the POH of the U3 signal or the AU4 signal.

By this processing, the AU3 signal or the AU3 signal
The four signals are extracted from the POH as shown in FIG.
S including the C3 signal or C4 signal obtained by this
The DH signal indicates that the movable contact a of the switch 401 is fixed contact b
Is supplied to the TU pointer processing circuit 35.

Thus, the SDH signal is changed from the phase of the transmission line to the phase in the device. As a result, A
2 included in the payload of U3 signal or AU4 signal
The eight or 84 TU11 signals are rearranged so that the pointers Vx are aligned as shown in FIG.

The switched SDH signal is supplied to the multiplexing circuit 36 and time-division multiplexed with the SDH signals from the other highways HW2 to HWn. At this time, the AU3 signal or the AU4 signal is, as shown in FIG.
It is divided in units of one signal. Then, each TU11 signal obtained by this division is time-division multiplexed with the TU11 signals of the other highways HW2 to HWn, as shown in FIG.

In FIG. 12, HiTm (i =
, N, m = 1, 2, ..., 28 (84))
13 shows the m-th TU11 signal of the highway HWi. FIG. 12 shows multiplexing of AU3 signals as a representative.

The multiplexed signal output from the multiplexing circuit 36 is
The signal is supplied to the cross-connect switch 37 and is subjected to time slot conversion for each TU11 signal. This conversion operation will be described later in detail.

The SDH signal after the time slot conversion is supplied to the separation circuit 38 and distributed to each highway HWi in TU11 signal units. The SDH signal of the highway HW1 obtained by this distribution is defined as
After receiving the reverse process, the signal is guided to the output terminal 31.

That is, the SDH signal of the highway HW1 output from the separation circuit 38 is supplied to the TU pointer processing circuit 35, and the TU pointer is added from the phase in the device. The SDH signal to which this addition has been completed is transmitted to the switch 40.
2 is connected to the fixed terminal b.
The POH is supplied to the UPOH processing circuit 34 and POH is added thereto.

Thereafter, the SDH signal is supplied to the AU pointer processing circuit 33 since the movable contact a of the switch 392 is connected to the fixed terminal b, and the AU pointer is added from the clock signal in the device. SD with this addition
The H signal is supplied to the SOH processing circuit 32, where the SOH is added. As a result, an SDH signal obtained in the output terminal 31 in the same form as the SDH signal supplied to the input terminal and cross-connected for each TU11 signal is obtained.

The above is the overall operation in the case of performing the cross-connect for each TU11 signal. Next, FIGS.
Some specific examples of the time slot conversion operation of the cross connect switch 37 will be described with reference to FIG.

In the following description, the number n of highways is set to 2 and the number of TU11 signals included in the AU3 signal or the AU4 signal is set to 2 for the sake of simplicity.

FIG. 13 shows a case where time slot conversion is not performed within the highway, and only time slot conversion between the highways is performed.

In this case, the TU11 signal is H1T1 → H
In the order of 2T1 → H1T2 → H2T2, the data memory 52
Is written to. On the other hand, the address control memory 5
3, the read address of the data memory 52 is written in the order of 2 → 1 → 4 → 3.

As a result, the TU11 signal written in the data memory 52 changes from H2T1 → H1T1 → H2T2 →
The data is read out in the order of H1T2. As a result, Highway H
This means that the time slot conversion between W1 and HW2 has been performed.

FIG. 14 shows a case where time slot conversion between highways is not performed, and only time slot conversion within a highway is performed. However, in the figure, the highway HW
The case where only the time slot conversion within 1 is performed is shown as a representative.

In this case, the address control memory 5
3, the read address of the data memory 52 is written in the order of 3 → 2 → 1 → 4. As a result, the TU11 signal written in the data memory 52 becomes H1T2 → H2
The data is read in the order of T1 → H1T1 → H2T2. As a result, the time slot conversion in the highway HW1 has been executed.

FIG. 15 shows a case where both time slot conversion within a highway and time slot conversion between highways are performed.

In this case, the address control memory 5
3, the read address of the data memory 52 is written in the order of 4 → 3 → 2 → 1. As a result, the TU11 signal written in the data memory 52 is changed from H2T2 to H1.
The data is read in the order of T2 → H2T1 → H1T1. As a result, the time slot conversion within the highway and between the highways is performed.

(2) Next, an operation in the case of performing a cross connect in AU3 signal units will be described.

In this case, an SDH signal including an AU3 signal is supplied to the input terminal 30 as a signal of an upper layer.

The switches 391, 392, 401,
The movable contacts a of 402 are all connected to the fixed contacts c based on a control signal output from the control circuit 41.
As a result, only the circuits 32 and 33 required for the cross connection of the AU3 signal unit are inserted between the input / output terminal 30 and the multiplexing circuit 36 and between the separation circuit 38 and the output terminal 31, and the crossover of the TU11 signal unit is performed. Circuits 34 and 35 required only for connection are not inserted.

However, regarding the TU pointer processing circuit 35, only the TU pointer processing section 351 is not inserted, and the bit buffer 352 is left as it is for time alignment.

Since the AUPOH processing circuit 34 has been removed, the multiplexing circuit 36 is supplied with the AU3 signal including the POH. Further, since the TU pointer processing unit 351 is removed, the multiplexing circuit 36 is supplied with the AU3 signal in which the pointer Vx of the TU11 signal is not aligned.

The AU3 signal supplied to the multiplexing circuit 36 is
The POH is virtually considered as two TU11 signals, and FIG.
As shown in FIG. 6, the signal is virtually divided into 30 TU11 signals. Hereinafter, the TU11 signal thus obtained is referred to as a virtual TU11 signal.

Each virtual TU11 signal is transmitted to another highway H
It is multiplexed with the virtual TU11 signal from W2 to HWn. This multiplexed signal is supplied to the cross-connect switch 37 and time-slot-converted for each virtual TU11 signal. At this time, the contents stored in the address control memory 53 are 30 virtual T divided from the same AU3 signal.
The contents are set such that the U11 signal is always output in the same direction.

That is, as in the case of FIG. 13 described above, 30 virtual TU1s divided from the same AU3 signal are used.
One signal is output to the same highway,
Time slot conversion is performed. As a result, the cross connect is performed for each AU3 signal.

The output of the cross connect switch 37 is guided to the output terminal 31 via the separation circuit 38, the bit buffer 352, the AU pointer processing circuit 33, and the SOH processing circuit 32.

(3) Finally, the operation in the case of performing a cross connect in AU4 signal units will be described.

In this case, an SDH signal including an AU4 signal is supplied to the input terminal 30 as a signal of an upper layer. The movable contacts a of the switches 391, 392, 401, and 402 are all connected to the fixed contact c, as in the case of performing a cross-connect in AU3 signal units.

As a result, the AU4 signal including the POH and having the pointer Vx of the TU11 signal not aligned is supplied to the multiplexing circuit 37, as in the case of performing the cross connection in the AU4 signal unit.

The AU4 signal supplied to the multiplexing circuit 36 is
The POH is virtually considered as six TU11 signals, and FIG.
As shown in FIG. 6, the signal is virtually divided into 90 TU11 signals. This virtual TU11 signal is transmitted to another highway HW.
After being multiplexed with virtual TU11 signals from 2 to HWn, time slot conversion is performed for each virtual TU11 signal. At this time, the content stored in the address control memory 53 is
The content is set such that 90 virtual TU11 signals divided from the same AU4 signal are always output in the same direction.

As described in detail above, this embodiment focuses on the following two points, and uses the switching circuits 39 and 40 and the control circuit 41 to connect the TU11 signal unit cross-connect device to the AU3 signal unit and AU4 signal unit. This is also used as a cross connect for each signal.

The circuits 32 to 35 that perform processing necessary for cross-connecting the SDH signal in units of TU11 signals are provided to the SDH signal.
Circuits 32 and 3 for performing processing necessary for cross-connecting the SDH signal in AU3 signal or AU4 signal units.
3 is included.

[0095] Even in the cross-connect switch 37 that converts a time slot in TU11 signal units, the time slot can be converted in AU3 signal units or AU4 signal units by appropriately setting the storage contents of the address control memory 53. it can.

(1) According to such a configuration, it is not necessary to develop a device for each cross-connect, and it is possible to quickly cope with a network change.

(2) The switching circuit 3 can be used without changing the cross-connect device for each TU11 signal.
By simply adding the control circuits 41 and 41 and the control circuit 41, it is possible to realize a cross-connect device that can be used for both the AU3 signal unit cross-connect and the AU4 signal unit cross-connect.

The embodiment of the present invention has been described above.
The present invention is not limited to such an embodiment.

(1) First, in the above embodiment, the case where a switch composed of a one-stage time switch is used as the cross-connect switch 37 has been described. A switch composed of a switch and a space switch may be used.

In other words, the present invention at least
It has time slot conversion means such as a time switch,
What is necessary is just to perform cross-connect by this means.

(2) In the above embodiment, the operation of each unit of the TU11 signal, AU3 signal, and AU4 signal has been described. However, the switching circuits 39 and 40 and the control circuit 41 are operated for each input multiplex signal. Accordingly, the present invention can be applied to a device in which signals of respective units are mixed and cross-connected simultaneously.

(3) In the above embodiment, the case where the present invention is applied to the cross connect of the TU11 signal unit, the AU3 signal unit, and the AU4 signal unit has been described. Can also be applied.

(4) Further, in the above embodiment, the case where the present invention is applied to a cross-connect device of a digital synchronous network based on SDH has been described. The present invention can also be applied to a connecting device.

(5) In addition, it goes without saying that the present invention can be variously modified and implemented without departing from the scope of the invention.

[0105]

As described in detail above, according to the present invention,
It is possible to provide a cross-connect device that can be used for a plurality of cross-connect units.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a multiplexing structure of SDH.

FIG. 3 is a block diagram showing a configuration of a cross-connect device for each TU11 signal.

FIG. 4 is a block diagram illustrating a configuration of a cross-connect device for each AU3 signal.

FIG. 5 is a block diagram showing a principle configuration of a time switch.

FIG. 6 is a diagram showing a structure of an SDH signal supplied to an input terminal.

FIG. 7 is a diagram illustrating a structure of an SDH signal output from an SOH processing circuit.

FIG. 8 is a diagram illustrating a structure of an AU3 signal or an AU4 signal supplied to an AUPOH processing circuit.

FIG. 9 is a diagram illustrating a structure of a VC3 signal or a VC4 signal output from an AUPOH processing circuit.

FIG. 10 is a diagram illustrating a structure of a C3 signal or a C4 signal output from a TU pointer processing circuit.

FIG. 11 is a diagram showing how an AU3 signal or an AU4 signal is divided in units of a TU11 signal.

FIG. 12 is a diagram illustrating a state in which AU3 signals are multiplexed in TU11 signal units.

FIG. 13 is a diagram for explaining time slot conversion between highways.

FIG. 14 is a diagram for explaining time slot conversion in a highway.

FIG. 15 is a diagram for explaining time slot conversion between highways and within a highway.

FIG. 16 shows an example in which an AU3 signal or an AU4 signal is converted to a virtual TU1 signal.
FIG. 3 is a diagram illustrating a state of division in units of one signal.

[Explanation of symbols]

30 input terminal, 31 output terminal, 32 SOH processing circuit, 33 AU pointer processing circuit, 34 AUPOH processing circuit, 35 TU pointer processing circuit, 36 multiplexing circuit, 37 cross-connect switch, 38 separation circuit,
39, 40: switching circuit, 41: control circuit, 351: T
U pointer processing unit, 352... Bit buffer, 391,
392, 401, 402... Switches.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04J 3/00 H04Q 3/52 101 H04Q 11/04 301

Claims (1)

(57) [Claims] 1. A cross-connect device provided in a digital synchronization network for cross-connecting a transmission signal synchronously multiplexed over a plurality of digital path layers, wherein a time slot of the transmission signal is set to a plurality of required cross-connects. A time slot conversion unit that converts the minimum cross-connect unit among the units, and a processing unit that performs a process necessary for performing cross-connection on the transmission signal in the minimum cross-connection unit, A switch for removing an unnecessary component from the processing means for cross-connecting the transmission signal in a cross-connect unit other than the minimum cross-connect unit, or for inserting the unnecessary component into the processing means. Switching means for performing a cross-connect in the minimum cross-connect unit. In the case where the connection is made, the unnecessary component is inserted into the processing unit, and when the cross connection is performed in a cross-connect unit other than the cross-connect unit, the switching unit is configured so that the unnecessary component is removed from the processing unit. Switching operation control means for controlling the switching operation of, when the transmission signal is cross-connected in the minimum cross-connect unit, the output signal of the processing means is divided in the minimum cross-connect unit, and this divided signal When a plurality of highways are time-division multiplexed and supplied to the time slot converting means, and when cross-connecting is performed in a cross-connect unit other than the cross-connect unit, an output signal of the processing means is virtually reduced to the minimum cross-connect. And divides the divided signal by time division multiplexing for a plurality of highways to obtain the time slot. Multiplexing means for supplying to the conversion means; and when the transmission signal is cross-connected in a cross-connect unit other than the minimum cross-connect unit, the time slot conversion means is used so that the time slot conversion is performed in this cross-connect unit. A time slot conversion operation control means for controlling the time slot conversion operation of the above, and a conversion output of the time slot conversion means is separated for each of the minimum cross-connect units, and the separated output is distributed to the processing means for each corresponding highway. A cross-connect device comprising: a separating unit.