JPH02276339A - High-speed ring lan system and lan node - Google Patents

Abstract

PURPOSE:To store two or more low-order networks, especially, public networks and LANs different in signal transmission speed by providing each of plural node devices, which are connected to one another by a ring transmission line, with interface means for the storage of low-order networks and switching fixed length packets between interface means and communication frames. CONSTITUTION:A high-order LAN 200 is constituted of nodes 1A to 1D and a transmission line 2, and a low-order network 201 constituted of nodes 3A and 3B and an optical fiber transmission line 4 is connected to the node 1A, and a low-order network 202 constituted of nodes 5A and 5B and a transmission line 6 is connected to the node 2A. Each of nodes 1A to 1D of the high-order LAN is provided with plural low-order network interfaces (user device interfaces), and one node can store plural input/output devices or low-order networks. At the time of constituting a network system, a 9-bit output terminal address unique in the system is given to the output terminal of each node which is connected to a low-order network interface.

Description

[Detailed description of the invention]

[Industrial Application Field 1] The present invention relates to a ring LAN system, and more specifically,
The present invention relates to a multi-ring LAN system suitable for high-speed data transmission, and a node device constituting the same. [Prior Art] Conventionally, regarding a bus type LAN having a transmission speed of 150 Mbps, for example, IE Communication Magazine Vol. 26 No. 4 (1988) No. 2
Pages 0 to 28 (IEEECommunication
n Magazine Vol, 26, No, 4
(1988) pp, 2O-28). Regarding a ring LAN with a transmission speed of 200 Mbps, the parent node in a slotted ring stores received information in a buffer so that the loop circuit delay is an integral multiple of the frame length. G
LOBECOM '851-4). Furthermore, this document describes a system in which all nodes operate using a clock extracted from a received signal. In addition, regarding the traditional slotted ring access method in which a node that has gained access and used a slot always empties the used slot after the ring cycle, see I.E.E. Transactions on Communications Com 29, (1981) No. 1
Page 466 (IEEE. Trans, Communications, CO
M-29 (1981) p. 1466. Furthermore, ATM (Async), which was used in conventional ring LAN,
ronous Transfer Mode) cell format is based on IEICE Switching System Study Group Material 5SE8
8-93.

[Problem to be solved by the invention]

Conventionally, high-speed ring L with a transmission speed of 100 Mbps or more
In AN, the transmission speed is based on 100 Mbps and is an integral multiple of 100 Mbps. On the other hand, public networks use 155.52 Mbps, which is the standard transmission speed of the International Telegraph and Telephone Advisory Committee, as the transmission speed.
When interconnecting an AN and a public network, a buffer for matching the transmission speeds of both is required, which poses a problem of increasing the size of the connecting device. Also, in multiple ring type exchanges, as a countermeasure to the demand for speeding up the ring connection processing unit due to multiplexing. In the conventional method, each node is provided with a transmitting buffer memory and a receiving buffer memory corresponding to each ring, and the information to be transmitted to other nodes is stored redundantly in the transmitting buffer memory of each ring, and then sent to each ring without duplication. On the other hand, cells sent to the own node on the ring are stored in the reception buffer memory of the ring at positions corresponding to the sending node and transmission order, and are stored in the reception buffer memory of the ring with the machine number. It is decided that the same address will be accessed at the same time and information will be retrieved. According to the above conventional method, the transmitting/receiving buffer memory can operate at the speed of the ring even when there are multiple rings, but the buffer memory for the number of rings (n) is provided in each node. It is necessary to prepare. In addition, each node has 2n inputs and outputs for relaying on the ring,
Since a total of 4n inputs/outputs (2n inputs/outputs to ring-compatible transmitting/receiving buffers) are required, there is a problem in that the amount of buffers and the amount of hardware increases exponentially as the number of inputs/outputs of nodes increases. In conventional slotted rings, the parent node buffers received information so that the ring round trip delay is an integral multiple of the frame length, which increases the delay and reduces the throughput between user equipment. there were. Furthermore, conventionally, regarding cell transmission rights, there are two methods: one prohibits continuous use of the transmission area of the own node's transmission cell, and the other method does not impose any restrictions.In order to achieve fair access, the former method is adopted. is common. As a means for realizing the former method, for example, each node has a user information buffer that stores user information to be transmitted in user transfer units that are longer than cells, and a cell buffer that stores cells obtained by dividing the user transfer information. and. in this case,
Since continuous use of the sending area of the own node's sending cell is prohibited, each node must either find a sending area of another cell or wait for the sending area of the own node's sending cell to go around the ring further. . Therefore, when a specific user is exclusively using the ring, the cell buffer release time of the node accommodating that user is delayed, resulting in an increase in the overflow probability of the user information buffer. There was a problem. An object of the present invention is to provide a high-speed ring LAN system suitable for accommodating two or more lower-level networks with different signal transmission speeds, particularly a public network and a LAN. Another object of the invention is to support the transmission of asynchronous information which is buffered in the user equipment and can be handled independently of the frame period, and the transmission of synchronous information where it is necessary to guarantee a constant frame period. The object of the present invention is to provide a high-speed ring LAN system that can be realized using a relatively small capacity buffer. Still another object of the present invention is to provide a node device that enables signal transmission between a high-speed ring LAN and a lower network with relatively low-speed signal processing capability. Another object of the present invention is to provide a multi-ring LAN in which cell transmission delay can be reduced to only ring propagation delay and intra-node cell processing delay, which can increase throughput between user equipments and reduce the amount of hardware. It is about providing. (Means for Solving the Problems) In order to achieve the above object, the high speed ring L according to the present invention
The AN system includes at least one ring-shaped transmission path;
It consists of a plurality of node devices interconnected by the ring-shaped transmission path, and each node device includes at least one interface means for accommodating a lower network, and each of the transmission paths includes a plurality of fixed-length packet areas. means for forming n channels (n is an even number) for transmitting communication frames at a signal transmission rate of 155.52 Mbps; and exchange of fixed length packets between each of the communication frames and the interface means. It is characterized by comprising a means for carrying out the operation. Another feature of the present invention is to prohibit distributed transmission of cells generated from the same user transfer information to arbitrary rings, and to install a reception determination function compatible with user equipment in front of the reception buffer, that is, in a switch or an access control unit. It's about having it. In order to improve the relay delay caused by the parent node and improve the input loop between user devices, the present invention separates the frame generation function and the relay function in the parent node, and generates buffered received information. The information is inserted into the information transfer area of the frame and relayed regardless of the frame position at the time the information is received. Furthermore, in order to reduce the overflow probability of the user information buffer, the present invention allows continuous use of the transmission area of the own node's transmission cell in units of user transfer information.

[Operation 1] According to the above configuration, each node device has, for example, 100 M
When accommodating three low-level bps LANs, by using two channels, the low-level LAN and high-speed ring LA
The data transmission speed can be almost matched with that of N, and the speed difference between the input side and the output side of the interface device can be almost eliminated. In addition, when accommodating a public network,
By allocating one channel to one public network, the input and output speeds of the interface can be completely matched. In the present invention, the communication frame sent to each channel is, for example, a SONE consisting of a section overhead area (SOH) of 9 bytes x 9 and a container 4 (VC-4) area of 261 bytes x 9. T (
5ynchronous 0ptical N E T
ork) frame, and the fixed length packet is
It can be inserted into the C-4 area and transmitted. In the present invention, if the address of each interface is associated with a specific channel in advance, and the originating node sends the packet to a communication frame on the channel selected according to the destination address of the transmitted packet, Since the receiving node only needs to receive packets addressed to one interface from communication frames on a specific highway, the received packets can be output to the interface without being routed. In the present invention, the cell header is given source and destination call numbers that can identify the user equipment input/output of the switch or cell access control unit. According to the present invention, cells generated from the same user transfer information are sent out on the same ring, so that the switch or cell access control unit can make relay/reception decisions depending on the user equipment. Further, the input/output of user devices only needs to be as many as the number of connected user devices, and reception buffers may be provided for each user device. According to the present invention, when cells are transmitted to a ring with the lowest traffic, it is possible to improve transmission efficiency. Also, if you control the sending of cells to a specific ring corresponding to the destination node, the receiving node will only receive cells destined for itself from the specific ring, so the maximum reception speed will be the ring speed - the main speed. , and the node operation speed can be reduced. Further, by setting the priority given to the priority information area of the cell header so that the priority of the relay cell is higher than that of the transmitting cell, intra-node delay due to relay can be reduced. Embodiment FIG. 1 shows an example of the overall configuration of a network system according to the present invention. In the figure, the upper LAN (Local Area Ne
A lower network 201 consisting of nodes 3A, 3B and an optical fiber transmission line 4 is connected to the node IA, and a lower network 201 consisting of nodes 5A, 5B and a transmission line 6 is connected to the node 2A. 20
2 are connected. The lower network 201 handles packet switching information, for example, ANS 1 (Ameri
can National 5 standard In
5 titute) compliant transmission speed of 100 Mbps
AN, and the lower level network 202 has a standard transmission speed of, for example, the International Telegraph and Telephone Advisory Committee, 155.52.
It is a public packet network with a transmission speed of Mbps. A camera 214 and a monitor 215, which handle circuit switching information, are connected to the node IC and ID, respectively. In the morning of Figure 1, the upper LAN 200 contains only four nodes, but in reality there are many more (for example, 120).
nodes can be connected, and multiple lower LANs and multiple public networks can communicate via the upper LAN 200. Also, top L
- The nodes IA to ID of the AN each have a plurality of lower network interfaces (user device interfaces), and one node can accommodate a plurality of input/output devices or lower networks. In addition, in the figure, nodes 3A, 3B, 5A, and 5B of the lower network accommodate terminal devices 210 to 213, respectively, but these nodes are equipped with the slower token ring based on the IEEE 802 standard committee, voice It can also accommodate other communication systems such as PBXs that handle information. In the present invention, the upper LA
The information transmission speed on the N200 transmission line 2 is the public network transmission speed 155.52 Mbps and the LAN transmission speed 1.
155.52Xn (n
is an even number) Mbps. FIG. 2 shows an example of the configuration of a time division multiplex transmission frame 10 flowing on the transmission path 2. As shown in FIG. In this example, the time division multiplex transmission frame rubber 10 has 16 SOs each consisting of 270 bytes x 9 columns and generated in a period of 125 μsec.
N E T (Synchronous Optica
l N E T work) Frames 11-1 to 11
-16 multiplexed in 1-byte units, and the transmission speed is 155.52 Mbps x 16. This is logically equivalent to having 16 transmission lines. In the present invention, a structure in which each channel has 16 optical fibers having a transmission speed of 155.52 Mbps is also possible. In each 5ONET frame 11, as shown in FIG. 3(A), each column has a 9-byte section overhead (
It consists of a SOH) area 12 and a Verticel Container 4 (VC-4) area 13 of 261 bytes. S
The OH area 12 contains, for example, a frame synchronization pattern, 15
5.52 Mbps unit identifier (SONET frame I
D) and inter-node communication control information such as an AU pointer indicating the start position of the container, which will be described later. Furthermore, the last three bytes of each SOH area are used as a dummy area for stuffing, which will be described later. In the VC-4 area 13, as shown in FIG. 3(B), each column is a 1-byte path overhead (POH) area 14 for storing control information used in a public network multiplexing device.
For example, if 61 cells 16 consisting of a cell transfer area 15 of 260 bytes are 69 bytes long, each 5 ONE
The T frame can accommodate a total of 33 cells in the cell transfer area, and the remaining 63 bytes become an invalid area 19. In addition, in the present invention, in order to increase the number of cells to be accommodated. The POH section may be omitted. FIG. 4 shows an example of the format of the cell 16. The cell 16 has a 1-byte access field (ACF) 16A,
It consists of a 4-byte header area 16B and a 64-byte information area 16C. The ACF area 16A contains a validity indicator bit 17V indicating whether or not the content of the cell is valid, and the information area 16C contains packet switching information 9 circuit switching information,
a type bit 17S indicating any of the inter-node control information;
Broadcast indicator bit 17B indicating whether the cell in question is a broadcast cell
, a monitor bit 17M for monitoring infinite circuits of cells due to bit errors or node failures, and a reserve bit 17R. In addition, the header area 16B contains a total of 20 bits of call number 1.
8N, a 2-bit priority display bit 18P indicating the priority of cell exchange, a reserve bit 18R, and the AC
8 for error detection in F area 16A and header area 16B
Bit error check sequence 18C
That's what I mean. In each node, a unique 9-bit output terminal address within the system is assigned to the output terminal connected to the lower network interface when the network system is constructed. The call number 18N consists of a combination of the above output terminal addresses at the destination node and the source node. Each node sets a valid bit in the validity indicator bit 17V when transmitting a cell, and when erasing a cell, sets the validity indicator bit to an invalid state and clears the call number 18N to zero. Figure 5 shows time division multiplexed frame 1 circulating on transmission path 2.
one 5ONET frame 11 forming part of 0;
The relationship with the container sent out on the 5ONET frame is shown. Each node 1 included in the upper LAN 200
generates 16 5ONET frames 11-1 to 11-16 based on the individual basic clocks output from the clock generator of each node, and transmits frame 10, which is obtained by time-division multiplexing these frames, to the transmission line 2. to neighboring nodes via. Therefore, each 5 ONET frame received 1
1, the frame period is 125 μSeC±α, reflecting the error in the basic clock of the source node (upstream node). In the upper LAN 200, one reference node (parent node) in the ring is used to achieve communication with a 125μSee cycle between all nodes connected via transmission path 2.
The container 20 generated at a cycle of 125 μsec is used. The total length of the container 20 is the same size as the total length of the cell area of the 5ONET frame (260 x 9 bytes), and there are 33 slot areas each having a length of 69 bytes, which is the same size as the cell 16. It consists of an invalid area of the remaining size. container 20
The contents of each slot are written in the cell area of the 5ONET frame 11 and delivered to the adjacent node. A node that receives a 5ONET frame generates a container in synchronization with the cycle of the received container, and places this on the 5ONET frame that each node independently generates. The difference between the frame period and the container period is absorbed by moving (stuffing) the starting position ST of the container in the 5ONET frame, and the starting position ST is
It is stored in the SOH unit 12 as an AU pointer. FIG. 6 shows another example of the format of the cell 16. In this cell, the information area 16C is 48 bytes, and the total length of the cell is shorter than that in FIG. 4. The ACF area 16A also includes a validity indicator bit 17V, an information type indicator bit 17S, a monitor bit 17M, and an access level indicator bit 17A indicating the priority level of information that can use the cell area (slot area). It consists of a release indicator bit 17L, which indicates that some node is requesting release of this slot, and a reserve bit 17R. The header area 16B consists of a 12-bit destination address 18D, a 12-bit source address 18S, and a header check sequence 18C, and the first bit of the destination address indicates whether or not it is a broadcast cell. Figure 7 shows an example in which the POH area is deleted and the entire 261x9 byte VC-4 area 13 is used for transmitting cell information in order to set a large amount of cell information in the 5ONET frame 11. This figure shows the case where 5OHI is immediately followed by 5OHI. When the POH area is deleted, the 53-byte cell becomes VC-
44 pieces can be placed in 4 areas, and 17 pieces can be placed in the invalid area 19.
Becomes a part-time worker. FIG. 8 shows the basic configuration of node IA. Other node IB
~ID also has the same configuration. Node IA is powered by 17 people (signal lines 3o-1 to 3O-17
), a switch unit 20 for intra-slot information exchange having 17 outputs (signal lines 31-1 to 3l-17);
an optical/electrical converter (0/E) 21 for converting an input optical signal from the optical fiber transmission line 2 into an electrical signal; and a converter 2
The received signal of 155.52 x 16 Mbps output from 1130-1 to 1130-16 is separated into 16 highways (channels), and the contents of the cell area of 5 ONET frames reproduced for each channel are transmitted through signals 1130-1 to 30-16. The separation unit 22 that sends data to the switch unit 20, the user equipment interface 23 connected between the signal lines 30-17 and 31-17, and the slot information output from the switch 20 are assembled into 5 ONET frames for each channel. Also, a multiplexing unit (MPX) 24 that time-division multiplexes these in byte units, and the multiplexing unit 2
an electrical/optical converter (Elo) 25 that converts the electrical signal output from 4 into an optical signal and outputs it to the optical fiber transmission line 2;
and a parameter setting device 26. When using 16 optical fibers for each channel, the splitter section 22 and MPX 24 are not necessary, and the O/E 21 is used instead.
．． E1025 is required for each channel. FIG. 9 shows the function of switch 20. In this example, the switch 2o has 17 input channels and 17 output channels, of which one pair of input/output channels (signal line 30
-17 and 3l-17) is the user equipment interface 23
and other input/output channels (signal lines 30-1 to 30-3).
0-16° 31-1 to 3l-16) correspond to each channel of the time division multiplex frame 10. Input signal line 30
The cell information input from -k (k=1 to 16) is sent to the output signal line 31-17 if this is addressed to the own node.
In other cases, it is exchanged (output) to the output signal line 31-k. If a method is adopted in which each cell information is erased at its source node, each node makes a copy of the cell information addressed to its own node, and sends the received cell (or duplicate cell) to the output line 31-k. (or received cell) to 31-
17. In each switch, one output signal line 31 . In order to avoid concentration of cell information on -17, it is preferable to allocate channels to be used for each node in advance. For example, when sending information from node IA to node IC and ID, the first channel 31-1. When sending information to node IB, it is decided to use the second channel 31-2. Similarly, if the first channel is used to send information from node IB to node IC and LD, node IC
, LD, cell information addressed to its own node is received only from the input signal line 31-1 in principle, and it is possible to prevent cells from crossing over toward the output signal line 31-17. Input signal line 30-1 from user device interface 23
The transmitted cell information input to the switch via 7 is sent to the output signal line 3 if it is addressed to the own node, except in the case of broadcast information.
1-17, if the signal is addressed to another node, it is sent to the output signal line 31-1 of the channel corresponding to the destination node. In the case of broadcast information cells, multiple cells are duplicated and output to all channels. Note that since the user frame input from the branch LAN to the user equipment interface 23 via the transmission path 4 has a maximum length of approximately 4 bytes, one user frame is defined as the length of the information area 16C in FIG. 64 bytes) and transmitted as multiple pieces of cell information. FIG. 10 shows one embodiment of the switch unit 20 in which the user equipment interface consists of an asynchronous port 23A that handles wait time information. The demultiplexing unit 22 separates the received time division multiplexed frame 10
The received frame is divided into 16 5ONET frames based on the frame synchronization signal. Further, the separation unit 22 includes each 5ONET near L/
(7) The SOHOH unit outputs the information of the VC-4 area 11 to the signal lines 30-1 to 30-16 in synchronization with the basic clock 37 generated from the received frame. During the output period of each cell information, if the validity indicating bit of the cell concerned is "1", write enable signals 36-1 to 36
-16 becomes II 171. The switch unit 20 connects the signal lines 3o-1 to 30-
It has 16 elastic buffer memories 32-1 to 32-16 corresponding to 16, and each elastic buffer receives a write enable signal 36-1 to 36-16.
takes in input data from the signal lines 30-1 to 30-16 in synchronization with the basic clock 37 during the I'IIT period. Each elastic buffer has a data storage capacity of several pytres and ten bytes, and discards input data if the data overflows. The switch unit 20 includes elastic buffers 32-1 to 32-1.
Cell access control receives cell information from 6 via signal lines 40-1 to 40-16, inserts cell (slot) information from asynchronous port 23A, and branches cell information to asynchronous port 23A. 33 and an AU- section provided corresponding to each output signal line 31-1 to 31-16.
It has four component circuits 34-1 to 34-16. Reading data from each elastic buffer 32-1 to 32-16 is performed by a pulse generator 35.
The read permission signals 39-1 to 39-16 output from the AU-4 component circuits 34-1 to 34-16 are synchronized with the basic clock (155,52 MHz±320 ppm) 38 generated from the Each AU-4 component circuit is for generating a 5ONET frame consisting of an SOH area 12 and a VC-4 area 13, and an overhead area (SOH and P
OH) and the read permission signal 1117 during a time period corresponding to a predetermined number of cell areas 15 excluding the invalid area 19.
Set it to 1. The cell access control unit 33 stores cell information A"-J read from each elastic buffer 32-1 to 32-16.
Checks the area 16A and header area 16B, branches the cell information addressed to the own node to the asynchronous port 23A, and
Delete cell information generated by the own node. Also,
Transmission cell information input from the asynchronous port 23A via the signal line 30-17 is inserted into the empty cell area of the channel corresponding to the destination node. Signal lines 40-1 to 40-16 except for cell information to be erased generated from the own node.
The cell information inputted from the AU-4 is supplied to the AU-4 constituent circuits via corresponding output signal lines 41-1 to 41-16, respectively. If there is no valid cell information in the elastic buffer 32, empty cell information is output to the signal line 41. Each AU-4tJ forming circuit 34-1 to 34-16 receives cell information inputted from the signal lines 41-1 to 41-16 by 5ON.
It is inserted into the cell area 15 of the ET frame and output to the multiplexer 24. If the user equipment interface of each node 1A to ID consists of only asynchronous ports, stuffing operation using the AU pointer is not necessary, and the AU
The -4 component circuits 34-1 to 34-16 may always insert cell information corresponding to the first slot of each container into the first cell area of each 5ONET frame. FIG. 11 is a detailed diagram of the cell access control section 33. The cell access control section has channel units 50-1 to 50-16 corresponding to each channel. The channel unit 50-1 includes a reception register 60 for temporarily storing cell information input from the elastic buffer 32-1 via the signal line 40-1;
It includes an address register 61 that stores an address assigned to the asynchronous port 54 and a determination circuit 62. The determination circuit 62 determines, based on the ACF section and hesider section of the received cell input to the reception register 60 and the contents of the address register 61, (1) a signal a indicating permission for cell information transfer associated with empty cell reception; (2) reception instruction signal b indicating that a cell addressed to the own node connection port has been received, and (3)
A cell erasure (slot release) instruction signal C2 is generated in response to cell reception generated from the own node connection port. The signal S is given to the reception control circuit 63, and when the signal S indicates reception of a cell addressed to the port 54, the reception control circuit 63 takes in the cell information output from the reception register 60 into the buffer 51. Signals a and b are applied to a transmission selection circuit 64. The transmission selection circuit selects the cell information (slot information) j output from the cell buffer 65 in the following cases, and in other cases selects the output of the reception register 60 and connects the output line 41- (1) Cell information transmission request signal j of the transmission cell buffer 65
(2) When the conditional continuous use permission mode is set in advance by the signal 66 from the parameter setter 26, the signal C becomes When the cell is erased and the release indication bit 17L is "0", that is, there is no node on the ring requesting release of the access right, and (3) the continuous use permission mode is set in advance by the signal 66. If set. The transmitting cell buffer 765 is connected to the buffer control circuit 53 through signal lines d and e, and is connected to the asynchronous port 2 through the data line.
Connected to 3A. If there is cell information to be transmitted, the synchronous port 23A1 sends a write request signal g, an output channel designation signal Q, and a signal f indicating whether or not the above cell information should be broadcasted to the buffer control circuit 53. . The output channel can be specified by referring to an address table that predefines the correspondence between destination addresses and channel numbers to which destination ports are connected. The buffer control circuit 53 is. Send the specified channel (if the write ready signal e is output from the cell buffer 65, give the write ready signal l to the port 23A), and give the write enable signal d to the specified buffer.port 23A. The transmitting cell buffer 65 confirms the ready signal and outputs the cell information 16 to be transmitted to the data line 1. It is preferable to consist of a first-in first-out buffer that is divided into a first memory area that can store broadcast cells and a second memory area that can store only broadcast cells. If a dedicated second memory area is prepared, broadcast cells can be written into the transmission buffer even when the first memory area is full, so it is possible to prevent subsequent cells from being stopped due to the broadcast cell not being able to be sent. The received cell destined for the asynchronous port 23A is taken into the buffer 51, and then sent to the port 23A via the selector 52.
is input. FIG. 12 shows a second embodiment of node 1. In this embodiment, the node 1 is provided with an asynchronous port 23A and a synchronous port 23B as user equipment interfaces, and a dedicated channel (signal line 3 in this example) is provided for the synchronous port.
The first channel (including channels o-1 and 31-1) is assigned. The synchronization boat 23B is for handling circuit switching information in which transmitting/receiving ports can be identified by their positions on the container, and transfers information in synchronization with 125 μsec. FIG. 13 shows one embodiment of the switch unit 2o corresponding to FIG. 12 above. In the figure, 2OA is an asynchronous cell processing unit that performs cell exchange between the second channel to the 16th channel, and has the same configuration as that in FIG. 8. 20B is a synchronous information processing unit for exchanging information between the seventh channel and the synchronous boat 23B in synchronization with the data reception speed from the first channel. The synchronization information processing unit 20B receives the control information extraction circuit 51 which receives the 5ONET frame signal 30-1 of the first channel supplied from the separation circuit 22, and inputs the signal through the extraction circuit 51 and the signal line 60. an elastic buffer memory 52 for storing cell information to be processed; an AU pointer input from the extraction circuit 51 via a signal line 61;
It also has a destuff control circuit 53 which receives a signal indicating the start position of the VC-4 area 11 and controls data reading from the elastic buffer 52. The destuff control circuit 53 provides an 8 KHz clock synchronized with the start position of the VC-4 region to the PLL circuit 54 as a synchronization pull-in signal. The PLL circuit 54 generates a clock CLI of 149 and 76 MHz on the signal line 62 based on the clock signal. Clock C above
LI transfers the data (260 x 9 x 8 bits) of the cell transfer area 15 shown in FIG. 3(B) at one frame period of 125 μ
This corresponds to the time per bit for reading in seconds. The cell information input to the elastic buffer 52 is sent bit by bit to the synchronous port 23 using the clock CLI.
B. The synchronous port 23B receives the clock CLI and the 8KH signal from the signal line 62 obtained by dividing the clock CLI by the counter 55.
Based on the frame synchronization signal of z and the signal indicating the first byte of the frame given from the destuffing control circuit 53,
Inserts and branches information in byte units on the container at the location assigned to its own boat. Cell information and container head information output from the synchronous boat to the signal line 64 are written to the elastic buffer memory 56, read out by the stuff control circuit 58, and sent to the AU-4.
The signal is input to the control circuit 57. The AU-4 control circuit 57 sends out the received container shapes at continuous timing. On the other hand, the AU-4 control circuit 57 of the parent node
Using the 8 KHz cycle generated by the counter 62-1 from the external clock 62 with which the 3B is synchronized, a container is generated and sent. The stuff control circuit 58 connects the AU-4 configuration circuits 57 to 5.
It receives a signal indicating the starting position of a dummy area (stuffing area) in each POH area of the ONET frame, and provides a cell information read enable signal 65 at a timing corresponding to the amount of data stored in the elastic buffer 56. . The stuff control circuit 58 controls the buffer 5
If there is a large amount of data stored in the buffer 56, by starting writing cell information from the stuffing area, the number of data output from the buffer 56 can be increased, thereby keeping the amount of data in the buffer constant on average. Adjust the data transmission speed so that FIG. 14 shows a third embodiment of node 1. In this embodiment, the switch unit 2o branches cell information from any one of the input channels 30-1 to 30-16 to the asynchronous port 23A and the synchronous port 23B. 31-1~
31-16 so that cell information can be transferred to the terminals 31-16. FIG. 15 is a block diagram showing the configuration of the switch unit 20 in the third embodiment. Both the asynchronous boat 23A and the synchronous port 1-23B are
It is connected to the cell access control circuit 33. Separation circuit 22
The cell information of each channel outputted to the signal lines 30-1 to 30-16 is inputted to the cell access control circuit 33 via the receiving units 70-1 to 70-16. For example, as shown in FIG. 16, each receiving unit 70 includes an extraction circuit 510 similar to the input stage of the synchronization processing section 20B previously explained in FIG. The configuration includes a memory 520, a stuff control circuit 530, a PLL circuit 540, and a frequency division counter 550. An 8 KHz and 149.76 MHz clock output from one of the 16 receiving units 70-1 to 70-16 is applied to the synchronization port 23B. The output of the cell access control circuit 33 is sent to the transmitting unit 71
-1 to 71-16, it is input to the multiplexer 24. For example, as shown in FIG. 17, the transmission unit 71 includes an elastic buffer memory 560 similar to the latter stage of the synchronization processing section 20B previously described in FIG.
A U-4 configuration port g570 and staff control circuit 58
It has a configuration consisting of 0. In FIG. 15, the parent node uses an 8 KHz signal created by frequency-dividing the external pull-in clock 72 as the container generation timing signal 75, while the child node uses the head information 76 of the received container. Therefore, the parent node can send the container independently of the sending timing of the 5ONET frame to be sent.
It is not necessary to adjust yA using a buffer so that the intra-ring delay is an integral multiple of 125 μsec. FIG. 18 shows the configuration of the cell access control circuit 33 in the above embodiment. In this example, two ports 23A and 2
In order to branch data to 3B, a reception control circuit 63B for the synchronization port 23B, a buffer 51B, and a selector 52B are added to the circuit configuration shown in FIG. Address register 61 contains ports 23A and 2.
3B address is stored, and the determination circuit 62 outputs a signal b1 if the received cell is addressed to an asynchronous port, and outputs a signal b2 if the received cell is addressed to a synchronous port. The buffer control circuit 53 is connected to the two ports 23A and 23B using control signals Q1 to h2, respectively.
Transmission cell information from each port is selectively written to the transmission cell buffer 65 of the channel designated by signal Q1 or Q2 via data line k. Figure 19 shows the state transition of slots in the container 20 described in Figure 5, which are written and transmitted in a 5ONET frame. 1 in free or unused state 100
When the sending node acquires one slot, it enters the busy state 110. When the slot in the used state goes around the ring transmission path 2 and is released at the transmitting node, it returns to the unused state 100. When any node issues a release request for a slot in the in-use state 110, the slot enters a release waiting state 120, and when the slot is released by the transmitting node, the slot changes to an unused state 100. FIG. 20 shows the state transition of nodes. When a node in an idle state 130 receives an information transfer request from the user equipment interface 23, it enters a transmission wait state 140 and waits for access rights to an empty slot to be obtained. When an unused slot is received (access right is acquired), the state becomes transmitting 150 and the information is transferred.
When this is finished. Return to idle state 130. When the slot containing the U transmitted by the node returns after going around the transmission path, the node enters a release determination state 160 and determines whether or not the slot needs to be released. If the above slot contains a bit (17L in Figure 6) indicating a release request set by another node, or if there is no information to be transmitted, the L slot is released, that is, it is set as an empty slot. , enters the idle state 130. If the release request is not made and there is still more information to be transmitted, the process returns to the transmitting state 150 to reuse the slot. FIG. 21 shows another embodiment of the switch unit 20. In this example, four ports 23E to 23H are provided,
Each port has a dedicated input channel 30-1 to 30-3.
0-4, so that the transmitted cell information from each port can be selectively output to any output channel 31-1 to 31-16. In this way, when cell information is received only from a specific input channel for one port, for example, the buffers 51A and 51B in FIG.
By omitting the selectors 52A and 52B, the configuration can be simplified. FIG. 22 shows an example of another format of the cell 16. This cell consists of a 4-byte header section 16B and a 32-byte information section 16C.
Consisting of The information section 16C consists of a division number area 16C and a user information area 16C2.
C processing consists of 2 bits indicating whether the cell (slot) corresponds to the beginning, middle, or end of a user frame divided into multiple slots, and 6 bits indicating the length of effective information in the slot. Become. When sending call setup information out-of-band. Call setting information 400 is set in the user information area 16C2. The call setting information 400 includes an identifier 401 indicating the protocol type, a target call number 402 for setting or canceling a call, a message type 404, and additional information 4.
05 and FC3406. Additional information 405 above
For example, it consists of an information element identifier 407, an information element length 408, and an information content-409. At the time of data transfer, the call number assigned by the call setting is set in the area 16B□, and information for detecting errors in the call number, information indicating the priority level, etc. are set in the control information area 16B2. As is clear with reference to FIG.
0 receives fixed length cells from a plurality of input signal lines 30-1 to 30-17, and sends them to output signal lines 31-1, 31-17 according to the destination address or call number of each cell.
It is selectively outputting to one of the following. Therefore, the switch unit is equipped with a known ATM (Asynchronous Transfer) function that has a fixed length cell switching function.
r Mode) switch can be applied. FIG. 23 shows the basic configuration of a switch unit 20 having an ATM switch structure. A plurality of cells (FIG. 24A) supplied in parallel from input signal lines 3o-1 to 30-17 are separated into a header part 16G and an information part 16B by a multiplexing circuit 201, and an information part 16c is separated by a delay circuit. 202, gate 203, 204
to the data input terminal of the buffer memory 203 via
Further, the header section 16B is input to each read address terminal of the relay table (header conversion table) memory 206. The relay table memory 206 stores the following information in the address corresponding to the header section 16B, as shown in FIG. 24B.
and information 161 indicating whether or not it is in use. A record consisting of an output line number 162, a priority level 163, and a new header 164 is stored. Of the data read from the relay table 206, the new header 164 and usage information 161 are combined with the information portion 16C output from the multiplexing circuit 201 by the gate 203. At this time, the write permission signal is sent via the gate 207 to
The output line number 162 is applied to the write enable terminal WE of the buffer memory, and the output line number 162 is applied to the address pointer unit 2.
It is input to the destination outgoing line number (DES) terminal of 08. If the cell supplied from the multiplexing circuit 201 is an empty cell, the write enable signal is not output. In addition, write permission signal 4 friends, empty address F I F O (First in
(Firststout) is input to the buffer memory 205 only if there is an empty address in the memory 209. The address pointer unit 208 stores a new header section 164, an information section 16G, and a next address 165 in an empty area of the buffer memory 205, as shown in FIG. 24C.
The buffer memory 2 generates a write address (WAD) for writing a cell record consisting of
Address of cell record to be read from 05 (RDA
). The above write address (WAD) is an empty address FIFO 20 that stores empty addresses in the common buffer memory.
9 and manually input to the primary write address (NWAD) terminal is used. The next write address read from the FIF○ 209 is combined with the cell information at the gate 204, thereby
@'c A record having the format shown in the figure is input to the buffer memory 205. The address pointer unit 208 has an outgoing line number (DES
) has a built-in memory that stores the read address (RDA) corresponding to the buffer.
Read addresses (RA) are given to the memory 205 one after another. Of the data records read from the buffer memory 205, the header section 164 and the information section 16C are input to a demultiplexer 210,
Output to signal lines 31-1 to 31-17, next address 1
65 is input to the address pointer unit 208 as the next read address (NRAD) and stored in the address memory. In addition, the read address (RDA) output from the address pointer unit 208
is input into empty address FIFO 209 for use in writing subsequently received cell records. The switch operation described above is based on the premise that a known ATM switch is applied. However, the switch
In the unit 20, the call number used in the new header 164 is
It may be the same as the call number in the header 16B of the received cell. [Effects of the Invention] As is clear from the above description, according to the present invention, when cells are transmitted to the ring with the lowest traffic, the transmission efficiency can be improved, and the destination node When controlling to transmit to a specific ring corresponding to , the maximum reception speed can be limited to 1 ring speed. In addition, by equipping the switch or cell access control unit with a reception judgment function compatible with user equipment, the amount of cell reception buffers and input/output control circuits are each reduced to 1/(number of ring multiplexing) compared to conventional systems. can. According to the present invention, since the relay delay at the parent node can be improved, for example, when the ring length is lkm and the number of connected nodes is 10 nodes, the intra-node delay of the present invention is about 1 μsec, which reduces the ring round delay from the conventional 125 μsec. 15 μsec, about 1/8
It can be shortened to

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram showing an example of a network system according to the present invention, FIG. 2 is an explanatory diagram of time division multiplexed frames flowing through transmission path 2, and FIGS. 3 (A) and (B)
is a diagram for explaining the 5ONET frame, FIG. 4 is a diagram showing an example of the structure of a cell carried by the 5ONET frame, and FIG. 5 is a diagram for explaining the relationship between the 5ONET frame and the container. , FIG. 6 is a diagram showing another example of the cell structure, FIG. 7 is a diagram showing another example of cell arrangement in a 5ONET frame, and FIG. 8 is a diagram showing the basic configuration of nodes constituting the upper LAN. FIG. 9 is a functional explanatory diagram showing the first embodiment of the switch unit 2o, and FIG.
A diagram showing an example of a specific configuration of the switch unit 20, FIG. 11 is a detailed diagram of the cell access control circuit 33 in FIG. 10, and FIG. 12 is a diagram showing a second implementation of the switch unit 2o. FIG. 13 is a diagram showing an example of a specific configuration of the switch unit of the second embodiment. FIG. 14 is a functional diagram showing a third embodiment of the switch unit 20. 15 is a diagram showing one example of a specific configuration of the switch unit of the third embodiment, FIG. 16 is a detailed diagram of the receiving unit 60 in FIG. 15, and FIG. 17 is a diagram showing an example of a specific configuration of the switch unit of the third embodiment. 15 is a detailed diagram of the transmitting unit 61, FIG. 18 is a detailed diagram of the cell access control circuit 33 in FIG. 15, FIG. 19 is a state transition diagram of slots in the container 20, and FIG. State transition diagram, No. 21
The figure shows a fourth embodiment of the switch unit 20 (a functional explanatory diagram; FIG. 22 is a diagram showing another example of the cell structure;
Figure 23 is. This is the format of the data record. Explanation of symbols 1: Connection note between upper LAN and lower LAN,
20C1-1st LAN, 301-202/7th LAN,
11...5ONET frame, 20...switch
Unit, 21... Optical/electrical converter, 22... Separation section, 23... User bag tube interface, 24... Multiplexing section, 25... Electrical/optical converter. 3rd F (A) ￥4 figure/l Kaya, S figure 111-/2j SμΣEc----→Fig. 2 ♀ヲ figure Kaya C figure ¥7 Chill? Fixed ￥lC figure f/ρ ￥I7 figure 41 搏CB, R) = [/, 7 ) Fig. 2θ Fig. 21

Claims (1)

[Claims] 1. In a high-speed ring LAN system comprising at least one ring transmission path and a plurality of node devices interconnected by the ring transmission path, each of the node devices is connected to a lower network or a user device. at least one interface means for accommodating the above, and n channels (n is an even number) for transmitting communication frames each including a plurality of uniform length packet areas at a signal transmission rate of 155.52 Mbps on the transmission path. means for forming;
A high-speed ring LAN system comprising means for exchanging uniform length packets between each of the communication frames and the interface means. 2. The packet switching means is associated in advance with the interface means and a transmission means for inserting the outgoing packet received from the interface means into a communication frame on a channel selected corresponding to the destination of the packet. 2. The high-speed ring LAN according to claim 1, further comprising receiving means for extracting packets destined for the interface means from received frames flowing through a specific channel, and supplying the extracted packets to the interface means. system. 3. The packet switching means connects the in. transmitting means for inserting the sending packet received from the interface means into a communication frame flowing through any of the plurality of channels;
2. The high-speed ring LAN according to claim 1, further comprising receiving means for extracting packets destined for the interface means from each communication frame on the plurality of channels and supplying the packets to the interface means. system. 4. The interface means receives a received message from a lower level network connected to it, and includes a control information field for accessing a packet area in the communication frame, a header field containing packet destination information, and a header field of the received message. a user information field including a part of the packet, and the switching means refers to the control information field and the header field of the packet area included in each received communication frame. 2. The high-speed ring LA according to claim 1, wherein the high-speed ring LA performs a packet exchange operation by
N system. 5. The communication frame is SONET (Synchronous Optical NET).
2. The high-speed ring LAN system according to claim 1, wherein the high-speed ring LAN system has a format according to a transmission method. 6. High-speed LA where multiple nodes are connected in a ring, and each node has both packet switching and circuit switching functions.
In the N system, a high-speed LA is characterized in that transmission processing and packet switching processing in transmission between nodes are operated by a transmission clock within the own node, and reception processing and line switching processing are operated by a clock extracted from a received signal.
N system. 7. In a high-speed ring LAN system that transmits and exchanges fixed-length packets (hereinafter referred to as cells), each node buffers cells and generates frames at its own timing, A high-speed LAN system characterized in that cells transmitted using the information transfer area of the frame are transmitted. 8. One parent node and multiple child nodes are connected in a ring, and the parent node transmits a frame having an information transfer area divided into multiple identification areas, so that the ring circulation delay is an integral multiple of the frame sending time. In a high-speed ring LAN system in which received information is generated at a timing such that A high-speed LAN system that is characterized by first-in, first-out transmission regardless of location. 9. A LAN node that is interconnected by a ring-shaped transmission path, and has M switch input/outputs connected to M transmission paths (M is an integer), and is connected to a lower LAN or user equipment (N- M) A LAN node characterized by having (number of inputs)×(number of outputs) N×N switches consisting of (N is an integer, N>M) switch inputs and outputs. 10. LAN nodes interconnected by a ring-shaped transmission path, where (number of inputs) x (number of outputs) is N x N (N is an integer)
switch, and L×M and M×L (M and L are integers, L<M
A LAN node comprising <N) transfer information multiplexing/demultiplexing units, and having (NM) switch input/outputs connected to a lower LAN or user equipment. 11. In LAN nodes interconnected by ring-shaped transmission lines, M internal transmission lines or L×M and M×
M×M (M is an integer) input/output connected to L internal transmission lines via L (M, L is an integer, L<M<N) transfer information multiplexing/demultiplexing unit, and the M inputs. A LAN node characterized in that it has a cell access control unit consisting of K inputs and outputs connected to user equipments that receive data from and transmit to M outputs. 2. In the switch according to claim 9 or 10 or the cell access control unit according to claim 11, one of the inputs from the internal transmission path is connected to one of the outputs connected to the user equipment, or A LAN characterized in that information is exchanged to one of M predetermined transfer information multiplex units.
node. 3. In the switch according to claim 9 or 10, or the cell access control unit according to claim 11, the input transfer information from the user equipment is transferred to the transfer information multiplexing unit or M units connected to the transmission path. A LAN node characterized by switching outputs to the one with the lowest traffic. 4. In claim 13, when user information is divided into a plurality of transfer information and transmitted, a switch is controlled so that transfer information belonging to the same user information is output to the same output. LAN node. 15. In the switch according to claim 9 or 10, or the cell access control unit according to claim 11, the input transfer information from the user equipment is transferred to the transfer information multiplexing unit or M outputs connected to the transmission path. Among these, a LAN node is characterized in that the output is exchanged to a predetermined output corresponding to a destination node. 16. In a LAN node that has a switch or a cell access control unit that performs cell exchange and statistical multiplexing that has a call number in its header, 1 used for communication between LAN nodes connected to the same medium before transmitting transfer information. A LAN system characterized in that one or more call numbers are set and communication between nodes is performed using the call numbers. 17. In a LAN node that has a switch or cell access control unit that performs exchange and statistical multiplexing of cells that have a call number in the header, before transmitting transfer information, the output terminal of the switch connected to the user equipment or the cell access control unit Set a call number to each of the output terminals of the
A LAN system characterized in that communication is performed using the call number. 18. The LAN system according to claim 16 or 17, wherein broadcast call numbers addressed to a plurality of nodes are simultaneously assigned to each of the output terminals along with the call number. 19. Claims 9, 10 or 11
2. A LAN node according to claim 1, wherein the broadcast information is copied to M outputs, and a broadcast call number is assigned to the same before being transmitted. 20. In the switch according to claim 9 or 10, according to the priority information set in the transfer information, for transfer information that outputs the same output, the transfer information with a higher priority is replaced with the transfer information with a lower priority. The input information is given priority when the switch is input, and the output transfer information from the user device is given a lower priority than the intra-LAN transfer information, and when the switch output A LAN node characterized in that the priority information is deleted. 21. In the switch according to claim 9 or 10, according to the priority information set in the transfer information, for transfer information output to the same output, transfer information with a higher priority is replaced with information with a lower priority. A LAN characterized in that output transfer information from a user device is transmitted with a lower priority than intra-LAN transfer information, and is converted to a higher priority when transmitted from the LAN node. node. 22. In the switch according to claim 9 or 10 or the cell access control unit according to claim 11, a first area for storing individual destination cells and broadcast cells and a first area for storing broadcast cells are provided. 1. A LAN node characterized in that the LAN node is divided into two regions and has a transmission cell buffer for each output, which is controlled in a first-in first-out manner. 23. A transmission cell buffering method characterized in that cells stored in the transmission cell buffer according to claim 22 are given a user identifier indicating that the cells are generated from the same user information unit. . 24. In an access method that determines whether or not to continuously transmit cells using the empty cell transmission area after erasing cells transmitted by the own node that have circulated around the ring, based on mode information set in the node in advance, A first mode that prohibits continuous use of the own node usage area, and a second mode that allows continuous use of the own node usage area with conditions,
An access method characterized by selectively using all or two modes of the third mode that permits continuous use. 25. The second mode described in claim 24 is characterized in that the use permission condition is that the cell to be transmitted is a cell generated from the same user information unit as the cell sent immediately before. access method. 26. In a multimedia LAN that handles both packet-switched information and circuit-switched information using logical or physical multiplexed rings, a ring LAN is characterized in that rings are used separately for each type of switched information. system.