JPS63224445A - Self-routing speech path - Google Patents

Self-routing speech path

Info

Publication number
JPS63224445A
JPS63224445A JP62058000A JP5800087A JPS63224445A JP S63224445 A JPS63224445 A JP S63224445A JP 62058000 A JP62058000 A JP 62058000A JP 5800087 A JP5800087 A JP 5800087A JP S63224445 A JPS63224445 A JP S63224445A
Authority
JP
Japan
Prior art keywords
circuit
communication information
header
self
routing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62058000A
Other languages
Japanese (ja)
Inventor
Hitoshi Imagawa
今川 仁
Shigeo Urushiya
重雄 漆谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP62058000A priority Critical patent/JPS63224445A/en
Publication of JPS63224445A publication Critical patent/JPS63224445A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce a hardware quantity for the control of a speech path, by combining a circuit which performs a copying operation by using a random readout type memory circuit and a non-block self-routing speech path which selects a path. CONSTITUTION:By constituting a buffer circuit 201 of the random readout memory circuit, the data part of a bit of communication information A is read out by copying for several times, and furthermore, a header part including different differential addresses is read out from the memory 202, and by inputting the data part and the header part in a form that they are synthesized to a self-routing speech path via a transmission line 219, the bit of communication information can be copied, and is distributed with the said speech path. Since non-blocking property can be guaranteed completely in the speech path, no collision between data occurs. A control circuit 208 recognizes the arrival interval of the communication information in advance at the time of setting a call, and controls the copying operation so as to be completed within the arrival interval. In such a way, it is possible to constitute a perfect non-block type self-routing speech path large in scale and having a copying function.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は情報の交換を行う自己ルーテ/グ通話路に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to self-routing/routing channels for exchanging information.

〔従来の技術〕[Conventional technology]

第3図は従来のコピー機能を有する自己ルーチング通話
路の例でろる。詳細は、GLOBECQM B4’r 
5rhnx、zrg : A wrwBMn DIar
rAr、 5WITCH」5.5.1に記述されている
。本動作については、外国通信技術1986年8月号N
o、 117.24〜31頁、大容量回線設定端局(ハ
ブ端局)による広帯域同期網の構成、発行所社団法人電
気通信協会、編集NTT技術開発部にも記載されている
FIG. 3 is an example of a self-routing channel with a conventional copy function. For details, please refer to GLOBECQM B4'r
5rhnx, zrg: A wrwBMn DIar
rAr, 5WITCH” 5.5.1. Regarding this operation, please refer to Foreign Communication Technology August 1986 issue N.
o, pp. 117.24-31, Configuration of Broadband Synchronous Network with Large Capacity Line Setting Terminals (Hub Terminals), Published by Telecommunications Association of Japan, Edited by NTT Technology Development Department.

この構成では、ルーチングを行うルーチング網の前段に
コピー用のンーテング網とコピー網を配置し、同図に示
すようにパケットは、信号源の原本パケットと無情報の
コピーパケットとが1)、これを区別するコピービット
を持ってしる。原本パケットは目的地アドレスと信号源
アドレスを持ち、コピーパケットはコピーを希望する信
号源のアドレスを原本アドレスとしている。コピー用ソ
ーチング網は、信号源アドレスにコピービットをLSB
として付加し次数値が大きい順に並ぶようにンーチング
を行う。コピーパケットはその原本パケットと隣接する
ようにわけられコピー網へ送られる。
In this configuration, a routing network for copying and a copying network are arranged before a routing network that performs routing, and as shown in the figure, packets are divided into an original packet of the signal source and a copy packet without information (1). It has a copy bit that distinguishes it. The original packet has a destination address and a signal source address, and the copy packet has the address of the signal source to be copied as the original address. The copy sorting network sets the copy bit to the signal source address by LSB.
, and the ordering is performed so that they are arranged in descending order of order value. The copy packet is divided into adjacent packets to the original packet and sent to the copy network.

コピー網では%原本パケットに隣接したコピーパケット
に次々に内容をコピーする。
In the copy network, contents are successively copied to copy packets adjacent to the original packet.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来のコピー機能を持つ自己ルーチング通話路の構成で
は、コピーを行う九めにコピー用ンーチング網さらにコ
ピー網を必要としハード蓋が大きくなるという問題があ
った。
The conventional configuration of a self-routing communication path with a copying function has the problem that a copy tracing network and a copying network are required at the ninth stage of copying, resulting in a large hard cover.

〔問題点を解決する九めの手段〕[Ninth way to solve the problem]

本発明は、従来の問題点全解決しハード量の少ない自己
ルーチング通話路を提供することを目的とするもので、
複数の段と各段を接続する複数の伝送リンクからなシ、
各段では通信情報に付与されるヘッダにより次段へのリ
ンクを決定し、該ヘッダは入回線番号と出回線番号の差
分を含み、各段では該ヘッダに従−情報の位置の移動を
行うか、または移動せずに次段に転送する自己ルーチン
グ通話路において、前記通信情報上一時蓄積する第一の
回路と、前記ヘッダを記憶する第二の回路と、前記纂−
の回路からの出力通信情報と前記第二の回路からのヘッ
ダとを合成する第三の回路と、前記第三の回路からの出
力を前記自己ルーチング通話路へ入力し所要のルーチン
グを行った後、前記通信情報を一時蓄積する第四の回路
と、新しいヘッダを記憶する第五の回路と、前記第四の
回路からの通信情報から旧ヘッダを削除し、前記新しい
ヘッダと通信情報を合成する第六の回路とを備えてなる
ことを特徴とし、とくに前記第一の回路はランダム読み
だし形の記憶回路からなシ、同一通信情報をN回読みだ
し各情報毎に前記第二の回路に記憶された入回線番号と
出回線番号の差分の異なるN個のヘッダを読みだし、前
記第三の回路で合成することを特徴とする。
The present invention aims to solve all the conventional problems and provide a self-routing communication path with a small amount of hardware.
consisting of multiple stages and multiple transmission links connecting each stage,
At each stage, the link to the next stage is determined by the header added to the communication information, and this header includes the difference between the incoming line number and the outgoing line number, and at each stage, the position of the information is moved according to this header. Alternatively, in a self-routing communication path that transfers the communication information to the next stage without moving, a first circuit that temporarily stores the communication information, a second circuit that stores the header, and a
a third circuit for synthesizing the output communication information from the circuit and the header from the second circuit; and after inputting the output from the third circuit to the self-routing channel and performing the required routing. , a fourth circuit that temporarily stores the communication information, a fifth circuit that stores the new header, and deletes the old header from the communication information from the fourth circuit and combines the new header and the communication information. In particular, the first circuit is a memory circuit of a random readout type, reads out the same communication information N times, and sends the same communication information to the second circuit for each piece of information. The present invention is characterized in that N headers having different differences between the stored incoming line number and outgoing line number are read out and combined in the third circuit.

〔作用〕[Effect]

本発明は、ランダム読みだし形の記憶回路を使用するこ
とによってコピー動作を行9回路と方路を選択するノン
ブロック自己ルーチング通話路と組み合わせることに二
って、コピー機能をもちかつノンブロックな自己ルーチ
/グ通話路が実現できるため、従来必要としていた複雑
なコピー用ンーチング網さらにコピー網が不要となシハ
ード量を少なくした点が特徴である。以下図面にもとづ
き実施例について説明する。
The present invention provides a copy function and a non-blocking method by using a random read type storage circuit and combining the copying operation with a row 9 circuit and a non-blocking self-routing channel that selects a route. Since a self-routing/routing communication path can be realized, a feature of the present invention is that the complicated copy routing network that was conventionally required, as well as the amount of shihad that does not require a copy network, is reduced. Examples will be described below based on the drawings.

〔実施例〕〔Example〕

第1図は、本発明の実施例の全体構成を示すもので、2
01は通信情報を一時蓄積するバッファ回路(第一の回
路の一例)、202はヘッダ等を蓄積する記憶回路(第
二の回路の一例)、205は該通信゛情報と該ヘッダを
合成する回路(第三の回路の一例)、204は差分アド
レス法による自己ルーチング通話路(特許出願中 特願
昭61−285621、特開昭 −号公報)、205は
通信情報を一時蓄積する2777回路(第四の回路の一
例ン、206は新しいヘッダを一時蓄積する記憶回路(
第五の回路の一例)、207は旧ヘッダを新しいヘッダ
と入れ替える合成回路(第六の回路の一例ン、20Bは
制御回路である。210は通信情報の入力線、211は
分岐回路、212は通信情報のうちデータ部を伝達する
線、213は通信情報のうち論理チャネル番号を伝える
線、214は制御回路から差分アドレスを書き込む線、
215は書き込み制御線、216はバッファからのデー
タ読みだし制御線、217はデータ部の伝達線、218
は差分アドレス等のヘッダの伝達線、219は多重化さ
れ九通信情報を差分アドレス法による自己ルーチング回
路204へ伝達する線である。220は自己ルーチング
通話路からの通信情報の入力線、221は分岐回路、2
22は通信情報のうちデータ部の伝達線、223は通信
情報のうち論理チャネル番号を伝える8%  224は
制御回路から倉ヘッダを書き込む線、225は誓き込み
制御線、226はバッファからのデータ読みだし制御線
、227はデータ部の伝達線、228は新ヘッダの伝達
線、229は出力線である。同図の破線は増設する単位
を示したものである。
FIG. 1 shows the overall configuration of an embodiment of the present invention.
01 is a buffer circuit that temporarily stores communication information (an example of a first circuit), 202 is a storage circuit that stores headers, etc. (an example of a second circuit), and 205 is a circuit that synthesizes the communication information and the header. (an example of the third circuit), 204 is a self-routing communication path using the differential addressing method (patent pending, Japanese Patent Application No. 61-285621, Japanese Patent Application Laid-open No. 1988-1181), and 205 is a 2777 circuit for temporarily storing communication information (No. 206 is a memory circuit (206) for temporarily storing new headers.
207 is an example of a sixth circuit, 20B is a control circuit, 210 is a communication information input line, 211 is a branch circuit, 212 is a synthesis circuit that replaces the old header with a new header (an example of the fifth circuit), 207 is a synthesis circuit that replaces the old header with a new header (an example of the sixth circuit) A line for transmitting the data part of the communication information; 213 is a line for transmitting the logical channel number of the communication information; 214 is a line for writing the differential address from the control circuit;
215 is a write control line, 216 is a data read control line from the buffer, 217 is a data section transmission line, 218
219 is a line for transmitting headers such as differential addresses, and 219 is a line for transmitting multiplexed communication information to the self-routing circuit 204 using the differential addressing method. 220 is an input line for communication information from a self-routing channel; 221 is a branch circuit;
22 is a transmission line for the data part of the communication information, 223 is 8% of the communication information that conveys the logical channel number, 224 is a line for writing a header from the control circuit, 225 is a write control line, and 226 is data from the buffer. A read control line, 227 is a data section transmission line, 228 is a new header transmission line, and 229 is an output line. The broken lines in the figure indicate the units to be added.

第1図の動作を、第2図の動作例を用いて説明する。第
2図(アンは、入力線210上の通信情報A〜Dの配列
を示し、それぞれの通信情報はデータ部DA〜DDとヘ
ッダ@ HA% HDからなり、分岐回路211におい
てデータ部とヘッダ部に分離され、第2図(イ)は伝達
線212を介してバッフ、回路201へ伝えられるデー
タ部、(つ)は論理チャネル番号を伝える線213を介
して記憶回路202へ伝えられるヘッダ部である。記憶
回路202からの新しいヘッダ部をけ)のように読みだ
し、一方データ部モ(1)のタイミングで読みだすこと
によって、それぞれ217.218の伝達線を介して合
成回路203へ伝えられ、自己ルーチング通話路204
へは(力)のような配列で伝達線219t−介して伝え
られる。自己ルーチング通話路を通った後の分岐回路2
21、バッフ1回路205、記憶回路206、合成回路
207の動作も第2図の(ア)〜(力)までの動作と同
様であるので詳細な動作説明は省略する。第2図(キ〕
、(り)は本発明の特徴的な動作を示したもので、バラ
フッ回路201ヲランダム読みだし形の記憶回路で構成
することに工って、通信情報Aのデータ部を(キ〕のよ
うに複数回コピーして読みだし、さらに202から異な
る差分アドレスを含むヘッダ’t ct)のタイミング
で読みだすことに工って、し)のようにデータ部とヘッ
ダ部を合成した形で伝達線219 ’z介して自己ルー
チング通話路へ入力することによって、通信情報をコピ
ーするとともに該通話路で分配する。該通話路は、特願
昭61−285621 (特開昭 −号公報〕で詳細に
記されているように、通話路内では完全にノンブロック
性が保証されるため、データの衝突は発生しない特徴を
有している。同、通信情報の到着間隔はあらかじめ呼設
定時に制御回路208は知り、到着間隔内でコピー動作
を完了するよう制御する。
The operation of FIG. 1 will be explained using the operation example of FIG. 2. FIG. 2 (An) shows the arrangement of communication information A to D on the input line 210, each communication information consists of data parts DA to DD and a header @ HA% HD, and in the branch circuit 211, the data part and the header part FIG. 2(A) shows a data part transmitted to the buffer circuit 201 via a transmission line 212, and (1) shows a header part transmitted to the memory circuit 202 via a line 213 that conveys a logical channel number. By reading out the new header section from the storage circuit 202 as in (1) and reading out the data section at the timing of (1), the new header section is transmitted to the synthesis circuit 203 via the transmission lines 217 and 218, respectively. , self-routing channel 204
The force is transmitted through the transmission line 219t in an arrangement such as (force). Branch circuit 2 after passing through the self-routing channel
21. The operations of the buffer 1 circuit 205, the memory circuit 206, and the synthesis circuit 207 are also similar to those shown in FIG. Figure 2 (K)
, (ri) show the characteristic operation of the present invention, in which the data portion of the communication information A is written as shown in (k) by configuring the variable circuit 201 with a random readout type memory circuit. By copying and reading multiple times, and then reading from 202 at the timing of the header 't ct) that includes different differential addresses, the data section and header section are combined as shown in 202 and transferred to the transmission line 219. By entering the self-routing channel via 'z, the communication information is copied and distributed on the channel. As described in detail in Japanese Patent Application No. Sho 61-285621, this communication path is completely non-blocking, so data collisions do not occur. The control circuit 208 knows the arrival interval of communication information in advance at the time of call setup, and controls the copying operation to be completed within the arrival interval.

従って、コピー数も到着間隔お工びランダムアクセスメ
モリの読みだしサイクルとの関係できまる。
Therefore, the number of copies is also determined by the relationship between the arrival interval and the read cycle of the random access memory.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明では、差分アドレス等のヘ
ッダ変換用の記憶回路お二びデータ用の記憶回路がコピ
ー用の回路にも共用でき、従来必要としていた専用の複
雑なコピー用ソーチング網さらにコピー網が不要となり
、通話路制御のためのハード量を削減するとともに、さ
きに発明した特願昭61−285621 (特開昭 −
号公報ンの自己ルーチング通話路と組み合わせることに
よりコピー機能を有する大規模完全ノンブロックな自己
ルーチング通話路を構成できる。
As explained above, in the present invention, the storage circuit for converting headers such as differential addresses and the storage circuit for data can also be used as a copying circuit, thereby eliminating the need for a dedicated and complex sorting network for copying, which was previously required. Furthermore, a copy network is no longer required, and the amount of hardware for controlling the communication path is reduced.
By combining this method with the self-routing channel of the publication, a large-scale completely non-blocking self-routing channel with a copy function can be constructed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例の全体構成、 第2図は第1図の動作を説明するための動作図、第3図
は従来のコピー機能を有する自己ルーチング通話路の構
成例でおる。 201:通信情報を一時蓄積するバッフ7回路202:
ヘッダ等を蓄積する記憶回路 203:該通信情報と該ヘッダを合成する回路204:
差分アドレス法による自己ルーチンク通話路 205:通信情報を一時蓄積するバッファ回路206:
新しいヘッダを一時蓄積する記憶回路207:旧ヘッダ
を新しいヘッダと入れ替える合成回路 208:制御回路 210;通信情報の入力線 211;分岐回路 212;通信情報のうちデータ部を伝達する線213:
通信情報のうち論理チャネル番号を伝える線 214:制御回路から差分アドレスを書き込む線215
:書き込み制御線 216:バッフ7からのデータ読みだし制御線217:
データ部の伝達線 218:差分アドレス等のヘッダの伝達線219:多重
化された通信情報t−204へ伝達する線 220:自己ルーチング通話路からの通信情報の入力線 221:分岐回路 222:通信情報のうち”データ部の伝達線225:通
信情報のうち論理チャネル番号を伝える線 224:制御回路から新ヘッダを書き込む線225:警
き込み制御線 226:バッフ1からのデータ読みだし制御線227:
データ部の伝達線 228:新ヘッダの伝達線 229:出力線 特許出顯人 日本電信電話株式会社 代理人弁理士玉蟲久五部 (外2名ン 210:  通信情報の入力線          2
11: 分岐回路2!2 : 過信’1報のうちチー9
部き伝道する*    2+3+  通信情報のうち論
理子ヤも(1号を信える線21fll1分アドレス等の
へフグのffi這1   219・ 多重化さ酊こ通信
情報を204へ舖すみ線220、 自とルーチンヅ通話
路からOIM信情報の入力線  221  分岐口路2
22 +  通信111報の95デ一9部の信連譲  
  2z3゛ 通信111′raの)5論l←禎1号と
伝λ4瞭224:  制御回路かI)#へ7グ2書ぎ込
む線  225・ 書叩込み[11線226   バヮ
ファかうのデータ読みだし1lIrn線  227: 
データ部のイ云遭線228:  斬ヘッダの伝1腺  
        229゛ 出力線本発明の実施伊ゆ金
体aF5.図 第  1  口 従来のコピー機能を有する自己ルーチング通話路の斗育
成f列第3図
FIG. 1 shows the overall configuration of an embodiment of the present invention, FIG. 2 is an operational diagram for explaining the operation of FIG. 1, and FIG. 3 shows an example of the configuration of a conventional self-routing channel having a copy function. 201: Buffer 7 circuit that temporarily stores communication information 202:
Memory circuit 203 for storing headers etc.: Circuit 204 for synthesizing the communication information and the header:
Self-routine communication path 205 using differential addressing method: Buffer circuit 206 for temporarily storing communication information:
Memory circuit 207 for temporarily storing new headers: Synthesizing circuit 208 for replacing old headers with new headers: Control circuit 210; Input line 211 for communication information; Branch circuit 212; Line 213 for transmitting the data part of communication information:
Line 214 that conveys the logical channel number among communication information: Line 215 that writes the differential address from the control circuit
:Write control line 216:Data read control line 217 from buffer 7:
Data section transmission line 218: Header transmission line 219 for differential addresses, etc.: Line for transmitting multiplexed communication information to t-204 220: Input line 221 for communication information from self-routing communication path: Branch circuit 222: Communication Among the information, a transmission line 225 for the data section: A line for transmitting the logical channel number among the communication information 224: A line for writing a new header from the control circuit 225: An alarm control line 226: A control line for reading data from buffer 1 227 :
Data section transmission line 228: New header transmission line 229: Output line Patent author: Nippon Telegraph and Telephone Corporation Patent Attorney Gobe Tamamushi (2 others) 210: Communication information input line 2
11: Branch circuit 2! 2: Overconfidence 'chi 9 out of 1 report
* 2 + 3 + Of the communication information, the logical child also (line 21 that trusts No. 1, 1 minute address, etc.) 219, multiplexed communication information to 204, corner line 220, self Input line for OIM information from Routines communication path 221 Branch path 2
22 + Transfer of 95 de-19 copies of Tsushin 111 Report
2z3゛ Communication 111'ra's) 5 theory ← Tei No. 1 and transmission λ4 224: Control circuit I) Line 7g2 to write to # 225. Writing [11 line 226 Data read from buffer 1lIrn line 227:
Data section Ien encounter line 228: Zan header Den 1 gland
229゛ Output line Implementation of the present invention metal body aF5. Figure 1. Self-routing channel with conventional copy function. Figure 3.

Claims (2)

【特許請求の範囲】[Claims] (1)複数の段と各段を接続する複数の伝送リンクから
なり、各段では通信情報に付与されるヘッダにより次段
へのリンクを決定し、該ヘッダは入回線番号と出回線番
号の差分を含み、各段では該ヘッダに従い情報の位置の
移動を行うか、または移動せずに次段に転送する自己ル
ーチング通話路において、 前記通信情報を一時蓄積する第一の回路と、前記ヘッダ
を記憶する第二の回路と、 前記第一の回路からの出力通信情報と前記第二の回路か
らのヘッダとを合成する第三の回路と、前記第三の回路
からの出力を前記自己ルーチング通話路へ入力し所要の
ルーチングを行った後、前記通信情報を一時蓄積する第
一の回路と、新しいヘッダを記憶する第五の回路と、 前記第四の回路からの通信情報から旧ヘッダを削除し、
前記新しいヘッダと通信情報を合成する第六の回路とを
備えてなる ことを特徴とする自己ルーチング通話路。
(1) Consisting of multiple stages and multiple transmission links connecting each stage, each stage determines the link to the next stage based on the header added to the communication information, and the header contains the incoming line number and outgoing line number. In a self-routing communication path that includes a difference, and in each stage moves the position of the information according to the header, or transfers the information to the next stage without moving, a first circuit that temporarily stores the communication information, and a first circuit that temporarily stores the communication information; a second circuit for storing the output communication information from the first circuit and a header from the second circuit; and a third circuit for combining the output communication information from the first circuit with the header from the second circuit; After inputting to the communication path and performing necessary routing, the first circuit temporarily stores the communication information, the fifth circuit stores the new header, and the old header is retrieved from the communication information from the fourth circuit. Delete and
A self-routing channel comprising: a sixth circuit for synthesizing the new header and communication information.
(2)前記第一の回路はランダム読みだし形の記憶回路
からなり、同一通信情報をN回読みだし各情報毎に前記
第二の回路に記憶された入回線番号と出回線番号の差分
の異なるN個のヘッダを読みだし、前記第三の回路で合
成することを特徴とする特許請求の範囲第1項記載の自
己ルーチング通話路。
(2) The first circuit consists of a random readout type memory circuit, reads the same communication information N times, and calculates the difference between the incoming line number and the outgoing line number stored in the second circuit for each piece of information. 2. A self-routing telephone line as claimed in claim 1, wherein N different headers are read and synthesized by said third circuit.
JP62058000A 1987-03-13 1987-03-13 Self-routing speech path Pending JPS63224445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62058000A JPS63224445A (en) 1987-03-13 1987-03-13 Self-routing speech path

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62058000A JPS63224445A (en) 1987-03-13 1987-03-13 Self-routing speech path

Publications (1)

Publication Number Publication Date
JPS63224445A true JPS63224445A (en) 1988-09-19

Family

ID=13071725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62058000A Pending JPS63224445A (en) 1987-03-13 1987-03-13 Self-routing speech path

Country Status (1)

Country Link
JP (1) JPS63224445A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02161851A (en) * 1988-12-14 1990-06-21 Fujitsu Ltd Atm exchange system
WO1992014321A1 (en) * 1991-01-31 1992-08-20 Fujitsu Limited Connectionless communication system
JPH0537546A (en) * 1990-07-31 1993-02-12 Nec Corp Cross connect communication equipnent for asynchronous transfer mode
JPH0851443A (en) * 1995-05-24 1996-02-20 Nippon Telegr & Teleph Corp <Ntt> Atm exchange device
US5809012A (en) * 1991-01-31 1998-09-15 Fujitsu Limited Connectionless communication system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02161851A (en) * 1988-12-14 1990-06-21 Fujitsu Ltd Atm exchange system
JPH0537546A (en) * 1990-07-31 1993-02-12 Nec Corp Cross connect communication equipnent for asynchronous transfer mode
WO1992014321A1 (en) * 1991-01-31 1992-08-20 Fujitsu Limited Connectionless communication system
US5689501A (en) * 1991-01-31 1997-11-18 Fujitsu Limited Connectionless communication system
US5809012A (en) * 1991-01-31 1998-09-15 Fujitsu Limited Connectionless communication system
JPH0851443A (en) * 1995-05-24 1996-02-20 Nippon Telegr & Teleph Corp <Ntt> Atm exchange device

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