JPH01231452A - Frame relay type data exchange - Google Patents

Abstract

PURPOSE:To reduce the number of times of memory access and to attain high speed processing by synthesizing an output logic channel number outputted from a temporary storage circuit and a communication data part outputted from a communication data buffer and outputting the result as a logic channel data. CONSTITUTION:A logic channel number form an output communication channel corresponding to the logic channel number of an input communication channel from a processor 90 is stored in an area of a memory 500. Thus, when the logic channel number coincident with a heater part being a collated data for an associate memory 400 while being separated by an input controller 10 is registered in the associate memory 400, an address control output of a corresponding to address is made active, and the logic channel number (revised header part) stored in the same address of a temporary storage circuit 500 is outputted and given to an output controller 30. The output controller 300 reads out communication data stored tentatively from a communication data buffer and outputs them to an output communication channel while synthesizing them. Thus, the memory access number of times is reduced and the processing is quickened.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a packet switch in a data switching network,
In particular, the present invention relates to a frame relay type data exchange for implementing frame relay services in an integrated services digital network (ISDN).

[Conventional technology]

In frame relay in 15DN, only header updates based on logical line numbers are performed within the network, and all processing related to data retransmission due to detection of data transfer errors etc. is performed end-to-end. 5DN PACK
ET 5ERVICES EVO-LUTION'
Mehmet Unsoy, IEEE 1987.
A4.4.1-A4.4.5).

3.1-47.3.5 'High 5peed Pa
cket Switching Protocol”.

This data exchange has a table on the software that shows the correspondence between input logical line numbers and output logical line numbers,
When it is detected that data has been input from the input communication line, the data is stored in memory, the corresponding output logical line number is found by looking up the software table from the header of this data, and the data is processed based on this. The header part of the data was updated and the data was sent to the output communication line.

[Problem to be solved by the invention]

However, in such a conventional data switch, since the correspondence between the input logical line number and the output logical line number is stored in the software table, the number of memory accesses required for header update processing increases. Furthermore, since this processing is performed by the processor, in order to achieve high-speed processing, not only the line support parts such as buffers, but also the
There is a drawback that it is necessary to increase the access to the memory storing the software table and the processing speed of the processor itself.

[Means to solve the problem]

The data exchanger of the present invention includes an input control device that inputs logical line data on an input communication line and separates it into a header part and a communication data part, and collates this header part with a pre-registered input logical line number. An associative memory that outputs an address control signal corresponding to the address where the matched input logical line number is stored, and outputs a pre-registered output logical line number corresponding to the matched input logical line number based on this address control signal. a temporary storage circuit for temporarily storing the communication data portion, a communication data buffer for temporarily storing the communication data portion, and a logical line by combining the output logical line number output from the temporary storage circuit and the communication data portion output from the communication data buffer. and an output control device that outputs data onto an output communication line.

〔Example〕

Referring to FIG. 1, a data exchange according to an embodiment of the present invention includes a processor 90 and a data exchange section 100 connected to the processor 90.

The data exchange unit 100 has an input terminal 1 for inputting logical line data on an input communication line (not shown), and an input terminal for inputting the logical line data from this input terminal 1 and separating it into a header part and a communication data part. From the control device 10, the header section exchange circuit 40, the communication data buffer 20 for temporarily storing the separated communication data section, and the header section conversion circuit 40, which updates the separated header section. an output control device 30 that combines an output logical line number to be output and a communication data section output from the communication data buffer 20 and outputs the result as logical line data; and this output control device 3
0 and an output terminal 2 for inputting the logical line data and outputting it onto an output communication line (not shown).

A more detailed explanation will be given below with reference to FIGS. 1 and 2.

The header section conversion circuit 40 includes an associative memory 400 that compares the header section with a pre-registered input logical line number and outputs an address control signal corresponding to the address where the matched input logical line number is stored; a temporary storage circuit 500 that outputs a pre-registered output logical line number corresponding to the matched input logical line number based on the address control signal; and a temporary storage circuit 500 that inputs the input logical line number from the processor 90 and provides it to the associative memory 400; An input logical line number address is inputted and given to the associative memory 400 via the address decoder 600, an output logical line number is inputted from the processor 90 and given to the temporary storage circuit 500, an output logical line number address is inputted and given to the address decoder 700. and a processor interface 800 for providing data to the temporary storage circuit 500 via the processor interface 800 .

The input control device 10 includes a serial-to-parallel conversion circuit 11, a counter 12 . First register 13 and second register 14
It is equipped with DAT of input terminal l of input control device 10
Logic circuit data is serially input to the terminal SD of the serial/parallel conversion circuit 11 via the A terminal. Note that the input terminal 1
Although it is equipped with DATA, CLOCK, and TIMING input terminals, the extraction of the clock from the serial data on the transmission path is a matter of the transmission system and is not directly related to the present invention, so a description thereof will be omitted.

The input to the input terminal 1 consists of a header section H and a communication data section, as shown in FIG. 2, and the start and end of a frame can be detected by a flag pattern.

Here, for the sake of simplicity, it is assumed that the length of the frame is fixed, and by detecting only the start of the frame, all the timing necessary for this data exchanger can be obtained.

Therefore, the relationship between data, clock, and timing signals at input terminal 1 is as shown in FIG.

Logic circuit data as shown in FIG. 2 is serially inputted to the terminal SD of the serial/parallel conversion circuit 11 via the input terminal 1 of the input control device 10. This serial/parallel conversion circuit 11 converts data into parallel data in units of octets (8 bits) and outputs the parallel data from a terminal PD. The data output from the serial/parallel conversion circuit 11 is sent to the first and second registers 13 and 14.
is supplied to The first register 13 is the controller 12
A header section H having a length of one octet is stored in response to a control signal T2 from the controller. Similarly, the second register 14 stores the communication data portion in units of octets in accordance with the control signal T1 from the controller 12.

Note that when the controller 12 receives a timing signal at the terminal R, it is reset, and the control signals TI, T2°Wl and W
Start creating 2. Of the logical line data separated by the input control device 10, the header part H is output from the first register 13 to the output 103 and is sent to the header part conversion circuit 4.
0 is supplied to the input 403 of the associative memory 400. Also, the communication data part is output from the second register 14 at 102.
is supplied to the communication data buffer 20 via. The communication data buffer 20 is comprised of a first-in-first-out (FIFO) memory 21. This F
The IFO memory 21 receives the control signal W1 from the controller 12 at the terminal WR, and stores the communication data portion input to the terminal WD via the input 201 in accordance with the clock signal C.

The associative memory 400 receives the header part to be collated from the input control device 10 via an input 403, and also receives a data input/output terminal 801 of the processor interface 800 via an input 404 and an address output terminal via the address decoder 600. 802 , and the contents are read and written under control from the processor 900 .

Both the associative memory 400 and the temporary storage circuit 500 have the same number of addresses (four addresses in the example shown in FIG. 1), and store data corresponding to the header portion corresponding to each of the four seven addresses. .

In the case of the associative memory 400, the address control input (
For example, 401) and an address control output (for example, 402) that is output when matching the verification data. The address control output of the associative memory 400 (for example, 4
02) are each connected to a cell at the same address of the temporary storage circuit 500 as an address control input (for example, 501). In the temporary storage circuit 500, an associative memory 400 and an address decoder 7 are provided for each address.
Address control signal input supplied from 00 (e.g. 5
01 and 502), and cycles can be accessed from either using the same method.

Further, the temporary storage circuit 500 can be accessed from the processor interface 800 similarly to the associative memory 400. Further, the temporary memory circuit 500 is an associative memory 4
When an address control input from 00 (for example, 501) is received, the data (updated header section) stored at the corresponding address is output to data output 503.

The output control device 30 has a third register 31 . Fourth register 32. Selector 33. It includes a parallel-to-serial conversion circuit 34 and a controller 35.

The control signal R2 from the controller 35 is sent to the temporary storage circuit 5.
When supplied to the terminal 503 of 00, the converted header section H is read from the corresponding area of the temporary storage circuit 500 and output to the fourth register. Also, the above-mentioned FIF
The controller 350 control signal R1 is connected to the terminal RR.
The received and accumulated communication data part is read out from the terminal RD and supplied to the third register 31. third register 3
1 stores this communication data part. After that, the controller 35 supplies the selection signal S to the selector 33 to switch between the header part H from the fourth register 32 and the communication data part from the third register 31, and converts the logical line data as shown in FIG. It is output to the parallel-to-serial conversion circuit 34 so that The parallel/serial conversion circuit 34 converts the header section H and the communication data section input in parallel from the selector 33 into serial data and outputs the converted data to the output terminal 2.

Next, the correspondence between the input logical line number of the associative memory and the output logical line number of the temporary storage circuit of the data exchanger of the present invention will be explained with reference to FIG. In the same figure, A is an address,
Nl indicates the logical line number of the input communication line, and N2 indicates the logical line number of the output communication line corresponding to the input communication line.

In FIG. 1, this logical line data is input to the input control device 1.
When input to 0, the header section H and the communication data section are separated, and the header section 11 is treated as verification data in the associative memory 400. At this time, the processor 90 stores in the associative memory 400 the logical line number (header section H) that is in use on the input communication line.

Further, as shown in FIG. 3, in the area of the memory 500 having the same address as this, the processor 90 writes the logical line number Nl of the input communication line (the logical line number corresponding to the header part H stored in the associative memory 400). ) is stored, which is the logical line number N2 of the output communication line corresponding to the output communication line. Therefore, if the logical line number that matches the header part H separated by the input control device 10 and becomes the verification data of the associative memory 400 is registered in the associative memory 400, the address control output of the corresponding address (for example, 402)
becomes active, and as a result, the logical line number (update header part) stored at the same address in the temporary storage circuit 500
is output and passed to the output control device 30.

The output control device 30 that has received this new header section reads out the temporarily stored communication data from the communication data buffer 20, combines them, and outputs them to the output communication line.

FIG. 4 is a block diagram of a data exchange network including a data exchange according to the present invention. In Figure 4, 1000, ~1
000. is the input terminal, 2000. ~20004 is the output terminal, 100+t~10014°10'Ozt~100s
4.100s+ is a data exchange unit, 200 is a logical line multiplexing device, and 300 is a logical line separating device. By combining the above-described frame relay type data exchange with the logical line multiplexing device 200 and the logical line separating device 300, it is possible to configure a large-scale data exchange as shown in FIG. be.

Next, the exchange operation will be explained with reference to FIG. 4 and FIG. 5.

Input terminal 1000. When logical line data having header parts AI and A2 are sequentially inputted to the data exchange unit 100++, the header parts AI and A2 are converted into header parts B1 and B3 and sent via the logical line multiplexing device 200 to the data exchange unit 1003.
! Output to. Here, the header parts Al and A2 are headers that are locally agreed between the subscriber (not shown) and this data exchange when a call is made and received, and the header parts Bl and
B3 is a call identification number that can be used up to the maximum ring multiplex of this data exchange.

In addition, input terminal 1000. Data Exchange Department 100+
Logical line data is input to s, the header part is converted to B2, and input to the data exchange section 10031. The data exchange section 100s+ includes the header sections B1, B2 . B3 is converted into headers C1, C2, and C3 set to simplify the operation in logical line separation device 300, and output to this separation device 300. Here, for example, CI is sent to data conversion unit 100□4, and C2. C3 is the data conversion unit 100□
This is a preset value that will be routed to 1. The separation device 300 distributes the data from the data exchange section 100g+ according to the header section, for example, the header section C1 is distributed to the data conversion section ioo, . Each data conversion section 100□4.10021 has a header section C1,
C2, C3 as header section DI, D2. Convert to D3. Here, D parts D1, D2. D3 is a header that is locally negotiated between a subscriber (not shown) and this exchange on the output side when a call is made or received.

〔Effect of the invention〕

As explained above, the data exchanger of the present invention can reduce the number of memory accesses associated with updating the header section to one time, and makes the processing associated with updating the header section independent of the processing capacity of the processor. It is possible to improve the exchange processing capacity in proportion to the increase in speed, independently of the call processing capacity that is originally required of the processor.

Furthermore, the data exchanger of the present invention does not encode the address control output of the associative memory and inputs it directly to the temporary storage circuit, thereby realizing high-speed access and miniaturization of the circuit scale, which is advantageous for large-scale integration. The configuration is obtained.

Further, in the data exchanger of the present invention, the word size of the associative memory and the temporary storage circuit can be arbitrarily determined by juxtaposing LSIs, etc., so that data formation in the header section can be made arbitrary and general-purpose.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data exchanger according to an embodiment of the present invention. FIG. 2 is a diagram showing a frame format of logical line data of the data exchanger of the present invention. FIG. 3 is a diagram showing the correspondence between the input logical numbers of the associative memory and the output logical numbers of the temporary storage circuit of the data exchanger of the present invention. FIG. 4 is a block diagram of a data exchange network including a data exchange according to the present invention. FIG. 5 is a diagram for explaining the operation of the data exchange network shown in FIG. 4. 10... Input control device, 20... Communication data buffer, 30... Output control device, 40
. . . Header exchange section, 400 . . . Associative memory, 500 . . . Temporary memory circuit. to

Claims (1)

[Scope of Claims] A data exchange device that updates an input logical line number of logical line data on an input communication line to an output logical line number and outputs the same on an output communication line, wherein the logical line data on the input communication line is input. an input control device that separates the header section into a header section and a communication data section; and an address control signal that compares this header section with a pre-registered input logical line number and corresponds to the address where the matched input logical line number is stored. an associative memory that outputs the address control signal, a temporary storage circuit that outputs a pre-registered output logical line number corresponding to the matched input logical line number, and communication data that temporarily stores the communication data section. a buffer; and an output control device that combines an output logical line number output from the temporary storage circuit and a communication data section output from the communication data buffer and outputs the resultant as logical line data onto the output communication line. A data exchanger characterized by: