JPH10327175A - Switch and switching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the switch that makes a high speed switching not by using the software processing but by the hardware. SOLUTION: A control section 110 of a network interface unit NIU 501 extracts destination information 12 included in received data and discriminates a channel of a transfer destination by cross referencing destination information 12 with transfer destination information 13 based on a table 10. Then received data are transferred to a buffer area 81 via a bus 91. The data are tentatively stored in the buffer area 81. Then the control section 110 writes a fact that data to be sent is in existence in the buffer area 81 to a queue 613 with a pointer denoting an address of the data in the buffer area 81. An NIU 503 properly checks states of queues 613 -643 and reads data from the buffer area 81 in a proper timing based on the pointer when the data to be sent are in existence and sends the data to a channel 3a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch used for transmitting and receiving data between lines in an information communication system.

[0002]

2. Description of the Related Art Information communication systems, especially LANs represented by Ethernet (registered trademark), ATM-LAN, etc.
In (Local Area Network), a type in which a transmission path is shared between terminals has become mainstream.
With the increase in the amount of data transmitted and received via the LAN and the increase in the number of terminals connected to the LAN, it has become difficult to obtain a sufficient transmission capacity in a LAN of a type in which all terminals share a transmission path. . Under these circumstances, LAN switches have recently been used to solve the above-mentioned inconveniences and allow each terminal to use the transmittable band of the transmission path over the entire band.

[0003]

However, the conventional LAN
In the switch, the switching of data on the transmission path is realized by software processing using a processor, so that there is a problem that it is difficult to improve the processing capability. For example, in spite of the performance of the transmission path itself, a bottleneck in the switch device may limit the transmittable band, although the band is originally transmittable.

The present invention has been made to solve such a problem, and an object of the present invention is to realize a switch capable of performing high-speed switching using hardware instead of software processing. It is.

[0005]

Means for Solving the Problems Claim 1 of the present invention
A first unit that recognizes a second line that is a data transmission destination based on data received from a first line that is a data transmission source, and a first unit that recognizes the first line and the second line. A buffer area for storing data received from the first line, a data address in the buffer area, a register for storing information indicating a source and a destination of the data, Transmitting data read from the buffer area to the second line based on the
Unit.

According to a second aspect of the present invention, the switch according to the first aspect is the switch according to the first aspect, wherein the buffer area is connected to each of the first and second units by a first bus. Are formed in the memory area, and the register is connected to the first bus by a second bus different from the first bus.
And a second memory area connected to each of the second unit and different from the first memory area.

According to a third aspect of the present invention, the switch according to the third aspect is the switch according to the second aspect, wherein the second memory area is provided separately in the first and second units, and the information is stored in the first unit. And transmitted through a signal line connecting the second unit serially.

According to a fourth aspect of the present invention, the switch according to the third aspect is the switch according to the third aspect, wherein a plurality of transmission sources exist, and the switch is provided in a second memory area divided and provided in the second unit. Is characterized by holding information for each transmission source.

According to a fifth aspect of the present invention, the switch according to the fifth aspect is the switch according to the fourth aspect, wherein the plurality of second units and the second lines are present in pairs, and the plurality of signal lines are provided in the plurality of first lines. Serial connection between two units, one second
When the other unit receives information indicating that the second line corresponding to the other second unit is the transmission destination, the unit transmits the information to the signal line.

The switch according to claim 6 of the present invention is the switch according to claim 3, wherein the destination information and the transfer destination information are stored in the second memory area while maintaining the correspondence. A table is also stored.

A switch according to a seventh aspect of the present invention is the switch according to any one of the first to sixth aspects, wherein the data has a fixed length.

The switch according to claim 8 of the present invention is the switch according to any one of claims 1 to 6, wherein data is divided into appropriate sizes and stored in a buffer area. Each of the divided data is managed in the form of a chain.

The switching method according to a ninth aspect of the present invention is characterized in that: (a) receiving the data from the first line which is the source of the data, and setting the second destination which is the destination of the data based on the data. A step of recognizing a line, (b) a step of transferring data to a buffer area shared between the first and second lines, and (c) an address of the data in the buffer area and a source of the data. And (d) reading data from the buffer area based on the information and transmitting the data to the second line.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of the switch according to Embodiment 1 of the present invention. Here, a switch for performing switching processing of 4 lines × 4 lines is shown. Network Interface Unit (hereinafter referred to as "NIU".) 50 _{1-50 4,} line 1a to 4a, the 1B to 4B, are respectively connected to the terminals that do not appear in FIG. 1, via the line 1B to 4B While data is input from each terminal, data is transmitted to each terminal via the lines 1a to 4a. Further, NIU50 ₁ ~50 ₄ are respectively connected to the memory 71 by a bus 91. That is, the memory 71 is in a form shared by all NIUs.

[0015] Figure 2 is a block diagram showing a specific configuration of NIU50 _1. The bus 91 and the lines 1a and 1b are connected to the control unit 110, respectively. Bus 15
The table 10 connected to the control unit 110 by the
The destination information 12 and the transfer destination information 13 are stored while maintaining the correspondence. For example, destination information n corresponds to transfer destination information k. Incidentally, also basically NIU50 ₂ ~50 ₄ form the same structure as NIU50 _1.

FIG. 3 is a block diagram showing a specific configuration of the memory 71. A buffer area 81 in the memory 71
And queues 6 _{11 to} 6 ₄₄ (in FIG. 3, they are generally represented as “6 _ij ” alone). Buffer area 81
Is an area for temporarily storing data 14a to 14c to be transmitted. On the other hand, the queue 6 _ij is a register for storing a pointer indicating the address of the data 14 a to 14 c in the buffer area 81 together with other information such as the data length. Here, the queues 6 _ij are provided individually corresponding to the data transmission source and the data transmission destination. That is, the queue 6 _ij stores the pointer and the like when data is transmitted from the line i to the line j. For example, when transmitting data from the line 1 to line 2 the pointer or the like in a queue 6 ₁₂ is stored.

The operation will be described below with reference to FIGS. 1 to 3 by taking as an example a case where data is transmitted from the line 1b to the line 3a. Data to be transmitted, the control unit 1 having a terminal that does not appear in Figure 1 of NIU50 ₁ via the line 1b
10 is input. The control unit 110 extracts the destination information 12 included in the data, determines the destination line by associating the destination information 12 with the transfer destination information 13 based on the table 10. Next, control unit 110 transfers the data to be transmitted to buffer area 81 via bus 91. This data is temporarily stored in the buffer area 81. After the data in the buffer area 81 transfer is complete, the control unit 110, the fact that data to be transmitted exists in the buffer area 81 is written to the queue 6 ₁₃ with a pointer indicating an address of data in the buffer region 81 . Here write to queue 6 ₁₃ since it is assumed the transmission from the line 1b of the data to the line 3a, but the queue 6 ₁₁ when the transmission destination of the data lines 1a, in the case of the line 2a queue 6 ₁₂ to, the writing each queue 6 ₁₄ in the case of the line 4a. NIU50 ₃ queue 6 _{13-6 43}
Is appropriately checked, and if there is data to be transmitted, the data is read from the buffer area 81 at an appropriate timing based on the pointer and transmitted to the line 3a.

According to the switch according to this manner, in the first embodiment, it is possible to realize the switch using hardware, also for sharing buffer region 81 between all NIU50 ₁ ~50 _4, There is no need to copy data between the NIUs, and switching can be speeded up. Furthermore, queues 6 ₁₁ to
Since ₆₄₄ is provided, not only the transmission destination but also the transmission source of the data can be grasped, which is particularly useful in a LAN.

Embodiment 2 FIG. 4 is a block diagram showing a configuration of the switch according to Embodiment 2 of the present invention. The switch according to the second embodiment is different from the switch according to the first embodiment in the following points.

[0020] First a first difference, and the buffer region 81 and queue 6 _{11-6 44} in the first embodiment are the same memory 7
While it was formed in one, the switch according to the second embodiment in that the buffer area 82 and queue 6 _{11-6 44} is formed separately in a separate memory. That is,
In the switch according to the second embodiment, a buffer area 82 for temporarily storing data to be transmitted is provided.
Memory is connected to NIU51 ₁ ~51 ₄ via the bus 92, whereas, queue 6 _{11-6 44} is formed 72
It is connected to the NIU51 ₁ ~51 ₄ via the bus 93.

The second difference is that the buffer area 82 and the memory 72 are connected to the NIU 51 ₁ via the buses 92 and 93.
To 51 ₄ of the result of the connection, respectively, in that the number of external terminals of the control unit included in each NIU is increasing. FIG.
IU51 is a block diagram showing _one specific configuration. A bus 93 is connected to the control unit 111 in addition to the lines 1 a and 1 b and the buses 15 and 92. Therefore, comparing FIG. 2 with FIG. 5, the control unit 111 according to the second embodiment has a higher bus 9 than the control unit 110 according to the first embodiment.
It can be seen that the number of external terminals is increased by three. This is the same for each controller having a NIU51 ₂ ~51 _4.

[0022] FIG. 6 is a block diagram illustrating a data 14a~14c stored in the buffer area 82, the relationship between the queue 6 _ij formed in the memory 72. As described above, the buffer area 82 and the memory 72 are formed separately. However, as in the first embodiment, the queue 6 _ij contains pointers indicating the addresses of the data 14 a to 14 c in the buffer area 82. It is stored together with other information such as the data length.

Hereinafter, the operation will be described mainly on the points different from the first embodiment with reference to FIGS. 4 to 6 taking as an example the case where data is transmitted from line 1b to line 3a.
Data to be transmitted is transmitted from a terminal not shown in FIG.
b, and is input to the control unit 111, and the control unit 111 determines the transfer destination line based on the destination information 12 extracted from the data. Next, the control unit 111 transfers the data to be transmitted to the buffer area 82 via the bus 92. After the data transfer to the buffer area 82 is completed, the control unit 11
1, the effect that the data to be transmitted exists in the buffer area 82, with a pointer indicating an address of data in the buffer area 82 is written to the queue 6 ₁₃ via the bus 93. NIU51 ₃ checks the status of the queue 6 _{13-6 43} appropriately reads a suitable timing that data based on the pointer from the buffer area 82 in the case where data to be transmitted exists, and transmits to the line 3a.

As described above, according to the switch of the second embodiment, the buffer area 82 and the bus 92 are stored in the memory 7
2 and the bus 93, the buffer area 8
The bottleneck caused by the difference in speed between the memory 2 and the memory 72 and the difference in transfer capability between the bus 92 and the bus 93 can be reduced, and higher-speed switching can be realized. . Further, since the bus 92 and the bus 93 are physically separate, an optimum bus width can be adopted according to a system to be applied.

Embodiment 3 In the second embodiment, the buffer area 82 and a memory 72, a result of the respectively connected to NIU51 ₁ ~51 ₄ via the bus 92 and 93, as compared with the switch according to the first embodiment in the control unit included in each NIU Although the number of external terminals to be provided has increased, it is more desirable to reduce the number of external terminals from the viewpoint of cost and the like.

FIG. 7 is a block diagram showing a configuration of a switch according to the third embodiment of the present invention, and FIG.
It is a block diagram showing a specific configuration of the 2 _1. Note that N
IU52 of _{2-52 4} configuration is basically the same as the configuration of NIU52 _1. The switch according to the third embodiment differs from the switch according to the second embodiment in the following points. That is, the memory 72, NIU51 ₁ ~5 via a bus 93 to a queue 6 _{11-6 44} in the second embodiment is formed
1 contrast was connected respectively to _4, a memory 73 which queue 6 _{11-6 44} is formed in the switch according to the third embodiment are arranged in each NIU, queue 6 ₁₁
6 ₄₄ is a point to be managed separately by each NIU.
The information indicating that the data to be transmitted exists in the buffer area 82 and the information regarding the address of the data in the buffer area 82 are stored in the serial signal lines 16 _{12 to} 16 _41.
In that it is forwarded between the NIUs via the.

Hereinafter, the line 1b will be described with reference to FIGS.
The operation will be described mainly on the points different from the second embodiment, taking as an example a case where data is transmitted from to the line 3a. Data to be transmitted is transmitted to the control unit 112 via the line 1b.
The control unit 112 determines the transmission destination line based on the destination information 12 extracted from the data. Next, the control unit 112 transfers the data to be transmitted to the buffer area 82 via the bus 92.

After the transfer of the data to the buffer area 82 is completed, the control unit 112 sends a signal indicating that the data to be transmitted exists in the buffer area 82 together with a pointer indicating the address of the data in the buffer area 82. Line 16
Through ₁₂ forwards to NIU52 _2. NIU 52 ₂
Based on the forwarded information, it is determined whether the data transmission destination is the line 2a. Data transmission destination is line 2
If it is determined that a is stored in any one queue 6 _{12-6 42} according to the information on the source of the line.
On the other hand, if the destination of the data is determined not to line 2a, further via the signal line 16 ₂₃ the information NIU52
Forward to ₃ . In this example, the data transmission destination is line 3a.
Since it is assumed that it is, the information is forwarded to NIU52 _3.

The NIU 52 ₃ performs the same processing as the NIU 52 _2. However, in this example, it is assumed that the data transmission source is the line 1b and the transmission destination is the line 3a. Is queue 6 ₁₃ via the bus 17
(Not shown in FIGS. 7 and 8).

The control unit 112 included in the NIU52 ₃ is based on a pointer in the queue 6 _{13-6 43} situation appropriately check the information that has been forwarded if the data to be transmitted exists buffers the data The data is read out at an appropriate timing from 82 and transmitted to the line 3a.

As described above, according to the switch according to the third embodiment, information relating to the fact that data to be transmitted is present in the buffer area 82 is transmitted by serial signal lines 16 _{12 to} 16 ₄₁ instead of the bus format. It was configured to forward between NIUs. Therefore, there is no need to connect the bus 93 requiring a large number of external terminals to the control unit of each NIU according to the number of bits of data and the like. The number of external terminals can be reduced, and the cost of the switch can be reduced.

Further, in the switch according to the third embodiment, a memory 73 which queue 6 _{11-6 44} are formed,
Each NIU is connected to each control unit via a bus 17 provided individually. Accordingly, the memory 72 which queue 6 _{11-6 44} is formed, the bus 9 which is shared between all NIU
As compared with the second embodiment in which each NIU is connected to the corresponding NIU through the third embodiment, a bottleneck related to the bus 93 can be avoided.

Embodiment 4 FIG. In the third embodiment, the table 10 and the memory 73 are configured separately, but they may be configured together in one memory.

FIG. 9 is a block diagram showing a configuration of a switch according to the fourth embodiment. Basically, Embodiment 3
However, since the specific configuration of the NIU is different, only this portion is shown. Especially it showed only the configuration of NIU53 ₁ in FIG. 9, forming the same configuration as also other NIU53 ₂ ~53 _4.

As shown in FIG. 9, the table 74 is stored in the memory 74 connected to the control unit 112 via the bus 18.
And queues 6 _{11 to} 6 ₄₁ are formed. That is, in the third embodiment, the table 10 and the memory 73 are separately configured, whereas in the fourth embodiment, these are collectively configured in one memory 74, and the memory 74 and the control unit 112 are configured. And were connected by one bus 18.

[0036] FIG. 10 is a block diagram illustrating a data 14a~14c stored in the buffer area 82, the relationship between the queue 6 _ij formed in the memory 74. Although the buffer area 82 and the memory 74 are formed separately, in the fourth embodiment as well as in the first embodiment, the queue 6 _ij stores data 14 a to 14
A pointer indicating the address of 14c is stored together with other information such as the data length.

As described above, according to the switch according to the fourth embodiment, the queues 6 _{11 to} 6 ₄₁ and the table 10 are collectively configured in one memory 74. As compared with the case where the queues 6 _{11 to} 6 ₄₁ and the table 10 are separately configured as described above and each is connected to the control unit 112 by the buses 17 and 15, the control unit 112
, The number of external terminals to be provided can be further reduced by the amount of the bus 17. As a result, the required memory can be reduced or optimized, and the cost can be further reduced.

Embodiment 5 In the fifth embodiment, the switch according to the first embodiment is connected to an ATM-LAN (Asynchronous
Transfer Mode LAN).

FIG. 11 shows ITU-T Recommendation I.T. FIG. 3 is a diagram showing a format of an ATM cell 19 specified by 432 or the like. In the ATM-LAN, an ATM cell 19 having a fixed length of 53 bytes is a unit for transmission and reception, and switching is also performed in units of this. In the ATM-LAN, VPI (virtual path identifier) / VCI (virtual channel identifier) in the 5-byte header corresponds to the destination information 12 shown in FIG. Therefore, the control unit 110 controls the line 1
The VPI / VCI is extracted from the ATM cell 19 input from b, and the transmission destination line is determined based on the transfer destination information 13 obtained by searching the table 10.

FIG. 12 is a block diagram showing a specific configuration of the memory 71. ATM cells 19a-1 transmitted
9c is temporarily stored in the buffer area 81 which is formed in the memory 71, ATM cells in queue 6 _ij 19a~1
A pointer indicating an address in the buffer area 81 of 9c is stored together with other information. Since the unit of data to be transmitted and received is a fixed length of 53 bytes, as shown in FIG.
19c all have the same size.

As described above, the switch according to the first embodiment can be applied to an ATM-LAN, whereby a high-speed switch for an ATM-LAN can be configured using hardware. The buffer area 8
Since all the ATM cells 19a~19c in one of the same size, it is possible to optimize the storage method of data into the buffer area 81, to delete the data length from the information to be stored in the queue 6 _ij Can be.

Although the example in which the switch according to the first embodiment is applied to an ATM-LAN has been described above, the present invention is not limited to this, and the switches according to the second to fourth embodiments can be applied to an ATM-LAN. Needless to say,

Embodiment 6 FIG. In the sixth embodiment, the switch according to the first embodiment is applied to Ethernet.

FIG. 13 is a diagram showing a format of the Ethernet frame 20 specified by IEEE802.3 or the like. In the Ethernet, a frame 20 having a variable length of 64 to 1518 bytes is a unit for transmission and reception, and switching is also performed in units of this. Also,
In Ethernet, the Destination IP Address corresponds to the destination information 12 shown in FIG. Therefore, the control unit 11
0 extracts the Destination IP Address from the Ethernet frame 20 input from the line 1b,
The transmission destination line is determined based on the transfer destination information 13 obtained by searching for “0”.

FIG. 14 is a block diagram showing a specific configuration of the memory 71. As described above, in the Ethernet, the unit of data to be transmitted and received is a variable-length frame. However, using the buffer area 81 in accordance with the maximum value is not preferable in terms of the efficiency of use of the memory 71.
Therefore, as shown in FIG. 14, each frame is divided into an appropriate size and managed in a chain. That is, the frames 20a ₁ , 20a ₂ , 20b, 2
Is divided into 0c ₁ ~20c _3, it is stored in the buffer area 81. In the queue _6ij , a pointer indicating the head of the frame is stored together with other information such as the frame length.

As described above, the switch according to the first embodiment can be applied to the Ethernet, whereby
A high-speed switch for Ethernet can be configured using hardware.

Also, in order to cope with the property of Ethernet that the unit to be transmitted and received is of variable length, the frame is divided into appropriate sizes, and these are managed in a chain, so that the data to the buffer area 81 can be stored. Can be optimized.

Although the example in which the switch according to Embodiment 1 is applied to Ethernet has been described above, the present invention is not limited to this, and it is possible to apply the switch according to Embodiments 2 to 4 to Ethernet. Needless to say.

[0049]

According to the first aspect of the present invention, a switch can be configured using hardware. Further, since the buffer area is shared between the first and second lines, there is no need to copy data between the first and second units, and the switching can be speeded up. Further, since information indicating the transmission source and the transmission destination of the data is stored in the register, not only the transmission destination of the data but also the transmission source can be grasped.

According to the second aspect of the present invention, the first memory area and the second memory area are separately provided, and the first and second memory areas are connected to each other by the first and second buses. To connect to the first and second units, respectively.
Bottleneck caused by a difference in speed between the first and second memory areas and a difference in transfer capability between the first and second buses can be reduced. Further, since the first and second buses are physically separate from each other, an optimum bus width can be adopted according to a system to be applied.

Further, according to the third aspect of the present invention, since information relating to the address of the data in the buffer area is transmitted between the units via a serial signal line, the first and the second information are transmitted. The number of external terminals to be provided for each of the two units can be reduced.

Further, since the first and second units and the second memory area are connected by individual buses and signal lines, respectively, the first and second units are connected between the first and second units. As compared with the case where two memory areas are shared and these are connected by a single bus, a bottleneck related to the single bus can be avoided.

According to the fourth aspect of the present invention, when there are a plurality of transmission sources, the second unit can determine the transmission source of the information.

According to the fifth aspect of the present invention, when there are a plurality of second lines that can be destinations, the second unit corresponding to one actually being the destination is sent to the second unit. And the information can be forwarded, and the effect of claim 4 can be obtained in the register in the second unit.

According to the sixth aspect of the present invention, since the register and the table are collectively configured in the second memory area, external registers to be provided in the first and second control units, respectively. The number of terminals can be further reduced.

According to the seventh aspect of the present invention, since the data to be transmitted has a fixed length,
The method of storing data in the buffer area can be optimized, and in particular, it can be applied to ATM-LAN.

According to the eighth aspect of the present invention, even if each data to be transmitted has a different data length, the method of storing data in the buffer area is optimized. In particular, it can be applied to Ethernet.

According to the ninth aspect of the present invention, since data is switched via a buffer area shared between the first and second lines, the first
There is no need to copy data between the second unit and the second unit, so that high-speed switching can be achieved. Also,
Since the method includes a step of storing information indicating a data transmission source and a transmission destination in a register, not only the data transmission destination but also the transmission source can be grasped.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a switch according to Embodiment 1 of the present invention.

2 is a block diagram showing a specific configuration of NIU50 _1.

FIG. 3 is a block diagram showing a specific configuration of a memory 71.

FIG. 4 is a block diagram showing a configuration of a switch according to Embodiment 2 of the present invention.

5 is a block diagram showing a specific configuration of NIU51 _1.

FIG. 6 shows data 14a stored in a buffer area 82.
FIG. 14 is a block diagram showing a relationship between .about.14c and a queue 6 _ij formed in a memory 72.

FIG. 7 is a block diagram showing a configuration of a switch according to a third embodiment of the present invention.

8 is a block diagram showing a specific configuration of NIU52 _1.

FIG. 9 is a block diagram illustrating a configuration of a switch according to a fourth embodiment.

FIG. 10 shows data 14 stored in a buffer area 82.
FIG. 14 is a block diagram showing a relationship between a to 14c and a queue 6 _ij formed in a memory 74.

FIG. 11 is a diagram showing a format of an ATM cell 19;

FIG. 12 is a block diagram showing a specific configuration of a memory 71.

FIG. 13 is a diagram showing a format of an Ethernet frame 20.

FIG. 14 is a block diagram showing a specific configuration of a memory 71.

[Explanation of symbols]

1a to 4a, 1b to 4b circuit, 50 ₁ to 50 ₄ , 51 _{1
~51 4, 52 1 ~52 4 NIU} , 6 11 ~6 44 queue,
71 to 74 memory, 81, 82 buffer area, 91
～93,15,17,18 bus, 16 _12, 16 _23, 1
6 _34, 16 ₄₁ signal lines, 12 address information, 13 transfer destination information, 110-112 controller, 19,19A～19c
ATM _{cell, 20,20a 1, 20a 2, 20b} , 20c
_{1 to} 20c ₃ frames.

Claims (9)

[Claims] A first unit for recognizing a second line which is a transmission destination of the data based on the data received from a first line which is a transmission source of the data; A buffer area for storing the data received from the first line, shared between the lines, and an address of the data in the buffer area;
A switch comprising: a register that stores information indicating the transmission source and the transmission destination of the data; and a second unit that transmits the data read from the buffer area based on the information to the second line. . 2. The buffer area is formed in a first memory area connected to each of the first and second units by a first bus, and the register is connected to the first bus. The switch according to claim 1, wherein the switch is formed in a second memory area different from the first memory area, the second memory area being connected to each of the first and second units by a different second bus. 3. The second memory area is provided separately in the first and second units, and the information is transmitted through a signal line that serially connects the first and second units. The switch according to claim 2, wherein 4. A plurality of said transmission sources, wherein said register formed in said second memory area provided separately in said second unit holds said information for each of said transmission sources. The switch according to claim 3. 5. A plurality of said second units and said second lines are present in pairs, and said signal line serially connects a plurality of said second units; The switch according to claim 4, wherein the unit transmits the information to the signal line when the unit receives the information indicating that the second line corresponding to the other second unit is the transmission destination. . 6. The switch according to claim 3, wherein a table in which the destination information and the transfer destination information are stored while maintaining the correspondence is stored in the second memory area. 7. The switch according to claim 1, wherein the data has a fixed length. 8. The data processing method according to claim 1, wherein the data is divided into appropriate sizes and stored in the buffer area, and each of the divided data is managed in a chain. The switch according to. 9. (a) receiving the data from a first line that is a data transmission source, and recognizing a second line that is a transmission destination of the data based on the data; (b) Transferring the data to a buffer area shared between the first and second lines; and (c) the address of the data in the buffer area, and the source and destination of the data. And (d) reading the data from the buffer area based on the information and transmitting the data to the second line.