KR100301168B1 - Common buffer type ATM exchange - Google Patents

Abstract

The present invention provides a shared buffer type asynchronous transmission for storing cell data input through any channel among a plurality of channels provided in a shared buffer memory and transmitting the cell data stored in the shared buffer memory to any channel among a plurality of channels provided with the stored cell data. In particular, the mode switch has both an input and an output side having an input / output buffer capable of storing one cell for each port, and data between channels connected to the shared buffer memory and the input / output buffer through an internal cell circular buffer controller. The cyclic buffer that performs matching and the cell data generated from the circular buffer are received and stored in the shared buffer memory side, and the data stored in the shared buffer memory are accessed and provided to the circular buffer side, but are stored in the storage area of the shared buffer memory. Shifting action that combines state change of address several times It is advantageous to design a fast dedicated memory inside the switch because the large data width required for data processing of the existing structure can be kept small, including the address controller that is made through the system, and the serial update of the read address register and the write address register is performed. Due to this, even when the exchange is expanded, it can be easily expanded without a large increase in complexity.

Description

Common buffer type ATM exchange}

The present invention relates to an exchange system according to the asynchronous transfer mode method, and in particular, to solve the problems such as data input / output speed degradation and exchange capacity deterioration caused in the memory management structure of the existing shared buffer type asynchronous transfer mode exchange system. In order to solve the problem, the present invention relates to a shared buffer type asynchronous transfer mode switch that can be easily expanded without increasing the complexity even when the exchange is expanded due to the serial update of the read address register and the write address register according to the pipeline method.

In general, modern people live in a wide variety of information, and means of providing such information have been limited to conventional newspapers and television broadcast news, etc. In recent years, various information from around the world is obtained quickly and easily through computer networks. The desire of network subscribers to provide faster service is increasing.

In order to satisfy the needs of network subscribers, the proposed technology is an ISDN that is currently put to practical use. The ISDN is centered on a 64Kbps circuit switched service and a 16Kbps packet switched service.

The above-mentioned ISDN is conceptually referred to as narrowband ISDN, and next-generation broadband ISDN is focusing on technology development to provide a full capacity of about 150 Mbps or 600 Mbps by drawing optical fibers to subscribers (eg, homes). Therefore, the next-generation broadband ISDN aims to integrate not only telephone and low-speed data but also high-speed file transfer and video transfer.

Accordingly, an ATM system has been proposed in which both services are integrated by adopting the advantages of the conventional packet switching and circuit switching techniques, on the premise of the above-described high-speed transmission path.

The asynchronous transmission mode called ATM is a transmission / switching technology that is the core of the B-ISDN. In general, ATM treats all information as a 53-byte cell (ATM cell). In addition, the protocol was reduced on the premise of high quality transmission. Therefore, the exchange process can be realized in hardware, and the exchange delay can be reduced while accepting the high transmission efficiency of the packet exchange.

In this case, each ATM cell is composed of 53 bytes, each of which has a header of 5 bytes and an information field of 48 bytes, and within the header consisting of 5 bytes, a channel virtual channel for identifying a connection to which the cell belongs. Identifier (VCI), Virtual Path Identifier (VPI), Cell Priority Identifier (CLP) to indicate whether the cell is allowed to be discarded, Cell Termination Identification (PT) to distinguish network control information, and Header Error Detection / Control (HEC) And so on.

In view of the features of the ATM scheme described above, the features of ATM multiplexing are that multi-efficiency higher than time division multiplexing can be obtained by statistical multiplexing, and that the transmission band allocated to each communication can be freely set. The feature is that each ATM switch can independently relay and exchange cells because routing information is stored in the header. Moreover, since the exchange process can be chipped (hardware process), the exchange process speed can be increased.

A shared buffer type ATM switch of the method used in the implementation of an ATM switch, that is, an ATM switch having the characteristics as described above is shown in FIG.

1 is a diagram illustrating a partial configuration of a conventional shared buffer type ATM switch, and a brief description of its configuration and operation includes a multiplexer 10 for selectively outputting one channel for n input channels. The output terminal includes a demultiplexer 20 which selectively transmits one transmission data to any one of n transmission channels.

In addition, a shared buffer memory 30 is provided between the multiplexer 10 and the demultiplexer 20 to store data input and output, thereby temporarily storing data received through an arbitrary channel until the data is transmitted to a corresponding transmission channel. It performs the function.

At this time, read / write registers WR1, WRn, RR1, RRn, decoders 40, 50, and the like are used as a means for adjusting data transmission and reception between the multiplexer 10, the demultiplexer 20, and the shared buffer memory 30. An idle address memory 60 and the like are provided.

The shared buffer memory 30 typically includes a plurality of cell storage areas, and accordingly idles having an address for an empty cell storage area among the cell storage areas provided in the shared buffer memory 30. ) Has an address memory 60.

Also, among the write address registers (WR) and read address registers (RR) read paired for each port, the write address registers WR1 and WRn are empty shared buffers in which the next cell is stored. The address of the memory 30 is stored, and the read address registers RR1 and RRn store the address of the shared buffer memory 30 in which the cell to be output is stored.

In addition, the multiplexer 10 selectively outputs one channel to n input channels and transfers the information to the cell area within the shared buffer memory 30. It is detected and sent to the root decoder 40. The root decoder 40 selects the write address register WR by calculating the output port by looking at the destination of the cell.

Therefore, the input cell data is stored in the data area on the shared buffer memory 30 indicated by the corresponding write address register WR. At the same time, an empty address is stored in the idle address memory 60 together with the cell data, and the address is used to change the write address register WR to a new value at the corresponding port. By repeating the above process, the input for each port is stored in the shared buffer.

On the other hand, when outputting cell data stored in the shared buffer memory 30, first, the cell data and the next cell in the shared buffer memory 30 are referred to by referring to the read address register RR corresponding to the corresponding port. Read this stored address.

The cell data read by the read address register RR is output to the corresponding output port through the demultiplexer 20, and the address of the next cell read along with the cell data is sent to the read address register RR to read the read address register RR. Value is used to update the idle address memory RR to inform the idle address memory 60 that the address is empty. This process is repeated for each output port to output cell data.

Therefore, in the existing shared buffer type ATM switch operating as described above, since the cell data and the address of the next cell are stored in the memory at one time, they have a large memory data width. As a result of this increase in capacitance, it becomes difficult to design a shared buffer memory having fast data input / output speed.

In addition, the read / write register data is read and written all at once, which increases the width of the internally used data bus. This phenomenon increases with the increase in the shared buffer memory, which increases the number of bits in the address to represent the capacity. As a result, there is a problem that is further deepened.

Therefore, in order to have a large number of transmission channels, the capacity of the shared buffer memory needs to be increased. As a result, the address data bus width is increased as in the above-described problem, and the increase in the address data bus width is caused by short circuit or control of each channel. The problem is that the expansion of the switch becomes difficult, so the expansion of the exchange capacity is not easy, and in the exchange system of limited size, there is a problem that the expansion of the exchange capacity is limited.

An object of the present invention for solving the above problems is to solve the problems of the data input / output speed degradation and the extensibility of the exchange capacity that occur in the memory management structure of the existing shared buffer type asynchronous transfer mode exchange system. According to the scheme, a serial buffer update of a read address register and a write address register is provided, thereby providing a shared buffer type asynchronous transfer mode switch that can be easily expanded even when the exchange is expanded.

1 is an exemplary configuration diagram of a conventional shared buffer type asynchronous transfer mode exchange;

2 is an exemplary configuration diagram of a shared buffer type asynchronous transfer mode exchange according to the present invention.

<Description of the symbols for the main parts of the drawings>

100: circular buffer 110: input cell buffer

120: output cell buffer 130: circular buffer controller

200: address controller 210, 220: shift controller

230: idle address memory IR: idle address register

WR: Write Address Register RR: Read Address Register

300: shared buffer memory

A feature of the present invention for achieving the above object is a plurality of cells having cell data stored in the shared buffer memory and the cell data input through any channel of the plurality of channels provided in the shared buffer memory In the shared buffer type asynchronous transfer mode exchanger for transmitting to any channel of the channel, both the input and output sides have an input / output buffer capable of storing one cell for each port and are shared through an internal cell circular buffer controller. A circular buffer for performing data matching between the buffer memory and the channel connected to the input / output buffer; And receiving cell data generated from the circular buffer and storing the data in the shared buffer memory and accessing and storing the data stored in the shared buffer memory to the circular buffer, wherein the address is in accordance with the storage area of the shared buffer memory. It is to include an address controller to be made through the shifting operation combined with the state change of several times.

An additional feature of the present invention for achieving the above object is in the circular buffer to transfer the data by K bits when passing the data to the address controller.

In another additional aspect of the present invention for achieving the above object, the address controller includes write address registers for writing an address for a data storage area on the shared buffer memory, and among the data stored on the shared buffer memory. Read address registers for recording an address of an area in which data to be read and transmitted exist, a first shift register for sequentially circulating a write operation of the write address registers, and a write operation of the read address registers sequentially A second shift register for cycling, an idle address memory for storing address data recorded in the read address registers and the write address registers, and a new main for the next cell in the idle address memory; It reads the address register has to include the children to save.

As another additional feature of the present invention for achieving the above object, the address where the next cell is to be stored during cell data storage is divided into n as in the case of the cell data, so that only h bits of the entire address are stored. The write address register is at the new value while the k + h bits are transferred to the shared buffer memory to store the fragment of the address.

According to another aspect of the present invention for achieving the above object, in the read operation of cell data, the shared buffer memory reads k + h bits of data from an address corresponding to a value of a corresponding read address register received from an address controller. The address controller transmits the k bits of the k + h bits of data received from the shared buffer memory to the circular buffer, and simultaneously transmits the h bits of the fragments of the read address register of the corresponding port. It's used to update.

The above objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is an exemplary configuration diagram of a shared buffer type asynchronous transfer mode switch according to the present invention, and is composed of a circular buffer 100, an address controller 200, and a shared buffer memory 300.

The circular buffer 100 is used as an input / output means in place of the multiplexing / demultiplexer of the existing shared buffer type ATM switch. The circular buffer 100 has an amount capable of storing one cell for each port on both the input side and the output side. It has buffers 110 and 120, and there are two of their groups. The circular buffer 100 is controlled through the cell circular buffer controller 130.

In addition, the address controller 200 is largely composed of the write address registers WR1 to WRn, the read address registers RR1 to RRn, and the arley address memory 230 as in the conventional structure. The difference from the conventional configuration of the above-described address controller 200 is that when the write address registers WR1 to WRn and the read address registers RR1 to RRn are changed to new values, all bits are not changed at once in parallel but missed several times. This is achieved through the shifting operation.

Accordingly, the idle address register IR and the shift left controllers 210 and 220 are additionally provided for the above-described multi-stage shifting operation.

Finally, the shared buffer memory 300 may be viewed as a single echo block as in the conventional art.

An exemplary operation of the shared buffer type asynchronous transfer mode switch according to the present invention configured as described above will be described.

First, in the case of the circular buffer 100, when a cell enters as an input, the input cell is stored in the input cell buffer 110 on one page. Meanwhile, cell buffers of other pages are used to send to the address controller 200. When input is completed for each port and all cells of different pages are simultaneously transferred to the address controller 200, the two pages change positions of each other so that a blank page receives an input and all pages are delivered to the address controller 200. do.

The output side operates in the same manner except for receiving data from the address controller 200 and outputting data received from the output cell buffer 120 constituting the output port. In this case, a cell circular buffer controller 130 is provided in the circular buffer 100 as a means for performing the input / output operation as described above, and the cell circular buffer controller 130 is connected to the input cell greener 1100. The data input / output operation of the output cell buffer 120 is controlled.

When data is transmitted from the circular buffer 100 to the address controller 200 according to the above-described operation, all data is transmitted by K bits at a time instead of at once. This is because the overall structure follows the pipelined scheme, where k bits are assumed to be sent in n divided whole cells.

The data divided by n bits are sent to the address controller 200. The address controller 200 reads through the write address register WR of the corresponding port to find the address of the memory to which the data is to be written. At the same time, the new address for the next cell is read from the idle address memory 230 in the address controller 200 and stored in the idle address register IR.

The data is written to the address of the shared memory thus found, and the address of the next cell is also stored. At this time, the address where the next cell is to be stored is also divided into n as in the case of the cell data, and only h bits of the entire address are stored. The write address register WR starts to change to a new value while k + h bits are transferred to the shared buffer memory 300 to store the corresponding data and fragments of the address. This process causes the address in the idle address register IR to be pushed into the write address register WR by h bits through the shift left controller 210.

In general, assuming a structure that is divided into n operations, n-1 shifting operations are required, which can be performed within a period of processing the n-divided whole cell data.

The k + h bits of data transmitted from the address controller 200 are transferred to the shared buffer memory 300 together with the address of the write address register WR and stored at the corresponding address.

When data is read from the data sharing buffer memory 300, the shared buffer memory 300 reads k + h bits of data from an address corresponding to the value of the read address register RR received from the address controller 200 and reads the data again. The address is sent to the controller 200. In this case, the address controller 200 transmits the k bits of the k + h bits of data received from the shared buffer memory 300 to the circular buffer 100 as it is and at the same time has the address bits of the h bits of the corresponding port. The value of the read address register RR starts to be updated. Before the update process, the value of the read address register RR is fed back to the idle address memory 230, and the read address register RR is shifted left by h bits and updated.

While the invention has been shown and described with respect to particular embodiments, it will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit and scope of the invention as set forth in the claims. Anyone can see it easily.

By providing a shared buffer type asynchronous transfer mode switch according to the present invention operating as described above, the large data width required for data processing of the existing structure can be kept small, which is advantageous for designing a fast dedicated memory inside the switch. The serial update of the read address register and the write address register has the advantage that it can be easily extended even when the exchange is expanded without a significant increase in complexity.

Claims (5)

Shared buffer type for storing cell data input through any channel among a plurality of channels provided in a shared buffer memory and transferring the cell data stored in the shared buffer memory to an arbitrary channel among a plurality of channels provided with the cell data. In an asynchronous transfer mode exchange: A circular buffer having an input / output buffer having a quantity of input / output buffers capable of storing one cell for each port, and performing data matching between the channels connected to the shared buffer memory and the input / output buffer through an internal cell circular buffer controller; And The cell data generated in the circular buffer is received and stored in the shared buffer memory side, and the data stored in the shared buffer memory is accessed and provided to the circular buffer side. A shared buffer type asynchronous transfer mode switch comprising an address controller for effecting a state change through multiple shifting operations. The method of claim 1, The shared buffer type asynchronous transfer mode switch of the circular buffer characterized in that for transmitting the data by K-bit when transferring the data to the address controller. The method of claim 1, The address controller includes write address registers for writing an address for a data storage region on the shared buffer memory; Read address registers for recording an address of an area in which data to be read and transmitted exists among data stored on the shared buffer memory; A first shift register for sequentially cycling a write operation of the write address registers; A second shift register for sequentially cycling a write operation of the read address registers; An idle address memory for storing address data written in the data written in the read address registers and the write address registers; And And an idle address register for reading and storing a new address for the next cell in the idle address memory. The method of claim 1, wherein When storing the cell data, the address where the next cell is to be stored is divided into n as in the case of the cell data, so that only h bits of the entire address are stored. A shared buffer type asynchronous transfer mode switch characterized in that the write address register is changed to a new value while being passed to. The method of claim 1, wherein In the read operation of cell data, the shared buffer memory reads k + h bits of data from the address corresponding to the value of the corresponding read address register received from the address controller and transmits the data back to the address controller, wherein the address controller is read from the shared buffer memory. Among the received k + h bits of data, k bits are transferred to the circular buffer, and at the same time, the shared bits type asynchronous transfer mode is used to update the value of the read address register of the corresponding port with the h bits. Exchanger.