JPH11122257A - Common buffer switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain traffic control with a high efficiency without remarkable increase in number of cell buffer address pointer FIFO sets. SOLUTION: A common buffer control section 8 acquires a cell buffer address FIFO number to be in use, acquires an address at which a cell is stored in a common buffer 4 from an idle address FIFO 10, a header and a payload of the cell transferred to the common buffer 4 are written in the common buffer 4 and an address acquired from the idle address FIFO 10 is queued in cell buffer address pointers FIFO 111 -11n corresponding to the address acquired from the idle address FIFO 10. A cell address stored in the cell buffer address pointers FIFO 111 -11n is read based on a cell output timing of the common buffer control section 8 and on the queued cell to read a cell stored in the common buffer 4 and the cell is outputted with higher priority as the class of higher level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a common buffer type switch, and more particularly to an ATM (Asynchronous Switch).
The present invention relates to a technology that is effective when applied to traffic control in a switch (Transfer Mode) switch.

[0002]

2. Description of the Related Art According to studies made by the present inventor, in an ATM switch or the like for routing fixed-length cells,
For example, a common buffer type switch that temporarily stores cells in a large-capacity shared buffer and performs routing by controlling the reading order is used.

[0003] This corresponds to a cell buffer address pointer FIFO (First In Fi) corresponding to an output port.
rst Out), input cells are stored in a common buffer, and the storage address of each cell is written to a cell buffer address pointer FIFO corresponding to the output port of each cell, and the cell output timing is set. Only the cells stored in the common buffer are read out and output.

To perform priority control such as delay and discard control in such a common buffer type switch, a priority queue for queuing about two or four cells is provided for each output port, and the priority queue is provided in this priority queue. When a cell is written, discard control is performed while observing the degree of accumulation of the queue, and when reading, a delay control is performed by giving priority to the order of reading from the queue, thereby implementing a priority control function.

[0005] The more priority queues are provided, the finer the priority control (for example, the control is performed to separate the priority queues used for traffics having different characteristics such as voice, video, and data so as not to be affected by other traffics). ) Is possible.

References describing this type of ATM in detail include, for example, "Standard A", published by ASCII Corporation on July 1, 1996, edited by The Multimedia Communication Society (ed.).
TM textbooks "P50-P56,
Various traffic controls in the TM exchange are described.

[0007]

However, the present inventor has found that the above-mentioned common buffer type switch has the following problems.

When the priority queue of a cell is to be increased in order to realize fine priority control, the above-mentioned cell buffer address pointer F according to the number of priority queues of the cell is increased.
IFO needs to be increased.

For example, if an attempt is made to construct a common buffer switch having 16 ports, a cell buffer capacity of 32 k cells, a queue length of a priority queue of 32 k entries, and only one priority class per port, a cell buffer is constructed. The required memory capacity is about 1.7 megabytes (53 bytes x 32k), and the memory capacity required to configure the cell buffer address pointer FIFO is 1 megabyte (16 ports x 32k entries x 2 bytes). × Class 1).

However, if the cell buffer capacity is kept at 32 k cells (1.7 megabytes) and the priority class for each port is increased to 8 classes, the memory required for forming the cell buffer address pointer FIFO is required. The capacity is 8 megabytes (32 k entries x 2 bytes x 1
6 ports x 8 classes), which is about 4.7 times the cell buffer capacity of 1.7 megabytes.

In other words, if the priority class per port for priority control is to be increased, the memory capacity constituting the cell buffer address pointer queue is larger than the memory capacity constituting the cell buffer, which results in cost and mounting. There is a problem that it is difficult to realize in terms of aspect.

An object of the present invention is to provide a common buffer type switch capable of performing high-efficiency traffic control without greatly increasing the number of cell buffer address pointer FIFOs.

[0013]

A common buffer type switch according to the present invention comprises a plurality of cell buffer address pointers for sequentially storing cell storage addresses in a common buffer so that cells stored in the common buffer form a queue. FI
FO, a first storage unit storing a FIFO allocation table for assigning an output port and a priority class in each of the cell buffer address pointer FIFOs, and a FIFO storage table defined in the FIFO storage table of the first storage unit. And a common buffer control unit for controlling cell queuing based on the information.

Further, the common buffer type switch of the present invention includes a second storage unit storing a cell read control table for designating read control in a priority queue configured based on information defined in the FIFO allocation table. It is provided.

As described above, the number of priority classes can be increased or decreased for each port, so that traffic control can be efficiently performed with a small number of cell buffer addresses FIFO.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a common buffer type switch according to Embodiment 1 of the present invention, and FIGS. 2 and 3 are used for a common buffer type switch according to Embodiment 1 of the present invention. FIGS. 4 and 5 are explanatory views of different examples of a queue configuration configured in the common buffer of the common buffer type switch according to the first embodiment of the present invention. FIGS. 6 is a format diagram of a cell used in the first embodiment of the present invention, and FIG. 7 is a block diagram of a cell format in a common buffer control unit of the common buffer type switch according to the first embodiment of the present invention.

In the first embodiment, the common buffer type ATM switch 1 is an ATM-LAN (Local A
The ATM switch is one of ATM self-routing switches used in ATM exchanges of the same area. This common buffer type switch 1 is connected to the ATM-LA
The cell multiplexing unit 2 multiplexes the cells S (FIG. 6) input to the plurality of input ports P0 to Pn via the N network.

The cell multiplexing section 2 is connected to a common buffer 4 via a signal line 3 for transferring cells S multiplexed and output from the cell multiplexing section 2. The common buffer 4 temporarily buffers the cells S multiplexed and output from the cell multiplexing unit 2.

Further, the common buffer 4 is connected to a cell distributor 6 via a signal line 5 for transferring the cells S read from the common buffer 4. This cell distribution unit 6
Receives the cell S read from the common buffer 4 and distributes the cell S to predetermined output ports among the plurality of output ports PO0 to POn.

The cell multiplexing unit 2 is connected to a common buffer control unit 8 via a routing information transfer interface line 7.
It is connected to the. The common buffer control unit 8 is connected to the common buffer 4 via a control signal line 9.

The common buffer control unit 8 has an empty address FIFO 10 for sequentially storing empty buffer addresses of the common buffer 4, and a cell buffer address pointer F
IFOs 11 _{1 to} 11 _n are connected. The cell buffer address pointer FIFOs 11 _{1 to} 11 _n sequentially store cell storage addresses in the common buffer 4 so that the cells S stored in the common buffer 4 form a queue.

Further, a table storage unit (first storage unit) 12 is connected to the common buffer control unit 8. The table storage unit 12 stores the cell buffer address pointers FIFO 11 _{1 to} 11 _n in any output port P.
A FIFO assignment table FT defining which priority class of O0 to POn is assigned is stored.
The common buffer control unit 8 controls queuing of the cells S in the common buffer 4 based on the information defined in the FIFO allocation table FT.

The FI stored in the table storage unit 12
As shown in FIGS. 2 and 3, the FO assignment table FT includes various assignment information tables defined for the common buffer control unit 8 to control various priority control functions. For example, the output ports PO0 to POn (FIG. 1) are included in the FIFO allocation tables FT shown in FIGS.
Output port number D1 and priority class number D2
And the cell buffer address pointer number D3 is written in the FIFO allocation table FT.
Differs in the definition of the priority class number D2.

Here, the FIF shown in FIGS.
The queue configuration defined in the O allocation table FT will be described with reference to FIGS.

First, in the case of the allocation information defined in the FIFO allocation table FT in FIG. 2, as shown in FIG. 4, all the port numbers 0 to N have four priority classes, and all of them have the same queue configuration. Defined.

On the other hand, the FIFO allocation table F shown in FIG.
In the case of the allocation information defined by T, as shown in FIG.
Port with 6 priority queues and 2 priority queues
One port is defined to appear alternately.

Here, a plurality of input ports P0-P of the common buffer type switch 1 are connected via an ATM-LAN circuit network.
The format of the cell S input to n will be described. As shown in FIG. 6, the cell S includes a virtual path identifier (VPI) for identifying which virtual path is used, a virtual channel identifier (VCI) that is a path and a number used in each relay section, and user information. And a header H including a header error control code and the like, and a payload P which is a field for transferring user data.

In the common buffer type switch 1, the format of the cell S1, which is information on which the cell S performs self-routing, will be described.
As shown in FIG. 7, output ports PO0 to POn (FIG. 1)
, A routing information field F including an output port number C1 and a priority class number C2, which are numbers allocated to the above, and the above-described header H and payload P.

Next, the operation of the present embodiment will be described with reference to FIGS.
This will be described with reference to FIGS. 3, 6, and 7.

First, the cell multiplexing unit 2 has input ports P0 to P0.
From the virtual path identifier and the virtual channel identifier stored in the header H of the cell S input from Pn, the routing information of the output port number C1 and the priority class number C2, which are the numbers of the output ports PO0 to POn, is set in advance. obtain.

The cell multiplexing unit 2 transfers the routing information to the common buffer control unit 8,
The header H and the payload P of the cell S are stored in the common buffer 4
Transfer to

Further, upon receiving the output port number C1 and the priority class number C2 sent from the cell multiplexing unit 2, the common buffer control unit 8 searches the FIFO allocation table FT stored in the table storage unit 12. , A plurality of cell buffer address pointers FIFO11 ₁
To 11 _n cell buffer address pointer number throat D3
To recognize whether to perform queuing.

The common buffer control unit 8 further includes an output port number C1, a priority class number C2, an output port number D1 of the FIFO allocation table FT, and a priority class number D.
An entry that matches 2 can be searched to obtain a self-buffer address pointer number D3 to be used.

Then, the common buffer control section 8 obtains the cell buffer address pointer number to be used by the above-described method and, at the same time, obtains the address for storing the cell S in the common buffer 4 from the free address FIFO 10.

Next, the common buffer control unit 8 outputs a control signal, writes the header H and the payload P of the cell S previously transferred from the cell multiplexing unit 2 to the common buffer 4 into the common buffer 4, The address of the cell S obtained from the address FIFO ₁₀ is queued in the corresponding cell buffer address pointer FIFO 11 _{1 to} 11 _n .

The common buffer control unit 8 reads the storage cell addresses from the cell buffer address pointers FIFO 11 _{1 to} 11 _n queued based on the cell output timing, and based on the read cell cell addresses, stores the common buffer 4.
And outputs the cell S stored in the cell.

Therefore, when the cells S are congested in a plurality of priority queues of one output port, control can be performed such that a class having a higher level is preferentially read out.

Thus, in the first embodiment, the FIF
Since the priority queue for each of the output ports PO0 to POn can be flexibly changed by freely changing the set value of the O allocation table FT according to the required specification, a small cell buffer address pointer FIFO11
_{With 1 to} 11 _n , efficient traffic control can be performed.

(Embodiment 2) FIG. 8 is a block diagram of a common buffer type switch according to Embodiment 2 of the present invention, and FIGS. 9 and 10 are used for a common buffer type switch according to Embodiment 2 of the present invention. FIG. 9 is an explanatory diagram of a different example of a cell read control table to be used.

In the second embodiment, the common buffer type switch 1 is provided with a cell table storage section (second storage section) 13 as shown in FIG. The cell read control table ST is stored.

The cell read control table ST is, as shown in FIGS. 9 and 10, various tables in which priority control and weighting ratio corresponding to each output port number E1 are defined.

The cell read control tables ST shown in FIGS. 9 and 10 exemplarily show output ports PO0 to POn.
Each output port number E1 which is the number of (FIG. 8)
And a priority control mode E2 which is a definition of priority control corresponding to the output port E1, and detailed information E3 which is a definition of a weighting ratio, are written in the cell read control table ST. The definitions of the mode E2 and the detailed information E3 are different.

The cell read control table ST
Designates a queue read control method configured based on information defined in the FIFO allocation table FT stored in the table storage unit 12.

In the priority control mode E2, information relating to an operation mode such as what kind of reading is performed is stored. Here, when “0” is written in the field of the priority control mode E2, the full priority control is performed,
When 1 'is written, weighted priority control is performed.
When 2 'is written, it means equal control.

The complete priority control is a control in which the smaller the number of the queue, the higher the priority, and while cells are stored in the high priority queue, the cells in the low priority queue are not read out. is there.

Further, in the weight priority control, the ratio of each queue is written in the field of detailed information E3 as weight information of each queue. In the case where a cell stays in a plurality of queues, control is performed for reading based on the field of the detailed mode E2.

The equalization control is a control in which, when cells stay in a plurality of queues, all queues are read out equally. Further, band management information (information for defining a read speed) of each queue may be stored in the cell read control table ST, and cell read control may be performed based on the information.

Here, for example, according to the information of the FIFO allocation table FT (FIG. 2), as described above, all the port numbers 0 to N have four priority classes, and as shown in FIG. Output ports PO0-POn are 4
It is defined to have one queue configuration.

According to the cell read control table ST corresponding to this, the port number 0 indicates that the priority control mode E2 is'
0 'is the full priority control, and the queue number 2 in FIG.
The queue number 202 is read out earlier than the queue number 203, the queue number 201 is read out earlier than the queue number 202, and the queue number 200 is read out earlier than the queue number 201.

The port number 1 corresponds to the priority control mode E
2 is “1”, the weighting priority control is performed, and the read ratio of the queue numbers 204 to 207 in FIG. 4 is read at a ratio of 8: 4: 2: 1 with reference to the value of the detailed information E3 of the same entry. Will be.

Further, like the port number 0, the port number N becomes the complete priority information when the priority control mode E2 is "0", and the queue number 2 is larger than the queue number 20M in FIG.
0M-1 is queue number 20 rather than queue number 20M-1
M-2 is queue number 20 rather than queue number 20M-2.
M-3 is preferentially read.

On the other hand, the FIFO allocation table F shown in FIG.
According to T, an output port having six priority queues and an output port having six priority queues as shown in FIG. 5 are defined so as to appear alternately.

According to the cell read control table ST in FIG. 10 corresponding to this, the port number 0 is weighted priority control because the priority control mode E2 is “1”, and the read ratio of the queue numbers 200 to 205 in FIG. Refers to the value of the detailed information E3 of the same entry,
The data is read at a ratio of 32: 16: 8: 4: 2: 1.

The port number 1 corresponds to the priority control mode E
When 2 is 1, weighting priority control is performed, and the queue number M-1 is read out prior to the queue number M in FIG.

Thus, in the second embodiment,
Since the value of the cell read control table ST can be freely changed, the output ports PO0 to POn of the respective cells are controlled.
Each priority control can be flexibly changed, and more efficient traffic control can be performed.

The present invention is not limited to the above-described embodiment, and it goes without saying that various changes can be made without departing from the scope of the present invention.

[0058]

【The invention's effect】

(1) According to the present invention, the number of priority classes for each output port can be freely mapped, so that traffic control can be efficiently performed with a small number of cell buffer address pointer FIFOs.

(2) Further, according to the present invention, the value of the cell read control table can be freely changed, so that priority control for each output port can be flexibly changed, and more efficient traffic can be achieved. Control can be performed.

(3) Further, in the present invention, the common buffer type switch can be reduced in cost and size by the above (1) and (2).

[Brief description of the drawings]

FIG. 1 is a block diagram of a common buffer type switch according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an example of a FIFO allocation table used for the common buffer type switch according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of another example of a FIFO assignment table used in the common buffer type switch according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram illustrating an example of a queue configuration configured in a common buffer of the common buffer type switch according to the first embodiment of the present invention;

FIG. 5 is an explanatory diagram of another example of the queue configuration configured in the common buffer of the common buffer type switch according to the first embodiment of the present invention;

FIG. 6 is a format diagram of a cell used in the first embodiment of the present invention.

FIG. 7 is a cell format block diagram in a common buffer control unit of the common buffer type switch according to the first embodiment of the present invention.

FIG. 8 is a block diagram of a common buffer type switch according to a second embodiment of the present invention.

FIG. 9 is an explanatory diagram of an example of a cell read control table used in the common buffer type switch according to the second embodiment of the present invention.

FIG. 10 is an explanatory diagram of another example of the cell read control table used in the common buffer type switch according to the second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Common buffer type switch, 2 ... Cell multiplexing part, 3 ... Signal line, 4 ... Common buffer, 5 ... Signal line, 6 ... Cell distribution part, 7 ... Routing information transfer interface line, 8 ...
Common buffer control unit, 9 control signal line, 10 free address FIFO, 11 _{1 to} 11 _n cell buffer address pointer FIFO, 12 table storage unit (first storage unit), 13 cell table storage unit 2), F
T: FIFO allocation table, ST: cell read control table.

Continuing on the front page (72) Inventor, Shiro Otani, 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside Hitachi Data Technology Co., Ltd. (72) Inventor Shoji Ise, 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture, Japan Incorporated Hidenori Kawamura 1st Horiyamashita, Hadano-shi, Kanagawa, Japan

Claims (2)

[Claims] 1. A method for temporarily storing cells in a common buffer,
A common buffer type switch for performing routing by controlling a reading order, wherein a plurality of cell buffer addresses sequentially storing cell storage addresses in the common buffer so that cells stored in the common buffer form a queue. Pointer FIFO
A first storage unit storing a FIFO allocation table for assigning an output port and assigning a priority class in each of the cell buffer address pointer FIFOs; and a first storage unit defined in the FIFO allocation table of the first storage unit. A common buffer control unit for controlling cell queuing based on information. 2. The common buffer type switch according to claim 1, wherein a cell read control table for specifying read control in a priority queue configured based on information defined in the FIFO allocation table is stored. A common buffer type switch characterized by including a unit.