JPS6256664B2 - - Google Patents

Info

Publication number
JPS6256664B2
JPS6256664B2 JP55184737A JP18473780A JPS6256664B2 JP S6256664 B2 JPS6256664 B2 JP S6256664B2 JP 55184737 A JP55184737 A JP 55184737A JP 18473780 A JP18473780 A JP 18473780A JP S6256664 B2 JPS6256664 B2 JP S6256664B2
Authority
JP
Japan
Prior art keywords
conductor
package
view
semiconductor
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55184737A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57107059A (en
Inventor
Norikuni Azuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18473780A priority Critical patent/JPS57107059A/ja
Publication of JPS57107059A publication Critical patent/JPS57107059A/ja
Publication of JPS6256664B2 publication Critical patent/JPS6256664B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5221—Crossover interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP18473780A 1980-12-25 1980-12-25 Semiconductor package Granted JPS57107059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18473780A JPS57107059A (en) 1980-12-25 1980-12-25 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18473780A JPS57107059A (en) 1980-12-25 1980-12-25 Semiconductor package

Publications (2)

Publication Number Publication Date
JPS57107059A JPS57107059A (en) 1982-07-03
JPS6256664B2 true JPS6256664B2 (enrdf_load_stackoverflow) 1987-11-26

Family

ID=16158474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18473780A Granted JPS57107059A (en) 1980-12-25 1980-12-25 Semiconductor package

Country Status (1)

Country Link
JP (1) JPS57107059A (enrdf_load_stackoverflow)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4417266A (en) * 1981-08-14 1983-11-22 Amp Incorporated Power and ground plane structure for chip carrier
JPS596563A (ja) * 1982-07-05 1984-01-13 Nec Corp 集積回路装置
JPS6038841A (ja) * 1983-08-12 1985-02-28 Hitachi Ltd 半導体装置
JPS60148148A (ja) * 1984-01-13 1985-08-05 Nec Corp 半導体装置
JPS6122358U (ja) * 1984-07-12 1986-02-08 株式会社東芝 ピングリツドアレイパツケ−ジ
JP2978533B2 (ja) * 1990-06-15 1999-11-15 株式会社日立製作所 半導体集積回路装置
JPH06103721B2 (ja) * 1990-09-25 1994-12-14 松下電工株式会社 半導体チップキャリア
KR100582497B1 (ko) * 2004-02-24 2006-05-23 삼성전자주식회사 정전기 방전 보호 패턴을 포함하는 인쇄회로기판을 갖는 메모리 카드

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5415663A (en) * 1974-01-10 1979-02-05 Nec Corp Semiconductor device
JPS5185349A (enrdf_load_stackoverflow) * 1975-01-24 1976-07-26 Hitachi Ltd
JPS5272169A (en) * 1975-12-12 1977-06-16 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPS57107059A (en) 1982-07-03

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