JPS6253864B2 - - Google Patents

Info

Publication number
JPS6253864B2
JPS6253864B2 JP58224690A JP22469083A JPS6253864B2 JP S6253864 B2 JPS6253864 B2 JP S6253864B2 JP 58224690 A JP58224690 A JP 58224690A JP 22469083 A JP22469083 A JP 22469083A JP S6253864 B2 JPS6253864 B2 JP S6253864B2
Authority
JP
Japan
Prior art keywords
transfer
adapter
controller
input
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58224690A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60116061A (ja
Inventor
Toshiharu Ooshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58224690A priority Critical patent/JPS60116061A/ja
Publication of JPS60116061A publication Critical patent/JPS60116061A/ja
Publication of JPS6253864B2 publication Critical patent/JPS6253864B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
JP58224690A 1983-11-29 1983-11-29 入出力処理方式 Granted JPS60116061A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58224690A JPS60116061A (ja) 1983-11-29 1983-11-29 入出力処理方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58224690A JPS60116061A (ja) 1983-11-29 1983-11-29 入出力処理方式

Publications (2)

Publication Number Publication Date
JPS60116061A JPS60116061A (ja) 1985-06-22
JPS6253864B2 true JPS6253864B2 (enrdf_load_stackoverflow) 1987-11-12

Family

ID=16817705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58224690A Granted JPS60116061A (ja) 1983-11-29 1983-11-29 入出力処理方式

Country Status (1)

Country Link
JP (1) JPS60116061A (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60120458A (ja) * 1983-12-05 1985-06-27 Nec Corp デ−タ転送装置
JPS6275861A (ja) * 1985-09-30 1987-04-07 Fujitsu Ltd チヤネル処理装置
JPS6410372A (en) * 1987-07-03 1989-01-13 Nec Corp Direct memory access restart system
US5333274A (en) * 1991-10-15 1994-07-26 International Business Machines Corp. Error detection and recovery in a DMA controller

Also Published As

Publication number Publication date
JPS60116061A (ja) 1985-06-22

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