JPS6251258A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To reduce base and emitter regions and to reduce base resistance, by forming single crystal silicon layers and polycrystalline silicon layers by vapor growth, forming the base and emitter regions in the single crystal silicon layer by a self-aligning method, and converting the upper parts of the polycrystalline silicon layers into silicide. CONSTITUTION:Oxide film patterns 4 and 5 are formed on an Si substrate 1. Single crystal Si layers 7A and 7B are formed on the Si substrate and polycrystalline Si layers 7C and 7D are formed on the oxide film patterns 4 and 5 both by a vapor growth method. Then, an oxide film 11 is formed on the slant surfaces of the recess parts of the single crystal Si layers 7A and 7B. Nitride films 12B are formed on the bottom surface of the recess parts of the single crystal Si layers 7A and 7B. Then, the upper layer parts of the polycrystalliner Si layers 7C and 7D are converted into a silicide layer 13. An interlayer insulating film 14 is formed on the entire surface other than the slant surface oxide film 11 and the bottom surface nitride film 12B in the recess parts of the single crystal Si layers 7A and 7B. Ions are implanted through the bottom nitride films 12B and a base region is formed. The bottom nitride films 12B are removed, and the single crystal Si layers are exposed. Then, a doped polycrystalline Si film pattern is formed on the exposed surface. Impurities are diffused in the single crystal Si layers by heat treatment, and an emitter region 18 is formed. There after, coentact holes for a base electrode 21 and a collecctor electrode 23 are formed, and wirings are formed.

Description

[Detailed Description of the Invention] [Summary] A single crystal silicon layer and a polycrystalline silicon layer are formed by silicon vapor phase growth, a base region and an emitter region are formed in the single crystal silicon layer by a self-line method, and The upper part of the polycrystalline silicon layer is made of silicide to reduce base resistance.

[Industrial application field]

The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a bipolar transistor.

[Conventional technology]

The increasing integration and performance of semiconductor devices such as ICs and LSIs
Recently, efforts have been made to reduce the size and improve the performance of individual transistors (bipolar transistors).

The self-line method has been adopted in the manufacturing process as an effective means of reducing the size of bipolar transistors (for example, Kazuo Maeda: Latest LSI Process Technology)
Chapter 3 Selfline Technology) (1983), pp
, 324-335. (See Industrial Research Council).

To increase the speed of bipolar transistors, the thickness of the base region below the emitter region is made thinner to form a shallow junction. In addition, bipolar transistors have been proposed that use epitaxial growth technology to reduce the parasitic transistor area and have extremely low base-collector junction capacitance (for example, Hajime Ishikawa: Ultrahigh-speed devices, electronic materials).

April 1982 issue, ρp, 44-51. Figure 5. ■Industrial Investigation Committee).

[Problem that the invention seeks to solve]

The object of the invention is to improve bipolar transistors by reducing the base and emitter areas and also reducing the base resistance rbb'.

Another object of the invention is to provide an improved method of manufacturing bipolar transistors.

[Means for solving problems]

A single crystal silicon layer and a polycrystalline silicon layer are simultaneously formed as one film by silicon vapor phase growth, and a base and an emitter are formed on the single crystal silicon layer by a self-line method, and a base lead-out electrode portion of the polycrystalline silicon layer is formed. The above-mentioned object is achieved by a method of manufacturing a bipolar transistor according to the present invention, which includes siliciding. The manufacturing method according to the present invention includes the following steps (a) to (c): (a) forming an oxide film pattern on a silicon substrate; (b) forming a single crystal on a silicon substrate by silicon vapor phase growth; a step of forming a polycrystalline silicon layer on the silicon layer and an oxide film pattern; (1) a step of selectively forming an oxide film on the slopes of the recesses of the single-crystal silicon layer;
(1) Forming a nitride film on the bottom of the recess in the single-crystal silicon layer; (e) Making the upper layer of the polycrystalline silicon layer a silicide layer; (Form) At the recess in the single-crystal silicon layer A step of forming an interlayer insulating oxide film on the entire surface other than the slope oxide film and the bottom nitride film; (g) Forming a base region by ion implantation through the bottom nitride film;
(i) Step of removing the bottom nitride film to expose the single crystal silicon layer; (e) Forming a doped polycrystalline silicon film pattern at least on the exposed surface of the single crystal silicon layer;
(l) Step of diffusing impurities in the doped polycrystalline silicon film into the single crystal silicon layer by heat treatment to form an emitter region; (l) Forming contact holes for the base electrode and collector electrode; ) forming a wiring;

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail by way of embodiments with reference to the accompanying drawings.

FIGS. 2 to 7 and FIG. 1 are schematic cross-sectional views of a bipolar transistor for explaining the manufacturing process according to the method for manufacturing a bipolar transistor according to the present invention. In addition, NP
This will be explained using an example of an N-type pi transistor.

In FIG. 2, an N+ type buried collector region 2 is selectively formed in a P type silicon substrate 1, and an N type epitaxial layer 3 is formed. It is also possible to omit the epitaxial layer if the impurity creeping up from the buried region is small. An isolation insulating film 4 for isolating the transistor region is formed by selective oxidation. In this case, a thin oxide film (Sin, film 2 not shown) and an oxidation-resistant film (SizNn film 1 not shown) are formed on the transistor region, and the epitaxial layer 3 is partially etched away before thermal oxidation is performed. Let's do it. It should be noted that the isolation insulating film 4 can also have a ■-groove (or U-groove) isolation structure.

After removing the oxide film and thin oxide film, thermal oxidation treatment is performed to form an oxide film (SiO□ film) 5 on the transistor region.
form. A resist pattern 6 is formed by applying a resist film to the entire surface and removing portions corresponding to the base region and collector region by development.

Using resist pattern 6 as a mask, oxide film 5 is selectively etched to form oxide film pattern 5 as shown in FIG. Next, silicon is grown in a vapor phase to form single crystal silicon layers 7A and 7B on the exposed portion of the N-type epitaxial layer 3, and polycrystalline silicon on the oxide film (isolation insulating film 4 and oxide film pattern 5). Form layers 7C and 7D. This single crystal silicon layer? The growth of A and 7B is epitaxial growth. Then, an oxidation-resistant film (Si3h
L film) is formed, and a third layer is formed using a normal photoetching method.
As shown in the figure, a film 8 with a predetermined pattern is formed.7) Then, a polycrystalline silicon layer 7C, ? Expose part of D.

Polycrystalline silicon layer 7c is formed by thermal oxidation treatment.

7D is selectively oxidized to form oxide films (SiO□ films) 9A and 9B (FIG. 4). The oxide film 9A is the isolation insulation 11
4 becomes an isolation film and oxidizes [9
9B is connected to the oxide film pattern 5 to insulate the base region and the collector region. The oxidation-resistant film pattern 8 is removed. Next, Si is grown by chemical vapor deposition (CVD).
An O□ film is formed on the entire surface, and a single crystal silicon layer is etched by anisotropic etching using reactive ion etching (RIB). A.

810.Only on the slope of the recess at 7B. The film 11 is left behind.

This is because out of the 5102 film formed on the entire surface, the portion on the slope is thicker than the other portions in the vertical direction, so RIE is performed to uniformly form polycrystalline silicon layers 7C and 7D on the entire surface.
Single crystal silicon layers 7A, 7B and oxide films 9A, 9B can be left until they are exposed during etching. Then, nitride films 12A and 12B are formed on polycrystalline silicon layers 7C and 7D and single crystal silicon layers 7A and 7B exposed by the thermal nitriding process (FIG. 4). A Si3N4 film may be formed over the entire surface by CVD instead of thermal nitriding. A resist or an organic film (not shown) such as polyimide is applied to the entire surface, and dry control etching (i.e., the organic film and nitride film 12) is formed.
Polycrystalline silicon layer 7C, ? The nitride film 12A on D is removed together with the organic film thereon. At this time, since an organic film remains in the recess, the nitride film 12B on the single crystal silicon layer 7A
remains as is.

Then, the organic material film is removed using a suitable solvent or the like.

Next, a polycrystalline silicon layer corresponding to the base electrode extension portion (polycrystalline silicon layer adjacent to the single crystal silicon layer 7A)
7C,? In order to silicide the surface of D, platinum (p
t) is formed on the entire surface by a vacuum evaporation method, and heat-treated to react polycrystalline silicon and platinum to form a platinum silicide layer 1.
3 (FIG. 5) is formed on the upper layer of the polycrystalline silicon layer. Platinum reacts only with polycrystalline silicon and does not react with oxide films or nitride films. Then, the remaining platinum is removed by etching (regia regia). Molybdenum (Mo) and tantalum (Ta) for silicidation.

Tungsten (W) or the like can also be used, but in these cases, the metal thin film is patterned by a normal phosphorography method and then heat treated.

Phosphorsilicate glass (PSG) or Si that becomes the interlayer insulating film
An NG film 14 is formed on the entire surface by the CVD method, and patterned by the usual phosphorography method so as to cover at least the silicide layer 13 (FIG. 6).

Before performing ion implantation for forming a base region, a resist pattern 15 is formed and a single crystal silicon layer 7A is formed.
An acceptor such as boron is implanted only into the single crystal silicon layer 7B, but not into another single crystal silicon layer 7B. Resist pattern 15, interlayer insulation II! 14 and slope oxidation (Sing) Ht! Boron is implanted into the single crystal silicon layer 7A through the nitride film 12B by an ion implantation method using L as a mask to form a base region 16. Before forming the resist pattern 15, it is also possible to thicken the oxide film 11 (lO) on the slope by thermal oxidation treatment. This allows the transistor area to be made smaller (the emitter width can be narrowed).

After removing the resist pattern 15 and the nitride film 12B, a doped polycrystalline silicon film is formed on the entire surface using the CVD method, and a predetermined pattern of the film 17 is formed using the phosphorography method (FIG. 7).
form. This doped polycrystalline silicon film 17 contains arsenic (As) or phosphorus (P) as a donor, is formed to cover the base region 16, and functions as an emitter electrode.

Next, by heat treatment, arsenic (phosphorus) in the doped polycrystalline silicon layer 17 is removed from the base region 1 of the single crystal silicon layer 7A.
6 to form an emitter region 17. During this heat treatment, annealing is also performed after the base region ion implantation, and the polycrystalline silicon layers 7C, ? A connection between the P wall region 19 and the base region 16 is also made by the boron implanted in the D region. Note that instead of forming the doped polycrystalline silicon film 17 by one-time CVD method, a non-doped polycrystalline silicon film is first formed to about half the thickness, and the slope inside the recess (slope oxide film) is etched by RIE. It is also possible to form a non-doped polycrystalline silicon film again with approximately half the thickness so as to completely fill the recess. In this case, the flat t in the recess of the polycrystalline silicon layer
H conversion can be achieved.

Then, a doped polycrystalline silicon film having a predetermined doping amount is formed by ion implantation of arsenic (or phosphorus).

The interlayer insulating film 14 is selectively etched by lithography to form a contact window with the silicide layer 13, and the slanted oxide film 11 on the single crystal silicon layer 7B is then etched on the single crystal silicon layer 7B. A contact window with the epitaxial layer 3 is then formed. As shown in FIG. 1, a metal such as aluminum (AI) is deposited on the entire surface and formed into a predetermined wiring pattern by lithography to form a base electrode 21, an emitter electrode 22, and a collector electrode 23. It is also possible to form the collector electrode 23 on the single crystal silicon layer 7B instead of on the epitaxial layer 3. In this case, after selective thermal oxidation of the polycrystalline silicon layers 7C and 7D,
P-type impurities such as boron are ion-implanted only into this single crystal silicon layer 7B using the resist pattern as a mask.
＋ ＋ Leave it as an area.

In this way, a bipolar transistor is manufactured according to the manufacturing method of the present invention, and the base and emitter regions are formed by the self-line method, and the silicide layer is formed in the base electrode extension part.

〔Effect of the invention〕

In the manufacturing method according to the present invention, the base region and emitter region can be formed using the self-line method, so the size can be reduced accordingly.Also, since silicide has a resistance 1 to 2 orders of magnitude lower than polycrystalline silicon, silicide can be used as the base electrode. By making it a part of the base, the base resistance can be lowered by that much.

[Brief explanation of the drawing]

2 to 7 and FIG. 1 are schematic cross-sectional views of a bipolar transistor illustrating the manufacturing process according to the method of manufacturing a bipolar transistor according to the present invention. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 4... Isolation insulating film, 5... Oxide film pattern, 7A, 7B... Single crystal silicon layer, 7C, 7 [1... Polycrystalline silicon layer, 9^, 9B...
- Oxide film, 11... Oxide film on slope, 13... Silicide layer, 14... Interlayer insulating film, 16... Base Nb1i, 18... Emitter region. Cross-sectional view of A polar transistor according to the manufacturing method of the present invention 4... Isolation insulating film 5... Oxide film nog turns 7A, 7B... Single crystal silicon layer 'C, 7D... Polycrystalline silicon layer 14... Interlayer insulating film 18... Emitter region Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Fig. 7

Claims (1)

[Claims] 1. The following steps (A) to (C): (A) Step of forming an oxide film pattern on a silicon substrate; (B) Forming a single crystal on the silicon substrate by a silicon vapor phase growth method. Step of forming a polycrystalline silicon layer on the silicon layer and the oxide film pattern; (c) Step of selectively forming an oxide film on the slope of the recess of the single crystal silicon layer; (d) Step of forming the oxide film on the slope of the recess of the single crystal silicon layer Forming a nitride film on the bottom surface of the recess in the silicon layer; (e) Making the upper layer of the polycrystalline silicon layer a silicide layer; (f) Forming the slope at the recess in the single crystal silicon layer forming an interlayer insulating oxide film on the entire surface other than the oxide film and the bottom nitride film; (g) forming a base region by ion implantation through the bottom nitride film; (h) removing the bottom nitride film and (i) forming a doped polycrystalline silicon film pattern on at least the exposed surface of the single-crystal silicon layer; A bipolar transistor comprising: forming an emitter region by diffusing impurities into the single crystal silicon layer; (iii) forming contact holes for base and collector electrodes; and (iii) forming wiring. manufacturing method.