JP3270151B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a step of forming an extraction electrode outside a Si active area used in an integrated circuit.

In recent years, as information processing apparatuses have become more sophisticated,
Larger scale and higher performance of the semiconductor integrated circuit forming the center thereof are further pursued. Among them, one of the performance improvement factors required for the integrated circuit element is speed-up.

In order to achieve high speed, it is necessary to improve the operation speed of the semiconductor element itself and reduce the parasitic resistance of the extraction electrode.

[0004]

2. Description of the Related Art An Si bipolar transistor will be described below as an example. In order to reduce the parasitic resistance and the parasitic capacitance of the bipolar transistor, it is desirable to reduce the pn junction area as much as possible and to form an extraction electrode made of a low-resistance material.

[0005] The material having the lowest resistance is metal, but if metal wiring is performed, heat treatment cannot be performed in subsequent steps. This is for preventing deterioration of the characteristics of the semiconductor element, disconnection of the metal wiring, and occurrence of electric leakage due to alloying or impurity diffusion.

[0006] Instead of metal, silicide is used as a wiring material that can withstand high-temperature processing. Silicide is a compound of Si and a metal, and has good contact characteristics with Si.

Further, metal silicide has a specific resistance of about 1 compared to poly (polycrystalline) Si doped with impurities at a high concentration.
It has orders of magnitude lower (about 1 Ω / square in sheet resistance), has heat resistance and chemical resistance similar to those of Si, and has great advantages such as good compatibility with device processes and the use of self-alignment technology.

When metal silicide is used for the wiring material, it is common to use impurity-doped poly-Si for the base. This is for the purpose of improving the adhesion to the silicon oxide film.

[0009] A so-called polycide structure in which poly-Si is disposed under a metal silicide is heavily used as a metallization material for CMOS and bipolar transistors. Metal silicide / poly Si double film (polycide film)
Example of wiring of self-aligned bipolar transistor by
As shown in FIG.

FIG. 4 is a cross-sectional view showing a part of the integrated circuit. As shown, the wiring for the base extraction electrode and the emitter extraction electrode is formed of a polycide film. The polycide film is formed, for example, of a B-doped poly-Si region 47 and a WSi
_It consists of _two layers 48. Such a bipolar transistor can be formed by the following steps.

An n ⁺ -type Si layer 42 is formed on a p-type Si wafer 41.
Is formed as a buried collector region by selective diffusion, and an n ⁻ -type Si layer 43 is epitaxially grown thereon. The field insulating layer 44 is formed by a selective thermal oxidation process, and an n ⁺ -type region reaching the buried collector region 42 from the surface is formed. A B-doped poly-Si layer 47 and a WSi ₂ layer 48 are deposited on the central active area.

After patterning the poly-Si layer 47 and the WSi ₂ layer 48, an SiO ₂ film 50 is deposited, a through hole is provided at a predetermined position to penetrate to the surface of the n ⁻ -type Si layer 43, and a p-type impurity such as B is implanted. , The base region 45 is selectively formed.

Thereafter, a SiO ₂ film is deposited on the surface by CVD and anisotropically etched to leave a sidewall oxide film 49. This sidewall oxide film separates the base electrode and the emitter electrode.

After depositing a poly-Si layer 51 in a region including the opening of the Si wafer, arsenic is ion-implanted to form an n-type poly-Si layer 51 and patterning is performed. The base region 45 and the emitter region 46 are formed by performing a heat treatment to diffuse and activate the impurities.

Next, a contact hole for a base extraction electrode and a contact hole for a collector electrode are formed, and a W film 52 is grown on the exposed Si surface. An Al base electrode 53 and an Al emitter electrode 5 on each W film 52
4. If the Al collector electrode 55 is formed, the configuration shown in the figure can be obtained.

[0016]

The polycide extraction electrode of which the example is shown in FIG. 4 has a problem that arises in the heat treatment step.

That is, heat treatment is indispensable for forming the emitter region and the base region by ion implantation. N ⁺ -type Si emitter region 46 in Figure 4, the arsenic diffusion from As doped poly Si layer 51, and p-type Si
Outer base region of base region 45 is B-doped poly S
It is formed by boron diffusion from i-layer 47. at the same time,
This heat treatment activates boron implanted in the internal base region.

This heat treatment is performed at a high temperature for a short time, for example, at 105 ° C.
When the diffusion is performed at 0 to 1150 ° C. for 1 to 20 seconds, the diffusion region is formed, but at the same time, the boron of the B-doped poly-Si layer 47 moves rapidly to the upper WSi ₂ layer 48. This is because WSi ₂ has a much larger segregation coefficient (the impurity concentration in WSi is higher than that in Si) and a large diffusion coefficient with respect to boron.

As a result, the WS of the B-doped poly-Si layer 47
A poly-Si layer having a low impurity concentration is formed in the interface region with i ₂ 48. The resistance of this layer is so high that the contact resistance is unusually high. This phenomenon cannot be completely prevented even if the boron concentration of the B-doped poly-Si layer 47 is increased in advance.

On the other hand, the heat treatment is carried out at a low temperature for a long time, for example, 90 hours.
This may be performed at 0 ° C. for 30 minutes to form an emitter-base region. However, the low-temperature heat treatment cannot eliminate the natural oxide film formed on the Si surface. That is, a natural oxide film of about 10 A remains on the surface of the Si wafer immediately before depositing the poly-Si layer 47.

When this thermal oxide film is heated to a temperature of about 1050 ° C. or more, the inside of the Si wafer or the poly Si layer 47 is heated.
But it cannot be absorbed below this temperature. Since the remaining SiO ₂ film increases the contact resistance of the emitter / base region, the characteristics of the transistor deteriorate.

In the case of low-temperature heat treatment, B-doped poly S
Since the activity of the dopant in the i-layer 47 and the As-doped poly-Si layer 51 is low and the resistance cannot be sufficiently reduced, the resistance of the extraction electrode also increases.

For the above reasons, the conventional impurity-doped poly-Si layer and polycide layer electrode still have a problem in the heat treatment step. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device including a lead electrode forming step in which a heat treatment step has a low risk of increasing contact resistance.

[0024]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an impurity-doped first semiconductor layer (2) on a semiconductor substrate; 2) a step of forming a dummy layer (3) formed of a predetermined material thereon; a step of patterning the dummy layer (3) and the first semiconductor layer (2); and a step of forming the dummy layer (3). A second pattern covering the pattern of the first semiconductor layer.
Forming an insulating film (4), selectively etching the second insulating film (4) to form an opening, exposing the dummy layer (3), The dummy layer (3) is selectively etched with respect to the first semiconductor layer (2) and the second insulating film (4) through a cavity under the second insulating film (4). Exposing the first semiconductor layer (2); depositing a metal conductive layer (5) on the first semiconductor layer (2) through the opening; Embedding the conductive layer (5).

[0025]

If a high-temperature heat treatment is performed before the deposition of the metal conductive layer, the impurity-doped poly-Si layer (first semiconductor layer) can be activated without causing any inconvenience due to the high-temperature heat treatment step.
Impurity diffusion or the like into an active region (semiconductor substrate) can be performed.

When the poly-Si layer contacts the Si wafer,
By this step, the SiO at the interface between the poly-Si layer and the Si wafer is
_{Since 2} is absorbed from the interface to the inside, the contact resistance does not increase.

Since the high-temperature treatment step is performed at a stage where the metal is not in contact with the poly-Si layer, alloying or impurity absorption does not occur. As a result of the etching of the dummy layer, the poly-Si layer is exposed in a wide area. Although the diameter of the hole at the entrance is small, the metal conductive layer can be easily buried deep inside by using a thermal decomposition reaction or the like in CVD. As a result,
The resistance of the extraction electrode can be reduced.

Hereinafter, the present invention will be described in more detail with reference to Examples.

[0029]

1 to 3 are sectional views showing steps of manufacturing a bipolar transistor according to an embodiment.

FIG. 1A shows a substrate preparation step. p-type S
An n ⁺ -type Si diffusion region 9 is formed in an element formation region of an i-substrate. Next, a thickness of about 1 [mu] m n ^- -type Si epitaxial layer 8. Further, a first insulating layer (field oxide film) 1 having a thickness of about 5000 A for element isolation / insulation is formed by a selective thermal oxidation technique using a mask.

Further, a donor impurity, for example, phosphorus is diffused at a high concentration in the collector opening region (the left end region in FIG. 1A),
A collector contact region of n ⁺ -type Si is formed.
Thus, the Si substrate 10 is prepared.

Next, as shown in FIG.
An impurity-doped poly-Si layer 2 made of a 500-A B-doped poly-Si layer and a dummy layer 3 made of a Si ₃ N ₄ layer having a thickness of about 1500 A are continuously deposited by a CVD method or the like.
The unnecessary region of the B-doped poly-Si layer 2 and the dummy layer 3 of Si ₃ N ₄ are removed by ordinary photolithography and patterning by etching.

Next, as shown in FIG. 1 (C), a second insulating layer 4 such as a SiO ₂ layer is
Deposit to a thickness of 00A. Then, the emitter / base formation region is patterned using ordinary photolithography and etching techniques. That is, Si
An opening reaching the surface of the substrate 10 is provided.

Next, first, a thickness of 1 mm was formed in the opening by thermal oxidation.
After forming a SiO ₂ film of 100 to 300 A, boron ion implantation is performed thereon. The ion implantation conditions are acceleration voltage 1
0 KeV, [B ⁺ ] = 3 × 10 ¹³ cm ⁻² .

Thereafter, as shown in FIG.
Deposits a SiO ₂ film 13 having a thickness of about 2000A.
After the SiO ₂ film 13 is deposited, leaving the SiO ₂ film 13 only on the opening side wall by using an anisotropic dry etching to remove the SiO ₂ film 13 on the flat portion. A poly-Si layer 7 having a thickness of about 1000 A is formed by CVD so as to cover the exposed Si surface.
Is deposited.

Next, ion implantation of arsenic is performed to form poly S
The i-layer 7 is doped. The ion implantation conditions are an acceleration voltage of 40 KeV and a dose of 1 × 10 ¹⁶ cm ⁻² . After the doping, the poly-Si layer 7 is patterned, and the poly-Si layer 7 is left only at necessary places as shown in FIG.

Next, as shown in FIG. 2B, an opening 6 for a base electrode is formed. Using photolithography and selective etching techniques, at least the second
The opening 6 penetrating through the insulating layer 4 is formed. Dummy layer 3
May be removed, but at least a part of the poly-Si layer 2 is left. In the drawing, the etching stopper layer is the impurity-doped poly-Si layer 2, but the dummy layer 3 of Si ₃
The N ₄ layer may be used as a stopper.

Next, as shown in FIG. 2C, selective etching of the dummy layer 3 is performed. In this embodiment, since the dummy layer 3 is a Si ₃ N ₄ layer, hot phosphoric acid may be used. However, if it is formed of another material, it is obvious that a selective etching solution of the material may be used. Will. Dummy layer 3
Needs to have etching characteristics different from those of the poly-Si layer 2 and the insulating layers 1 and 4.

When immersed in hot phosphoric acid, a poly-Si layer or Si
The O ₂ layer has a low etching rate, and the Si ₃ N ₄ layer is selectively removed to form a cavity as shown. The etching does not always have to reach the innermost part of the cavity, that is, the SiO ₂ film 13 for the side wall. Slightly Si ₃ N ₄
A layer may remain.

Thereafter, a high-temperature heat treatment is performed. The heat treatment condition is, for example, 1100 ° C. for several seconds. As a result, as shown in the figure, the implanted boron is activated to form an internal base region, and at the same time, impurities are diffused from the impurity-doped poly-Si layer to form respective active regions.

That is, boron diffuses from the B-doped poly-Si layer 2 to form an external base region (p region) 11,
Arsenic diffuses from the As-doped poly-Si layer 7 to form an emitter region 12 made of n ⁺ -type Si.

Next, as shown in FIG. 3A, a metal conductive layer 5 is formed. For example, W is deposited by thermal decomposition from a compound using a low pressure CVD method. In this case, W is S
It grows on i, but does not grow on an insulator (in this case, SiO ₂ ), and has a very good wraparound growth state. For this purpose, the Si ₃ N ₄ etching holes (cavities) formed by the process shown in FIG. 2C are filled with W.

W represents not only the opening 6 for the base electrode,
Poly-Si layer 7 in emitter and n ⁺ -type S in collector
It is also deposited on i and becomes each extraction electrode. Therefore, it is possible to contribute to reduction of the emitter resistance and flattening of the collector. The resistance of the base extraction electrode is reduced by about one digit as compared with the case where silicide is used.

FIG. 3B shows the same buried growth step of W as FIG. 3A, but as described above, the Si ₃ N ₄ layer is completely etched off in the step of FIG. It shows the situation when it is not left.

As compared with the case of FIG. 3A, the resistance value of the base extraction electrode is slightly increased, but the conventional silicide (WSi
_The resistance is reduced by almost one digit compared to the case of using ₂ ). The same can be said for the case where the etching is completely performed, but the deposition of W is not complete, and the portion of the Si ₃ N ₄ layer 3 in FIG. 3B becomes hollow.

In the above-described embodiment, the selective growth of W is used. However, the selective growth is not always necessary. If a step of removing unnecessary portions by etching with a resist mask is added later, the blanket W growth can be performed. good.

Finally, as shown in FIG. 3 (C), each electrode, that is, the Al base electrode 14, Al
By forming the emitter electrode 15 and the Al collector electrode 16, a bipolar transistor can be obtained as a part of an integrated circuit device.

In the above embodiment, the first and second insulating layers 1 and 4 are made of SiO ₂ , and the dummy layer 3 is made of Si ₃ N ₄ , but the combination may be reversed. In this case, the selective etching solution for the dummy layer 3 is NH ₄ F, H
F or the like.

Furthermore, SiO ₂ can be used for the first and second insulating layers 1 and 4, and PSG (when poly-Si is n-type), BPSG or BSG (when p-type is used) or the like can be used as the dummy layer 3. . When an HF-based etchant is used, the etching rate of these materials is reduced to SiO ₂ containing no impurities.
10 to 100 times larger than

The metal conductive layer 5 is formed of W,
It can also be formed of Mo, Ti, Cr, Pt, Ta, Au, Ni, Al, or the like. In the case of the above embodiment, the high-temperature heat treatment for forming the active region, ie, the base and emitter regions, was performed after the selective etching of the dummy layer 3 in FIG. However, this heat treatment can be performed at any time after the impurities are doped into the poly-Si layers 2 and 7 and before the formation of the metal conductive layer.

For example, once performed after the step of FIG. 2A or 2B, it is not necessary to perform the step of FIG. 2C once. The present invention is of course applicable to the manufacture of devices other than bipolar transistors, such as CMOS. As long as a poly electrode is used, the present invention can be applied to semiconductor devices other than Si.

FIGS. 5, 6, and 7 show a method of manufacturing a semiconductor device according to another embodiment of the present invention. As shown in FIG. 5A, an n ⁺ -type buried collector region 9 is selectively formed on the surface of a p-type Si substrate 20, and an n ⁻ -type epitaxial layer 8 is grown thereon. Thereafter, a field oxide film 1 is formed on the surface by local oxidation (LOCOS).
Further, by diffusing n-type impurity in the collector contact region to form an n ⁺ -type diffusion region 21 reaching the n ⁺ -type buried collector layer 9.

As shown in FIG. 5B, a CVD SiO ₂ film 2 having a thickness of about 1000 ° is formed on the surface by chemical vapor deposition.
Then, a boron-doped polycrystalline Si layer 2 and a Si ₃ N ₄ layer 3 having a thickness of about 1500 ° are deposited thereon. Thereafter, patterning using photolithography is performed, and the Si ₃ N ₄ layer 3, the polycrystalline Si layer 2, and the CVD SiO ₂ film 23 are patterned as shown in the figure.

As shown in FIG. 5C, an SiO ₂ layer 4 having a thickness of about 3000 ° is deposited on the surface by CVD, and is patterned by photolithography. This SiO
_{The two} layers 4 enclose the previously formed Si ₃ N ₄ layer 3 and the polycrystalline Si layer 2.

As shown in FIG. 6A, the SiO ₂ layer 4
An opening 25 is formed in the laminated structure of the Si ₃ N ₄ layer 3 and the polycrystalline Si layer 2 by photolithography to expose the surface of the n ⁻ -type epitaxial layer 8. Here, a p-type impurity is ion-implanted into the n ⁺ -type epitaxial layer 8 to form a base region.

As shown in FIG. 6 (B), a thickness of about 1
2,000 ° B-doped polycrystalline Si layer 27 is deposited by CVD, a resist layer is spin-coated, and recesses are buried,
Etchback is performed from the surface to remove the remaining polycrystalline Si layer 27 having a depth equal to or less than a certain depth embedded in the resist layer.

After that, the photoresist layer is removed, and the polycrystalline Si layer is further anisotropically etched to remove the polycrystalline Si layer 27 on the flat portion. Thus, a structure as shown in FIG. 6B is obtained.

[0058] Figure 6 (C), the further deposited by CVD SiO ₂ layer 29 having a thickness of about 3000Å on the surface by anisotropic ion etching (RIE), SiO on the sidewalls ₂ Others are removed leaving layer 29.

[0059] Further, as shown in FIG. 7 (A), a polycrystalline Si layer 31 having a thickness of about 1000 Å, As ⁺ ions at an acceleration energy of about 40 KeV, a dose of 1 × 10 ¹⁶ ions are implanted, n ⁺ A type polycrystalline Si layer 31 is formed. After patterning the polycrystalline Si layer 31, the SiO ₂ layer 4 is selectively etched to form an opening 33. This opening 3
3 defines a base electrode extraction region.

If high-temperature heat treatment is performed in this state, n⁺Type
N-type impurities from the crystalline Si layer 31 ^-Type epitaxial
Is diffused into layer 8 to form an emitter region and
⁺The p-type impurity diffuses from the
Forming a contact region to the source region.

Thereafter, as shown in FIG. 7 (B), the Si ₃ N ₄ film 3 is removed from the opening 33 by boiling with hot phosphoric acid to form a cavity under the SiO ₂ layer 4.
Next, as shown in FIG. 7C, the W layer 5 is grown on the exposed surface of the polycrystalline Si layer 2 by performing selective growth of W. Note that the W layer 5 also grows on the polycrystalline Si layer 31 at the same time.

In this W selective growth, high-temperature heat treatment can be avoided, so that absorption of boron from the polycrystalline Si layer 2 can be prevented. Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0063]

As described above, according to the present invention,
It is possible to reduce the occurrence of contact failure and reduce the parasitic resistance of the extraction electrode.

Since the production method of the present invention does not involve an increase in complicated steps, the cost is not substantially increased. A highly reliable and high-performance method for manufacturing a semiconductor device for an integrated circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a part of a method for manufacturing a bipolar transistor according to an embodiment.

FIG. 2 is a cross-sectional view showing a part of the method for manufacturing the bipolar transistor according to the embodiment.

FIG. 3 is a cross-sectional view showing a part of the method for manufacturing the bipolar transistor according to the embodiment.

FIG. 4 is a sectional view showing the structure of a conventional bipolar transistor.

FIG. 5 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 7 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 first insulating layer 2 impurity-doped poly-Si layer 3 dummy layer 4 second insulating layer 5 metal conductive layer 6 base electrode opening 7 poly-Si layer 8 n ^- type Si epitaxial layer 9 n ⁺ -type Si diffusion region 10 Si Substrate 11 Base region 12 Emitter region 13 SiO ₂ film 14 Al base electrode 15 Al emitter electrode 16 Al collector electrode 41 p-type Si wafer 42 n ⁺ -type Si layer 43 n ^-- type Si layer 44 field insulating layer 45 base region 46 n ⁺ Type Si emitter region 47 B-doped poly Si region 48 WSi ₂ layer 49 Thermal oxide film (SiO ₂ film) 50 SiO ₂ film 51 Poly Si layer 52 W layer 53 Al base electrode 54 Al emitter electrode 55 Al collector electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/28-21/288 H01L 21/44-21/445 H01L 21/33-21/331 H01L 29 / 40-29/51 H01L 29/68-29/737 H01L 29/872

Claims (5)

(57) [Claims] A step of forming an impurity-doped first semiconductor layer on a semiconductor substrate; and a step of forming a dummy layer formed of a predetermined material on the impurity-doped first semiconductor layer. Forming the dummy layer (3) and the first semiconductor layer (2); and forming a second layer covering the dummy layer (3) and the pattern of the first semiconductor layer. Forming an insulating film (4); selectively etching the second insulating film (4) to form an opening; and exposing the dummy layer (3); The dummy layer (3) is selectively etched with respect to the first semiconductor layer (2) and the second insulating film (4) to form a cavity below the second insulating film (4). Forming the first semiconductor layer (2) and exposing the first semiconductor layer (2) through the opening. A) depositing a metal conductive layer (5) thereon and embedding the metal conductive layer (5) also in the cavity. Providing an active region defined by a first insulating layer on a semiconductor substrate; and forming an impurity-doped first semiconductor layer on the semiconductor substrate in the active region. Forming a dummy layer (3) made of a predetermined material on the impurity-doped first semiconductor layer (2); and forming the dummy layer (3) and the first semiconductor layer ( 2) patterning the first insulating layer (1) from the active area;
A step of forming a pattern extending upward; a step of forming a second insulating layer (4) covering the pattern of the dummy layer (3) and the first semiconductor layer; and a step of forming the second insulating layer ( 4) selectively etching the opening to form an opening and exposing the dummy layer (3); and connecting the dummy layer (3) to the first semiconductor layer (2) and the opening through the opening. A step of selectively etching the second insulating film (4) to form a cavity below the second insulating film (4) and exposing the first semiconductor layer (2); Depositing a metal conductive layer (5) on the first semiconductor layer (2) from the opening and embedding the metal conductive layer (5) also in the cavity. 3. A step of forming an opening that penetrates through the second insulating layer (4), the dummy layer (3), and the first semiconductor layer (2) and exposes the Si active region. Forming a side wall insulating film on the side wall; and forming another impurity-doped poly-Si in the opening provided with the side wall insulating film.
Forming a layer (7), wherein the step of depositing the metal conductive layer (5) simultaneously deposits the metal conductive layer on another poly-Si layer (7). Method. 4. The semiconductor substrate is a Si substrate, the first and second insulating layers (1, 4) are formed of silicon oxide, and the dummy layer is formed of silicon nitride.
A high-temperature heat treatment step at a temperature of 1050 ° C. or more after the formation of the first semiconductor layer (2) and before the formation of the metal conductive layer (5).
4. The method for manufacturing a semiconductor device according to any one of items 3 to 3. 5. The semiconductor device according to claim 1, wherein said first semiconductor layer is a polysilicon or amorphous silicon layer.