JPS6250848B2 - - Google Patents

Info

Publication number
JPS6250848B2
JPS6250848B2 JP56048591A JP4859181A JPS6250848B2 JP S6250848 B2 JPS6250848 B2 JP S6250848B2 JP 56048591 A JP56048591 A JP 56048591A JP 4859181 A JP4859181 A JP 4859181A JP S6250848 B2 JPS6250848 B2 JP S6250848B2
Authority
JP
Japan
Prior art keywords
data
input
output
control device
output control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56048591A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57164355A (en
Inventor
Joji Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56048591A priority Critical patent/JPS57164355A/ja
Publication of JPS57164355A publication Critical patent/JPS57164355A/ja
Publication of JPS6250848B2 publication Critical patent/JPS6250848B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP56048591A 1981-03-31 1981-03-31 Input and output interface device Granted JPS57164355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56048591A JPS57164355A (en) 1981-03-31 1981-03-31 Input and output interface device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56048591A JPS57164355A (en) 1981-03-31 1981-03-31 Input and output interface device

Publications (2)

Publication Number Publication Date
JPS57164355A JPS57164355A (en) 1982-10-08
JPS6250848B2 true JPS6250848B2 (OSRAM) 1987-10-27

Family

ID=12807640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56048591A Granted JPS57164355A (en) 1981-03-31 1981-03-31 Input and output interface device

Country Status (1)

Country Link
JP (1) JPS57164355A (OSRAM)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59173867A (ja) * 1983-03-22 1984-10-02 Fujitsu Ltd デイスクキヤツシユデ−タ転送制御方式
JPS61281349A (ja) * 1985-06-07 1986-12-11 Oki Electric Ind Co Ltd インタフエ−ス制御方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112543A (OSRAM) * 1973-02-23 1974-10-26
JPS5010127U (OSRAM) * 1973-05-24 1975-02-01
US3950735A (en) * 1974-01-04 1976-04-13 Honeywell Information Systems, Inc. Method and apparatus for dynamically controlling read/write operations in a peripheral subsystem
US4161778A (en) * 1977-07-19 1979-07-17 Honeywell Information Systems, Inc. Synchronization control system for firmware access of high data rate transfer bus
JPS55157051A (en) * 1979-05-25 1980-12-06 Nec Corp Disc cash system

Also Published As

Publication number Publication date
JPS57164355A (en) 1982-10-08

Similar Documents

Publication Publication Date Title
EP0009678B1 (en) Computer input/output apparatus
US4860244A (en) Buffer system for input/output portion of digital data processing system
US4096569A (en) Data processing system having distributed priority network with logic for deactivating information transfer requests
US4209838A (en) Asynchronous bidirectional interface with priority bus monitoring among contending controllers and echo from a terminator
US5093780A (en) Inter-processor transmission system having data link which automatically and periodically reads and writes the transfer data
KR100275407B1 (ko) 컴퓨터 버스 상의 공유 자원에 대한 신속한 액세스
US5574868A (en) Bus grant prediction technique for a split transaction bus in a multiprocessor computer system
US5584033A (en) Apparatus and method for burst data transfer employing a pause at fixed data intervals
KR920013151A (ko) 동기고속 패키트 교환방식 버스를 위한 장치 및 방법
JPS5921048B2 (ja) 多重取出しバス・サイクル操作を与えるシステム
US5129072A (en) System for minimizing initiator processor interrupts by protocol controller in a computer bus system
JPH06309230A (ja) バススヌ−プ方法
JPS621057A (ja) 転送制御装置
US5835957A (en) System and method for a fast data write from a computer system to a storage system by overlapping transfer operations
JPS6250848B2 (OSRAM)
WO1998028679A1 (en) Data transfer with mirroring
US5764935A (en) High speed active bus
JP2570847B2 (ja) データ転送方式
JP3110024B2 (ja) メモリ制御システム
JPH10307788A (ja) バスブリッジ
JPS634219B2 (OSRAM)
JPH0642227B2 (ja) デ−タ転送装置
JP2963696B2 (ja) データ転送制御システム
KR950003885B1 (ko) 큐(queue)를 구비한 중대형 컴퓨터의 입출력 프로세서
KR940003300B1 (ko) 파이프라인 버스 프로토콜을 사용하는 시스템의 메모리큐