JPS6249590A - High speed image processor - Google Patents

Abstract

PURPOSE:To inspect a pattern at a high speed by processing a reference pattern of a large capacity memory by plural image memories which are used successively. CONSTITUTION:Pattern information from an ITV camera 20 is inputted to an image processing processor 16 through a TV controller 5, a high speed bus, etc. of a high speed image processing part 60. Next, a binary data of one picture element each is compared with a binary data of a reference pattern from a large capacity memory 3 of an image memory 9 or 10 by the processor 16, and a pattern is detected. Each of these plural memories 9, 10 is controlled through a controller 11, and when one of them reads out its contents to the processor 16, the reference pattern from the memory 3 is written to the other which has ended read-out. Accordingly, information transfer time from the large capacity memory is covered and a detection processing of many kinds of patterns can be executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a high-speed image processing device that compares and inspects an input pattern with a reference pattern.

[Technical background of the invention]

Conventionally, a high-speed image processing system that compares and inspects a reference pattern and an input pattern has been configured as shown in FIG. In the figure, ■ is the main memory, ■ is the processor, ■ is the large capacity memory, (a) is the bus interface, ■ is the ITV controller, ■ is the image processing processor, ■ is the image memory that holds the reference pattern, and ■ is the comparison An image memory that holds the result (in this case, the difference between the standard pattern and the pattern to be inspected); (20) is an ITV camera for inputting the pattern to be inspected controlled by the ITV controller; (100) is the arithmetic control unit CPU (30); ) and the image processing unit (40), (200) is pattern data (image data)
It is an image bus that transfers images at high speed. The nine standard patterns stored in the large capacity memory ■ on the CPU (30) side are stored in the main memory ■ and the bus interface (A) by the processor (2).
, and is held in the image memory (2) via the bus (100). The reference pattern of this image memory ■ is image processing processor 0.
On the other hand, it is compared with the input pattern to be inspected inputted from the ITV camera (20), and the comparison result is held in the image memory (c).
0).

[Problems with background technology]

In the above conventional system, the reference pattern is the calculation control section (3
Since the reference pattern was stored in a large capacity memory (2) connected to the image processing unit (40), it required a lot of time to transfer the reference pattern to the image processing unit (40), which had the drawback that high-speed pattern inspection was not possible.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed image processing apparatus that eliminates the above-mentioned conventional drawbacks and enables high-speed pattern inspection.

[Summary of the invention]

The present invention includes a controller that controls a large-capacity memory in an image processing section, and a controller that controls the large-capacity memory, receives a standard turn from the large-capacity memory, and stores the pattern by switching it sequentially for each pattern, and after reading, can sequentially store new patterns. a plurality of image memories, an image processing processor that inputs and compares an ITV camera input pattern (pattern to be inspected) and a corresponding reference pattern from the image memory, and notifies a calculation control unit of the result; This objective is achieved by providing dedicated high-speed buses for transferring patterns and reference patterns from each image memory to the image processing processor.

[Embodiments of the invention]

FIG. 1 is a block diagram showing an embodiment of the present invention, and the same numbers as in FIG. 3 indicate parts with the same functions.

Also, (10) is the image memory, and (11) is the controller for the large capacity memory (for example, a disk).

The reference pattern stored in the large capacity memory (2) is transferred to the image memory 0 or (10) via the image bus (200). (16) is an image processing processor;
(50) is an arithmetic control unit CPU, and (60) is a high-speed image processing unit. Figure 2 shows the image processing processor (16) in Figure 1.
), (16-1) (16-6) are the bus interface circuits, (16-2) is the input pattern (1
7) and the reference pattern (18) by an interface circuit (
16-1) to compare the two.

Further, (16-3) is a counter, (16-4) is a test reference value register, and (16-5) is a comparison circuit between the counter value and the test reference value.

Next, the operation will be explained. The image bus (200) consists of a plurality of independent buses, each high-speed bus (a.

b, c...) are respectively connected between the TV controller 0 and the image processing processor (16) or the image memory (9).
) or between (10) and the image processing processor (16), etc.
Used as a dedicated data transfer bus between each section.

The pattern input from the ITV (20) is input to the image processing processor (16) via the TV controller 0 and the bus (a). On the other hand, the image memory (9) is controlled by the controller (11) from the large capacity memory ■.
Alternatively, the reference patterns stored in (10) are also input to the image processing processor (16) once when necessary via dedicated buses (b, c, etc.) and compared pixel by pixel (binary data). If there is a difference, the counter (16-2) is counted up one by one. If this count value is large, the difference between the input pattern and the reference pattern is large. When the counter (16-2) counts a value greater than or equal to the inspection reference value held in the register (16-4), the arithmetic control unit (50) is notified of the NG of the input pattern at that point. Note that the reference pattern is created by using a plurality of image memories (two in the above example) and a plurality of buses corresponding to the number of image memories (two in the above example), so that the next reference pattern is read out while one pattern is being inspected. The images are sequentially input to the image memory.

〔Effect of the invention〕

The present invention is as described above, and the transfer time of a large capacity memory is covered by sequentially using a plurality of image memories, and a plurality of high-speed buses are dedicated to each transfer, so that high speed is achieved. This has the effect of making it possible to inspect many types of patterns.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a detailed diagram of a part of FIG. 1, and FIG. 3 is a block diagram showing a conventional example. 1... Main memory 2... System processor 9. 10... Image memory 16... Image processing processor 50... Arithmetic control section 60... High speed image processing section 100... Connection bus 200. ...Image bus a, b, c...Express bus agent Patent attorney Inoue - Strategy 1 Figure 3

Claims (1)

[Claims] The high-speed image processing unit is equipped with an arithmetic control unit and a high-speed image processing unit, the arithmetic control unit has a system processor for controlling the entire system, and a main memory, and the high-speed image processing unit is connected to the arithmetic control unit by a bus. An image bus consisting of a plurality of buses each working independently, a plurality of image memories connected to this image bus, an image processing processor, a large capacity memory controller, and a large capacity memory connected to this large capacity memory controller. The reference pattern is read from the large-capacity memory via the large-capacity memory controller and the image bus, the reference pattern is stored in the image memory, and the reference pattern from the image memory and the input pattern are compared in the image processing processor. The high-speed image processing device is characterized in that the difference between them is accumulated and when the difference exceeds a reference value, the arithmetic and control unit is notified.