JPS6247162A - Manufacture of insulated gate field effect transistor - Google Patents
Manufacture of insulated gate field effect transistorInfo
- Publication number
- JPS6247162A JPS6247162A JP60187920A JP18792085A JPS6247162A JP S6247162 A JPS6247162 A JP S6247162A JP 60187920 A JP60187920 A JP 60187920A JP 18792085 A JP18792085 A JP 18792085A JP S6247162 A JPS6247162 A JP S6247162A
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- type
- impurity ions
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 150000002500 ions Chemical class 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000001133 acceleration Effects 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 11
- 229910052804 chromium Inorganic materials 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 17
- 238000005468 ion implantation Methods 0.000 description 9
- 229910052796 boron Inorganic materials 0.000 description 5
- -1 boron ions Chemical class 0.000 description 5
- 239000005368 silicate glass Substances 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は絶縁ゲート型電界効果トランジスタの作製方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing an insulated gate field effect transistor.
絶縁ゲート型電界効果トランジスタ、特に２重拡散ＭＯ
３ＦＥＴ （ＤＭＯ３ＦＥＴ）では、ｎチャネルの場合
を例にすると、高いソース・ドレイン間耐圧を獲るため
に、Ｐ型ヘース層に高濃度で比較的深く拡散されたＰ１
型つき出しベース領域が必要である。従来、このＰ＋型
つき出しベース領域を形成するためには、高温で長時間
の熱拡散工を必要とし、しかもＰ型ベース領域とは別の
熱拡散工程にならざるを得す、熱拡散工程が多数回にな
り、作製時間を短縮する上で大きな問題点があった・
〔発明の目的〕
本発明は上記事由に鑑みてなしたものであって、その目
的とするところは、絶縁ゲート型電界効果トランジスタ
のヘース拡散Ｔ程、ソース拡散工程、ゲート酸化］−程
を一回の熱酸化工程により同時に行い、従来の作製方法
に比較して作製時間を大幅に短縮する絶縁ゲート型電界
効果トランジスタの作製方法を提供することにある。Insulated gate field effect transistors, especially double diffused MO
In a 3FET (DMO3FET), taking the case of an n-channel as an example, in order to obtain a high breakdown voltage between the source and drain, P1 is diffused relatively deeply at a high concentration in the P-type heat layer.
A molded base area is required. Conventionally, in order to form this P+ type exposed base region, a thermal diffusion process was required at high temperature for a long time, and it had to be a separate thermal diffusion process from that for the P type base area. [Objective of the Invention] The present invention has been made in view of the above reasons, and its purpose is to An insulated gate field effect transistor that performs the heat diffusion process, source diffusion process, and gate oxidation process of a field effect transistor simultaneously in a single thermal oxidation process, significantly shortening the manufacturing time compared to conventional manufacturing methods. The object of the present invention is to provide a method for producing a.
本発明は、絶縁ゲート型電界効果トランジスタ、特にｌ
） Ｍ ＯＳ Ｆ Ｅ Ｔのベース領域のうち、高濃度
で他のベース領域より深く拡散されるつき出しベース領
域を形成する工程として、イオンの飛程が１μｍ（ミク
ロン）以−Ｌになる高加速電圧のイオン注入法を用いる
ことにより、ヘース拡散工程をソース拡散工程とゲート
酸化工程とともに一回の熱酸化工程によって行い、作製
時間を短縮するＭＯＳＦＥＴの作製方法に係り、その要
旨とするところは一つは第１伝導型半導体基板の一部分
に高加速電圧、高濃度で第２伝導型不純物イオンを注入
する工程、前記第１伝導型半導体基板の表面に至る一部
分の領域であってかつ前記第２伝導型不純物イオンを注
入した部分上の領域に、所望の絶縁ゲート型電界効果ト
ランジスタのしきい値電圧を得るべく制御した加速電圧
、ドーズ量（単位面積あたりの不純物イオンの数）の第
２伝導型不純物イオンを注入する工程、前記第１伝導型
半導体基板の一部分に隣接した領域に低加速電圧、高濃
度で第１伝導型不純物イオンを注入する工程を有するこ
とを特徴とする絶縁ゲート型電界効果ｌ・ランジスタの
作製方法である。The present invention relates to insulated gate field effect transistors, particularly l
) Among the base regions of MOS FET, as a process of forming an exposed base region that is highly concentrated and diffused deeper than other base regions, high acceleration is applied so that the range of ions is 1 μm (micron) or more. This is a MOSFET manufacturing method that uses a voltage ion implantation method to shorten the manufacturing time by performing the Hass diffusion process in a single thermal oxidation process together with the source diffusion process and gate oxidation process. One is a step of implanting impurity ions of a second conductivity type at a high concentration at a high acceleration voltage into a part of the first conductivity type semiconductor substrate, and a part of the region reaching the surface of the first conductivity type semiconductor substrate and the second conductivity type impurity ion. In the region above the part where the conduction type impurity ions are implanted, the second conduction is applied at the acceleration voltage and dose (number of impurity ions per unit area) controlled to obtain the desired threshold voltage of the insulated gate field effect transistor. an insulated gate type electric field characterized by comprising the steps of: implanting type impurity ions, and implanting first conductivity type impurity ions at a low acceleration voltage and high concentration into a region adjacent to a part of the first conductivity type semiconductor substrate. This is a method for manufacturing an effect transistor.
以下、本発明の一実施例を第１図乃至第６図に基づいて
説明する。Hereinafter, one embodiment of the present invention will be described based on FIGS. 1 to 6.
第１図は本発明により得られる絶縁ゲート型電界効果ト
ランジスタの構成例であり、縦型ｎチャネルＤＭＯ３Ｆ
ＥＴである。Ｉ）ＭＯＳＦＥＴのＰ“型つき出しベー
ス領域■ は高加速電圧のイオン注入により形成されて
おり、Ｎ゛型ソース領域■ 、Ｐ型チャネル領域■、ソ
ース領域の下のＰ型ベース領域■ 、ゲート酸化膜■
は−回の熱酸化工程により同時に形成される。その作製
方法の主要な工程を第２図乃至第６図により説明する。FIG. 1 shows a configuration example of an insulated gate field effect transistor obtained according to the present invention, and is a vertical n-channel DMO3F
It is ET. I) The P" shaped base region ■ of the MOSFET is formed by ion implantation at a high acceleration voltage, and includes the N" type source region ■, the P type channel region ■, the P type base region under the source region ■, and the gate. Oxide film ■
and are simultaneously formed by two thermal oxidation steps. The main steps of the manufacturing method will be explained with reference to FIGS. 2 to 6.
まず第２図に示すように、Ｎ−型半導体基板１上にフィ
ールド酸化膜２を形成した後、フォトリソグラフィー技
術を用いて不要の部分をエツチングし、さらに高加速電
圧イオン注入用のレジスト３をフォトリソグラフィー技
術を用いて形成する。レジスト３には１０００人（オン
グストローム）程度のクロム（Ｃｒ）を蒸着した上に１
μｍ（ミクロン）程度の金（Ａｕ）を蒸着した薄膜を用
いる。さらに、つき出しベース領域となる領域４にボロ
ンイオン（Ｂ゛）の飛程が１μｍ（ミクロン）以上にな
る高加速電圧（６００ＫＶ以上）でボロンイオンを注入
する。このとき、加速電圧を６００ＫＶ以上で２種類量
にとし、ボロンイオンを少なくとも２回以十注入して数
ミクロン程度の深さまでボロンイオンを均一に分布させ
る。First, as shown in FIG. 2, after forming a field oxide film 2 on an N-type semiconductor substrate 1, unnecessary portions are etched using photolithography technology, and then a resist 3 for high acceleration voltage ion implantation is formed. Formed using photolithography technology. For resist 3, about 1000 angstroms of chromium (Cr) is deposited, and then 1
A thin film of gold (Au) deposited on the order of μm (microns) is used. Further, boron ions are implanted into the region 4 which will become the exposed base region at a high accelerating voltage (600 KV or more) so that the range of the boron ions (B') is 1 μm (micron) or more. At this time, the accelerating voltage is set to 600 KV or more in two different amounts, and boron ions are implanted at least twice or more to uniformly distribute the boron ions to a depth of about several microns.
次に第３図に示すように高加速電圧イオン注入用レジス
ト３を除去した後、所望のＤ Ｍ □ Ｓ Ｆ Ｆ。Next, as shown in FIG. 3, after removing the high acceleration voltage ion implantation resist 3, a desired D M □ S F F is formed.
Ｔのしきい値電圧を得るように制御した加速電圧、「−
ズ量のボロンイオンをベース領域となる領域５に注入す
る。The acceleration voltage controlled to obtain the threshold voltage of T, "-
Boron ions in an amount of about 100 mL are implanted into the region 5 that will become the base region.
次に第４図に示すように、ベース領域となる領域５の中
央部に、レジスト６を形成した後、ヒ素イオンをソース
領域となる領域７に高濃度に注入する。Next, as shown in FIG. 4, after a resist 6 is formed in the center of the region 5 which will become the base region, arsenic ions are implanted at a high concentration into the region 7 which will become the source region.
次に、レジスト６及びフィールド酸化膜２の開口周縁を
除去した後、第５図示すように熱酸化によりゲート酸化
膜９を形成する。この熱酸化工程によってベース拡散、
ソース拡散、ゲート酸化を一度に行い、つき出しベース
領域■ 、ソース領域■ 、ソース領域の下のベース領
域■ 、チャネル領域８、ゲート酸化膜９を一度に形成
する。Next, after removing the resist 6 and the periphery of the opening of the field oxide film 2, a gate oxide film 9 is formed by thermal oxidation as shown in FIG. This thermal oxidation process causes base diffusion,
Source diffusion and gate oxidation are performed at once to form exposed base region (1), source region (2), base region (2) below the source region, channel region 8, and gate oxide film 9 at one time.
最後に多結晶シリコンゲート１０を形成し、バソシヘー
ション膜を形成した後、ソース電極１２を形成する。パ
ソシヘーション膜１１としてはリン・シリケートガラス
膜（ＰＳＧ膜）またはリン・シケートガラス膜とノンド
ープ−シリケートガラス膜（ＮＳＣ膜）を組合せたもの
等が使用される。Finally, after forming a polycrystalline silicon gate 10 and forming a bathoccupation film, a source electrode 12 is formed. As the passivation film 11, a phosphorus silicate glass film (PSG film) or a combination of a phosphorus silicate glass film and a non-doped silicate glass film (NSC film) is used.
以上の如く、本発明は、０ＭＯ３ＦＥＴのつき出しベー
ス領域を形成するのに、イオンの飛程が１μｍ（ミクロ
ン）以」二になる高加速電圧のイオン注入法を用いるこ
ととしたから、ベース拡散、ソース拡散、ゲート酸化を
一回の熱酸化工程で同時に行うことが可能になり、ＤＭ
Ｏ３ＦＲＴの作製時間を短縮する効果を奏する。As described above, the present invention uses a high acceleration voltage ion implantation method with an ion range of 1 μm (micron) or more to form the protruding base region of an OMO3FET. , source diffusion, and gate oxidation can be performed simultaneously in one thermal oxidation process, and DM
This has the effect of shortening the manufacturing time of O3FRT.
第１図は本発明によるｎチャネル縦型の０ＭＯ３ＦＥＴ
の一実施例を示す断面図、第２図乃至第６図は上記ＤＭ
Ｏ３ＦＥＴの作製工程順を示す断面図である。
１はＮ−型半導体基板、２はフィールド酸化膜、３は高
加速電圧イオン注入用レジスト、４はＰ゛型つき出しベ
ース形成の為のイオン注入領域、■ はＰ゛型つき出し
ベース、５はチャネルヘース形成の為のイオン注入領域
、■ はソース領域下のＰ型チャネルベース領域、６は
ソース形成用イオン注入のためのレジス］・、７はソー
ス領域形成の為のイオン注入領域、■ はＮ゛型ソース
領域、８はチャネル領域、９および■ はゲート酸化膜
、１０は多結晶シリコンゲート、ＩＩはパソシヘーショ
ン膜（ＰＳＧ膜またはＰＳＧ＋ＮＳＧ膜）、１２ソース
電極、１３はＮ゛型半導体基板（ドレイン領域）、１４
はドレイン電極である。Figure 1 shows an n-channel vertical 0MO3FET according to the present invention.
2 to 6 are cross-sectional views showing one embodiment of the above-mentioned DM.
FIG. 3 is a cross-sectional view showing the order of manufacturing steps of an O3FET. 1 is an N-type semiconductor substrate, 2 is a field oxide film, 3 is a resist for high acceleration voltage ion implantation, 4 is an ion implantation region for forming a P'' type exposed base, ■ is a P'' type exposed base, 5 7 is the ion implantation region for forming the source region, ■ is the P-type channel base region under the source region, 6 is the resist for ion implantation for forming the source region], N'-type source region, 8 is a channel region, 9 and ■ are gate oxide films, 10 is a polycrystalline silicon gate, II is a passivation film (PSG film or PSG+NSG film), 12 is a source electrode, 13 is an N'-type semiconductor substrate ( drain region), 14
is the drain electrode.
Claims (3)
濃度で第２伝導型不純物イオンを注入する工程、前記第
１伝導型半導体基板の表面に至る一部分の領域であって
かつ前記第２伝導型不純物イオンを注入した部分上の領
域に、所望の絶縁ゲート型電界効果トランジスタのしき
い値電圧を得るべく制御した加速電圧、ドーズ量（単位
面積あたりの不純物イオンの数）の第２伝導型不純物イ
オンを注入する工程、前記第１伝導型半導体基板の一部
分に隣接した領域に低加速電圧、高濃度で第１伝導型不
純物イオンを注入する工程を有することを特徴とする絶
縁ゲート型電界効果トランジスタの作製方法。(1) A step of implanting impurity ions of a second conductivity type at a high concentration and at a high acceleration voltage into a portion of the first conductivity type semiconductor substrate; The acceleration voltage and dose amount (number of impurity ions per unit area) controlled to obtain the desired threshold voltage of the insulated gate field effect transistor are applied to the region on the part where the 2 conductivity type impurity ions are implanted. an insulated gate type, comprising the steps of implanting conduction type impurity ions, and implanting the first conduction type impurity ions at a low acceleration voltage and at a high concentration into a region adjacent to a portion of the first conduction type semiconductor substrate. How to make a field effect transistor.
濃度で第２伝導型不純物イオンを注入する工程は、イオ
ンの飛程（半導体中に注入されたイオンの半導体表面か
らの平均距離）が１μｍ（ミクロン）以上になる高加速
電圧を用いて、少なくとも２種類以上の高加速電圧で第
２伝導型不純物イオンを２回以上注入することを特徴と
する第１項記載の絶縁ゲート型電界効果トランジスタの
作製方法。(2) The step of implanting impurity ions of the second conductivity type at a high acceleration voltage and high concentration into a portion of the semiconductor substrate of the first conductivity type is based on the ion range (the average distance from the semiconductor surface of the ions implanted into the semiconductor). 2. The insulated gate type according to item 1, wherein the second conductivity type impurity ions are implanted two or more times at at least two types of high acceleration voltages using a high acceleration voltage such that ) is 1 μm (micron) or more. How to make a field effect transistor.
程を一回の熱酸化工程により同時に行う、ことを特徴と
する第１項又は第２項記載の絶縁ゲート型電界効果トラ
ンジスタの作製方法。(3) The method for manufacturing an insulated gate field effect transistor according to item 1 or 2, characterized in that the base diffusion step, the source diffusion step, and the gate oxidation step are performed simultaneously in a single thermal oxidation step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60187920A JPS6247162A (en) | 1985-08-27 | 1985-08-27 | Manufacture of insulated gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60187920A JPS6247162A (en) | 1985-08-27 | 1985-08-27 | Manufacture of insulated gate field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6247162A true JPS6247162A (en) | 1987-02-28 |
Family
ID=16214515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60187920A Pending JPS6247162A (en) | 1985-08-27 | 1985-08-27 | Manufacture of insulated gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6247162A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01287512A (en) * | 1988-05-13 | 1989-11-20 | Minolta Camera Co Ltd | Automatic focus detecting device |
| EP0667035A1 (en) * | 1992-02-11 | 1995-08-16 | Ixys Corporation | Single diffusion process for fabricating semiconductor devices |
| EP0772242A1 (en) * | 1995-10-30 | 1997-05-07 | STMicroelectronics S.r.l. | Single feature size MOS technology power device |
| US5631177A (en) * | 1992-12-07 | 1997-05-20 | Sgs-Thomson Microelectronics, S.R.L. | Process for manufacturing integrated circuit with power field effect transistors |
| US5798554A (en) * | 1995-02-24 | 1998-08-25 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | MOS-technology power device integrated structure and manufacturing process thereof |
| US5841167A (en) * | 1995-12-28 | 1998-11-24 | Sgs-Thomson Microelectronics S.R.L. | MOS-technology power device integrated structure |
| US5900662A (en) * | 1995-11-06 | 1999-05-04 | Sgs Thomson Microelectronics S.R.L. | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
| US6030870A (en) * | 1995-10-30 | 2000-02-29 | Sgs-Thomson Microelectronics, S.R.L. | High density MOS technology power device |
| US6090669A (en) * | 1995-10-09 | 2000-07-18 | Consorzio Per La Ricerca Sulla Microelectronics Nel Mezzogiorno | Fabrication method for high voltage devices with at least one deep edge ring |
| US6228719B1 (en) | 1995-11-06 | 2001-05-08 | Stmicroelectronics S.R.L. | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
-
1985
- 1985-08-27 JP JP60187920A patent/JPS6247162A/en active Pending
Cited By (17)
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| JPH01287512A (en) * | 1988-05-13 | 1989-11-20 | Minolta Camera Co Ltd | Automatic focus detecting device |
| EP0667035A1 (en) * | 1992-02-11 | 1995-08-16 | Ixys Corporation | Single diffusion process for fabricating semiconductor devices |
| EP0667035A4 (en) * | 1992-02-11 | 1996-07-31 | Ixys Corp | Single diffusion process for fabricating semiconductor devices. |
| US5631177A (en) * | 1992-12-07 | 1997-05-20 | Sgs-Thomson Microelectronics, S.R.L. | Process for manufacturing integrated circuit with power field effect transistors |
| US6111297A (en) * | 1995-02-24 | 2000-08-29 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | MOS-technology power device integrated structure and manufacturing process thereof |
| US5798554A (en) * | 1995-02-24 | 1998-08-25 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | MOS-technology power device integrated structure and manufacturing process thereof |
| US6090669A (en) * | 1995-10-09 | 2000-07-18 | Consorzio Per La Ricerca Sulla Microelectronics Nel Mezzogiorno | Fabrication method for high voltage devices with at least one deep edge ring |
| US5981343A (en) * | 1995-10-30 | 1999-11-09 | Sgs-Thomas Microelectronics, S.R.L. | Single feature size mos technology power device |
| US5981998A (en) * | 1995-10-30 | 1999-11-09 | Sgs-Thomson Microelectronics S.R.L. | Single feature size MOS technology power device |
| US5985721A (en) * | 1995-10-30 | 1999-11-16 | Sgs-Thomson Microelectronics, S.R.L. | Single feature size MOS technology power device |
| US6030870A (en) * | 1995-10-30 | 2000-02-29 | Sgs-Thomson Microelectronics, S.R.L. | High density MOS technology power device |
| US6064087A (en) * | 1995-10-30 | 2000-05-16 | Sgs-Thomson Microelectronics, S.R.L. | Single feature size MOS technology power device |
| EP0772242A1 (en) * | 1995-10-30 | 1997-05-07 | STMicroelectronics S.r.l. | Single feature size MOS technology power device |
| US5900662A (en) * | 1995-11-06 | 1999-05-04 | Sgs Thomson Microelectronics S.R.L. | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
| US6228719B1 (en) | 1995-11-06 | 2001-05-08 | Stmicroelectronics S.R.L. | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
| US6051862A (en) * | 1995-12-28 | 2000-04-18 | Sgs-Thomson Microelectronics S.R.L. | MOS-technology power device integrated structure |
| US5841167A (en) * | 1995-12-28 | 1998-11-24 | Sgs-Thomson Microelectronics S.R.L. | MOS-technology power device integrated structure |
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