JPS61242079A - Manufacture of mos type semiconductor element - Google Patents

Abstract

PURPOSE:To minimize capacitance between a gate and a drain, and to increase the speed of operation by forming a gate electrode, shaping a low-concentration drain region through several-time ion implantation and also forming a high- concentration drain layer through ion implantation. CONSTITUTION:A channel stopper 2 and a field oxide film 3 are shaped to a substrate 1, a gate insulating film 4 is formed, and a gate polycrystalline silicon electrode 5 is shaped. A low-concentration drain region 6 is formed by using an ion implantation method. Since the region 6 requires depth deeper than a high-concentration drain region, ion implantation is divided into several times and conducted. The oxide film in a region as the high-concentration drain region 7 is removed, and the high-concentration drain region 7 is shaped to the oxide film section through the ion implantation method. Accordingly, only the annealing of anion implantation region is limited as heat treatment after forming a gate insulating film, and the overlapping of the low- concentration drain region can be minimized in a gate region, thus reducing capacitance between a gate and a drain, then increasing the speed of operation.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a MOS type semiconductor device, and in particular,
The present invention relates to a method for forming lightly doped drains and heavily doped drains for medium and high voltage MOS semiconductor devices.

[Conventional technology]

Conventionally, in this type of medium-voltage and high-voltage MOS type semiconductor devices, after forming a lightly doped drain region, a gate electrode is formed, and then a heavily doped drain region is formed.

A conventional method for manufacturing medium-voltage and high-voltage MOSfi semiconductor devices will be described with reference to FIGS. As shown in FIG. 3(a), a field oxide film 23 is formed by the LOCO8 method. A channel stopper 22.414 film 28 is formed. Thereafter, the photoresist film 29 is patterned using, for example, photolithography technology in order to selectively form the low concentration drain region 26. Next, a low concentration drain region 26 is formed using, for example, ion implantation technology, and the photoresist film 29 is removed. Then, heat treatment is performed to push the low concentration drain region 26 sufficiently deep.

Next, as shown in FIG. 3(b), the thin oxide film 28 of FIG. 3(a) is removed, and a gate oxide film 24 is formed by, for example, a thermal oxidation method. Next, to form a gate electrode, for example, a polycrystalline silicon film is formed over the entire surface by LPCVD, and a polycrystalline silicon gate electrode 25 is selectively formed by photolithography.

Next, as shown in FIG. 3(C), the highly doped drain region 2
7, the oxide film 24 on this region is selectively etched using photolithography. next,
For example, the high concentration drain region 27 is formed by a thermal diffusion method. Thereafter, an interlayer insulating film and aluminum lead electrodes are formed to obtain a MOS type semiconductor device.

[Problem that the invention seeks to solve]

In the above-mentioned conventional medium-voltage and high-voltage MOSfi semiconductor devices, the gate electrode is formed after forming the lightly doped drain layer, so the amount of overlap between the gate electrode and the drain region becomes large and the gap between the gate and drain increases. This has the disadvantage of increasing parasitic capacitance. As a result, this is extremely disadvantageous for high-speed operation. Also, LSI
For example, when used as an output section, current consumption increases and chip size is limited.

The present invention eliminates the above drawbacks, enables high-speed operation without increasing the parasitic capacitance between the gate and drain, and increases the chip size without increasing current consumption when used as an output section. It is an object of the present invention to provide a method for manufacturing a MOS type semiconductor device that can prevent the above problems.

[Means for solving problems]

The method for manufacturing a MOB type semiconductor device of the present invention is a method for manufacturing a medium voltage and high voltage MOS type semiconductor device having a lightly doped drain region and a heavily doped drain region, in which an insulating film is formed in a gate region and a source/drain region. After forming the gate electrode, the first step is to form a low concentration drain region by controlling the concentration and depth using multiple ion implantation methods, and the first step is to remove the insulating film in the high concentration drain formation region to form a thin layer. The method includes a second step of forming an insulating film and a third step of forming a high-density drain region by ion implantation technology. Therefore, since the low concentration drain region is formed on the gate electrode by self-alignment, and the heat treatment is performed only by annealing the ion implantation layer, it is possible to minimize the overlap between the gate electrode and the drain region.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views shown in the order of steps to explain one embodiment of the present invention, and an N-channel type MOS transistor will be described as this embodiment.

First, as shown in FIG. 1(a), after forming a channel stopper region 2 on a P-type semiconductor substrate 1, for example, a LOCO
A field oxide film 3 is formed using the 8 method.

Next, a gate insulator PA4 is formed in the active region using, for example, a thermal oxidation method. Next, a polycrystalline silicon layer is formed by, for example, an LPCVD method, and a gate polycrystalline silicon layer is formed by, for example, a photolithography technique and an etching technique.
'4jIi, 5 is selectively formed.

Next, as shown in FIG. 1(b), an n-type low concentration drain region 6 is formed on the gate polycrystalline silicon electrode 5 with a self-alignment line.
Formed by t-ion implantation technique. At this time, the n-type low-concentration drain region 6 requires a deeper depth than the high-concentration drain region, and in order to obtain a depth with a constant concentration, ion implantation is performed multiple times with different energy conditions, for example, using phosphorus atoms. . FIG. 2 is a diagram showing the profile of the drain region of this example. FIG. 2 shows that the lightly doped drain region 10 is formed by, for example, two ion implantations.

Next, as shown in FIG. 1 (C1), in order to form the high concentration drain region 7, the oxide film in the region that will become the high concentration drain region 7 is selectively removed using photolithography and etching techniques. .

Next, a thin oxide film is formed by, for example, a thermal oxidation method, and a highly concentrated drain region 7 is formed by, for example, an ion implantation technique of arsenic atoms.
form. As shown in FIG. 2, ions with a high concentration are implanted shallowly in the low concentration drain region.

Next, as shown in FIG. 1(d), an insulating film 9 between the eyebrows is formed by, for example, a CVD method, a contact is opened by, for example, a photolithography technique and an etching technique, and a contact is formed by, for example, a sputtering method. An aluminum film is formed, and an aluminum lead electrode 8 is formed by, for example, photophosphorography technology and etching technology. In this way, a MOS type semiconductor device according to an embodiment of the present invention can be manufactured.

Although an N-type MOS transistor has been described as an example, similar effects can be obtained with a P-type MOS transistor or a C-MOS type structure as an IC.

〔Effect of the invention〕

As explained above, the present invention performs ion implantation after forming the gate electrode in forming the lightly doped drain region.
In order to obtain a desired depth with a constant concentration, ion implantation is performed multiple times. Furthermore, the formation of a highly doped drain layer is also performed by ion implantation. As a result, the only heat treatment required after forming the gate insulating film is annealing of the ion-implanted region, making it possible to minimize the overlap between the gate region and the lightly doped drain region, thereby minimizing the gate-drain capacitance. , high-speed operation is possible, and it is possible to avoid increasing current consumption and increasing chip size when used as a part of an LSI, for example, as an output section. .

[Brief explanation of drawings]

1(a) to 1(d) are cross-sectional views shown in the order of steps to explain one embodiment of the present invention, FIG. 2 is a diagram showing the profile of the drain region of the present invention, and FIG. 3(a) -(C) are cross-sectional views shown in order of steps to explain a conventional method for manufacturing a MOS type semiconductor device. 1.21... Semiconductor substrate, 2.22...
・Channel stopper +, :3,23...Fiel)"Oxide film, 4゜24...Gate insulating film,
5.25... Gate electrode, 6, 10.26...
...low concentration drain region, 7.11.27...
... High concentration drain region, 8 ... Aluminum extraction electrode, 9 ... Interlayer insulating film, 28 ...
...Thin insulating film, 29...7 Otoresist film. 1 spear

Claims (1)

[Claims] In a method for manufacturing a medium-voltage and high-voltage MOS type semiconductor device having a low concentration drain region and a high concentration drain region, an insulating film for a gate region and a source/drain region is formed, and then, after forming a gate electrode, a low concentration drain region is formed multiple times. a first step of forming the insulating film using the ion implantation method; a second step of removing the insulating film in the high concentration drain formation region to form a thin insulating film; and forming the high concentration drain region by the ion implantation technique. A method for manufacturing a MOS type semiconductor device, the method comprising: a third step.