JPS6245254A - Resampling device - Google Patents

Abstract

PURPOSE:To smooth a signal transmission between digital systems operated in a different sampling period by selecting properly the characteristic of a digital low pass filter so as to change a sampling period. CONSTITUTION:An input digital signal 6 is written in a buffer memory 1 by a synchronizing pulse train 7. When a new data is written at every sampling period T1, the original data is erased. Then the newest data is read synchronously with the 1st synchronizing pulse train 11. Since the sampling period T1 of the synchronizing pulse train 7 is sufficiently longer than the sampling period TS of the pulse train 11, the same data is read continuously for some times as a filter input signal 8. Since a digital low pass filter 2 passes a frequency component below a predetermined frequency to produce an output signal 9, only the output signal 9 is outputted (10) as an output digital signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Minute Hand] The present invention relates to a sampling device that receives a digital signal as an input and outputs a digital signal having a desired sampling period different from the input sampling period.

[Conventional technology]

Conventional digital signal transmission is often performed at the same sampling period from the transmitting side to the receiving side, and there is no need for a resampling device. In addition, conventionally, when converting the sample period, the input sample period and the output sample period were only in a simple integer ratio, and resampling was performed by thinning the sample data or interpolating the sample data. .

[Problem that the invention seeks to solve]

However, with the development of digital communication networks, communication between networks designed with different design concepts has become important. Sampling has become necessary due to conversion, but there is a problem in that conventional devices cannot cope with such a purpose.

This invention was made to solve the above-mentioned problems. If the ratio of sample period T- is T-/T, 0.5 to 2.0
The overall objective is to obtain a resampling device capable of obtaining a desired value for the output sample period T- within a certain range of degrees.

[Means for solving the problem vr+is] In the glue sampling device of the present invention, the input signal sound is written in the first buffer memory for each sampling period, and read out at a sampling period sufficiently shorter than the sampling period T1 of the input signal. This read digital signal is processed by a digital low-pass filter, the output of this digital low-pass filter is written to a second buffer memory, and the contents of this second buffer memory are read out with an output sampling period T - no pulse train, and the output sample period T - to obtain a digital signal.

[Effect]

In the glue sampling device of the present invention, by appropriately selecting the characteristics of the digital low-pass filter, it is possible to completely change the sampling period without substantially impairing the shape of the spectrum of the input signal.

〔Example〕

Hereinafter, the embodiment gold drawings of this invention will be explained.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which (1) C is a first buffer memory L, +21fl digital low-pass filter, (3) is a second buffer memory IJ, and +41 is a pulse generator. , (5) is a delay circuit, (
6) is an input digital signal, (7Hd is a synchronous pulse train indicating the sampling time of input digital signal (6), (11)
is the first synchronous pulse train generated by the pulse generator (4), and (8) is the filter read out from the buffer memory (1) in synchronization with the first 1 = '1st period pulse train (11). The input signal (9) is the filter output signal obtained by processing the filter input signal (8) by the digital low-pass filter (2), and (12) is the first synchronizing pulse train (11) delayed by the delay circuit (5). The delayed pulse train (12) causes the filter output signal (9) to be written into the second buffer memory (3). (13) represents the second synchronous pulse train generated by the pulse generator (4)\ (10) represents the output digital signal read out from the second buffer memory (3) in synchronization with the second synchronous pulse train. ing. The pulse repetition period T8U of the first synchronization pulse train (11) is sufficiently shorter (less than a fraction) than the pulse repetition period T1 of the synchronization pulse train, and the pulse repetition period T-ij (0 ,5~2)T
The sampling period of the output digital signal (10) can be any period Kl within a range of approximately I.

FIG. 2 is a waveform diagram showing the relationship between the synchronization pulse train (7) and the first synchronization pulse train (11), which indicate the sampling points of the input digital signal, and FIG. 3 shows the relationship between the delay pulse train (12) and the second synchronization pulse train ( 13); FIG.

The input digital signal (6) is written into the first buffer memory (1) by the synchronization pulse train (7) of FIG.

When new data is written every sampling period T1,
The original data will be deleted. Therefore, the newest data is read out in synchronization with the first synchronization pulse train (11). T
Since S is sufficiently shorter than T1, the same data will be read out several times in succession as the filter manual signal (8). At this time, if the write and read timings overlap, write? In this way, the newly convoluted data can be read out with a slight delay.

The operation of the digital low-pass filter (2) will be explained in detail in a later section, but among the frequency components included in the filter (8), only the frequency components below the frequency determined by the design are passed through. A filter output signal (9) is generated.

The filter output signal (9) is sent to the second buffer memory in synchronization with the delayed pulse (12) shown in FIG.
m to be included. New data of the filter output signal (9) is written and old data is erased for each sample group MT8. Since T5>Ts, the data that is erased without being continuously written is written immediately before the pulse of the second synchronization pulse train (13) is input after aJ times of writing. Only the filter output signal (9) is output as the output digital signal (10). Delay circuit (
5) is equal to the processing delay in the digital low-pass filter (2), and the filter output signal (91
and the timing of the delayed pulse train (12).

FIG. 4 is a block diagram showing an analog circuit corresponding to the circuit in FIG.
15) is a low-pass filter, and its transmission characteristic is set to GtSl. Also, (16) is a sampler with period TI, (17)
t: Sampler with m period T-, Xbtd7+.

Gummy pressure
denotes the saliva of the sample point of v (tl.

FIG. 5 is a waveform diagram showing the waveforms of each signal in FIG. 4, and FIG. 4 ta) shows the signal x2. In the same figure [bl is the signal u (tl,
1cl in the same figure represents No. 15 v ltl, and tdl in the same figure represents the signal yek. Figure 5 (At at, when the analog voltage indicated by x Itl is sampled at period T1, xk-2, xk
-1,
t gain, u ltl fist G tsl as signal v ltl
get. That is, the high frequency components in the signal u (tl) are removed by the low-pass filter (15), and the signal v
ftl, and this signal v ttl k sample period MT
- to obtain the signal vek.

According to the circuit of FIG. 1, the signal u ftl (FIG. 5(b)
)), a pulse train with a period T8 amplitude-modulated by the signal u ttl becomes the filter input signal (8), and if a digital low-pass filter (2) with the same transfer characteristics as the low-pass filter (15) is used, the filter output signal(
9), a pulse train of period T8 with amplitude f at tl and W4 is obtained.The second buffer memory (3) in FIG. The most permissible one among the output signals (9) becomes the output digital signal, so the sampler (1) in Figure 4
7) causes the signal V. This is equivalent to obtaining .

FIG. 6 is a frequency characteristic spectrum diagram related to the digital low-pass filter 2) of FIG. 1. However, although a negative value ω does not exist, for convenience of calculation, the spectrum of a negative value ω is shown which is symmetrical to the positive value ω spectrum with respect to the axis of ω=0. Let ω be the highest angular frequency among the frequency components included in the original analog signal, that is, the signal xItl in FIG. The Nyquist frequency ω determined by the sampling period T1 is ω = -, and ω
1...filI I 'l'.

Is the value of T1 so that stipulate. Filter input signal 18
) (corresponding to the double number u ftl in Figure 4) (This power spectrum 'klU (expressed in iω months) is as shown in Figure 6 tal. Among these, the range from -ωi to ωi The power spectrum is the power spectrum of the signal x (tl), and the spectrum outside that range is the signal x.
) is processed by the signal u (tl). Therefore, the characteristic G fsl of the low-pass filter (15) is changed as shown in FIG. (expressed in the form of (iω)1) - If we cut off the components outside the range of ω6 to ωA, we get
In Fig. 5 tel, we obtain a power spectrum similar to the power spectrum of the original signal x ILI, as shown by the power spectrum IV (iω), and therefore the signal v ftl becomes similar to the signal x ltl. In Fig. 6 +bl It is sufficient to set the cutoff angular frequency ωc shown in FIG.

That is, the digital low-pass filter (2) in FIG.
It is sufficient if it has the characteristics shown in FIG. 6 tbl.

Techniques for designing a digital filter that approximates the characteristics shown in FIG.
(u, +u, -1-+uJ-M+1)・(31 pieces M
It is given by JJ~1. Here, θ=ωT3 (5) is called a normalized frequency.

FIG. 7 is a percentage diagram showing the frequency characteristics of the digital low-pass filter (2) used in the present invention, where M=
1 of IHf in case of 17 is shown. In the case of Fig. 7, the value θC corresponding to the cutoff frequency is θ = 2g,...
It is given by (6). From equation (6), the cutoff angular frequency ωC is ω0=ω, -+21, so M −TI/T
Get 8.+81. Equation (8) provides the design conditions for the digital low-pass filter (2) having the configuration of Equation (3).

In this case, considering equation (4) t-, the delay time as a phase characteristic becomes. That is, it can be seen that a delay of half the sampling period T1 of the input digital signal g(6) is generated by the low-pass digit filter (2). Based on equations (8) and (3), a digital low-pass filter (2
) can be designed.

In the above embodiments, a sampling device capable of performing sampling processing on a single signal has been described. However, if a processor that specifically implements a digital low-pass filter has a margin, it is also possible to construct a sampling device capable of performing resampling processing by time-division switching for a plurality of digital signals.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to smoothly transmit signals between digital systems operating at different sampling periods.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the relationship between the synchronization pulse train and the first synchronization pulse train showing the sampling points of the input digital signal in FIG. 1, and FIG. 1 is a waveform diagram showing the relationship between the delayed pulse train and the second synchronous pulse train in Figure 1, Figure 4 is a block diagram showing an analog circuit corresponding to the circuit in Figure 1, and Figure 5 is a waveform diagram showing each signal in Figure 4. FIG. 6 is a spectrum diagram showing frequency mantissa characteristics related to the digital low-pass filter of FIG. 1, and FIG. 7 is a characteristic diagram showing an example of frequency characteristics of the digital low-pass filter used in the present invention. [111'1@1 buffer memory, (2) is a digital low-pass filter, 131: second buffer memory,
(4) is a pulse generator, (5) is a delay circuit, (6) is an input digital signal, +71 [synchronous pulse train of input digital signal, (8) is a filter input signal, (9) is a filter output signal, (10 ) is the output digital signal, (11)
is the first synchronous pulse train, (12) is the delayed pulse train, (1
3) is the second synchronous pulse train. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A first buffer memory into which a digital signal having a sampling period T_I is written every sampling period T_I, a first synchronizing pulse train having a pulse repetition period T_S sufficiently shorter than T_I, and a first synchronizing pulse train having a pulse repetition period T_S sufficiently shorter than T_I; A pulse generator that generates a second synchronous pulse train having an arbitrary pulse repetition period T_O within a range, and a digital signal that reads the contents of the first buffer memory in synchronization with the first synchronous pulse train is input. a digital low-pass filter; a second buffer memory into which the output of the digital low-pass filter is written in synchronization with a pulse train that is obtained by delaying the first synchronizing pulse train by the processing time of the digital low-pass filter; A resampling device comprising means for reading out contents in synchronization with the second synchronization pulse train.