JPH0865105A - Sampling frequency converter - Google Patents

Abstract

PURPOSE: To attain high stability and to reduce the power consumption by reducing the operating speed of the entire system with a time varying coefficient filter when input data sampled by a 1st clock signal are sampled by a 2nd clock signal having a 2nd sampling frequency. CONSTITUTION: Progression data according to a prescribed rule are formed as a table and it is stored in advance in a memory 102. A latch circuit 5 latches a count at a time when an output sampling clock fOUT is received and gives the count to the memory 102 as address data. The progression data stored in the address of the memory 102 are sequentially read and given to a memory 6 as address data. A time varying coefficient αn (2) is read from the memory 6 and given to a time varying coefficient filter 3. Thus, output data y(t) resulting from input data applied with prescribed product sum calculation and whose sampling frequency is converted are outputted to a switch 11 according to an output sample rate. The switch 11 is used to sample the data y(t) and the result is outputted to an output terminal 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling frequency conversion device used in various digital signal processing devices including communication devices.

[0002]

2. Description of the Related Art In a digital signal processing device for exchanging data between a plurality of circuits having different operation sampling frequencies, a sampling frequency conversion device capable of converting a sampling frequency with an arbitrary conversion ratio is required between the circuits. ，
Conventionally, this sampling frequency conversion device has a significantly high operating clock frequency when the sampling frequency conversion ratio is not a simple integer ratio, and the hardware configuration becomes very complicated, resulting in an increase in circuit scale and power consumption. Was causing problems such as an increase in As a known technique of a sampling frequency conversion device in consideration of this point, for example, as shown in Japanese Patent Laid-Open No. 4-332214, "High-speed interpolation device", a time-varying coefficient FIR (Finite Impulse Respo) is used.
An example of a sampling frequency conversion device using a (nse) filter is known. Hereinafter, this conventional example will be described with reference to FIG.

In FIG. 3, the input data applied to the input terminal 1 is first applied to one terminal of the switch 2. The switch 2 is supplied with an input sampling clock (hereinafter, clock f _in ) of frequency f / N obtained by dividing the reference clock of frequency f generated from the reference clock generator 10 by N (N is a positive integer). cage, the input data, this is sampled in accordance with the input timing of a clock f _in, it is supplied to the variable coefficient filter 3 when. Time-varying coefficient filter 3, the input data x according to the input timing of the input sampling clock f _in (input sample rate)
(T) is fetched and the internal data is sequentially updated, while an output sampling clock (hereinafter referred to as a clock) having a frequency f / M obtained by dividing the reference clock by M (M is a positive integer and M ≠ N). According to the input timing (output sample rate) of f _out ), a predetermined product-sum calculation process is performed,
The data y (t) with the sampling frequency converted again is output. On the other hand, the counter 4 updates the counter value at high speed by using the reference clock signal of the frequency f as the operation clock signal and sequentially outputs the counter value to the latch 5, but the input data x is input according to the input sample rate.
At the same time as (t) is taken in, the counter value is reset once, and immediately after the counter value is reset, counting is started and the count value is updated again. Further, the latch 5 holds the counter value at the time when the output sampling clock f _out is input, and gives the held counter value as address data to the memory 6 in which the interpolation coefficient is stored. The address data given to the memory 6, that is, the held counter value corresponds to the time from the input of data to the first output (sampling time of output data). The memory 6 reads out a predetermined interpolation coefficient stored in advance at an address designated by this address data, and gives the time-varying coefficient α (t) to the time-varying coefficient filter 3.

In the time-varying coefficient filter 3, the given time-varying coefficient α _n (t) is used to perform a predetermined sum-of-products operation on the input data, and then the output data y (t ) Is output to the switch 11 according to the output sample rate. An output sampling clock f _out is supplied to the switch 11, and similarly, the output data y (t) is sampled in accordance with the above output sample rate,
Output to the output terminal 12. In this way, the sampling frequency is converted.

[0005]

In the above-mentioned prior art, as described above, even when the ratio of the input / output sampling frequencies is not a simple integer ratio, it operates at a low speed with a relatively simple structure. Implements a sampling frequency converter. However, since it is necessary to measure the time from the input of the data signal to the first output, that is, the sampling time of the output data with high accuracy, the clocking means still needs a high-speed counting operation. However, considering the sampling frequency converter as a whole, there was a problem that the operating frequency could not be reduced. Further, in a system in which the input and output sampling clocks f _in and f _out are asynchronous, when the timings of the sampling clocks are very close to each other, the data update operation and the product-sum operation operation in the time-varying coefficient filter are performed. However, there is a risk that incorrect data may be output as a result of incorrect ordering depending on the state of the device used. The present inventor has studied a sampling frequency conversion apparatus, when the sampling clock f _in and f _out of the input and output is in the synchronization state, samples of the output data of the address data supplied to the memory 6 that stores the time-varying coefficients It was discovered that the time series of each sampling time gives a sequence according to a predetermined rule, and correct sampling time data can be obtained without requiring a high-speed counting operation.

A first object of the present invention is to reduce the operating clock frequency of the clocking means for measuring the sampling time of output data in the sampling frequency converter, and thus reduce the operating clock frequency of the entire sampling frequency converter. Especially. A second object of the present invention is to provide a sampling frequency conversion device capable of always performing data update operation and product-sum operation at correct timing even in a system in which input / output sampling clocks are given in an asynchronous state. To provide.

[0007]

In order to achieve the above first object, the present invention has a second sampling frequency for input data sampled with a first clock signal having a first sampling frequency. A time-varying coefficient filter for converting the output data resampled by the second clock signal, and a clocking means for measuring the sampling time of the second clock signal given an operating clock signal of a predetermined frequency,
In the sampling frequency conversion device having a first storage means for inputting the sampling time data given from the time measuring means as address data and giving a coefficient determined by the sampling time to the time varying coefficient filter, A second clock means for using the operation clock signal as the second clock signal, the second clock means storing the address data to be supplied to the first memory means between the time counting means and the first storage means. The storage means is provided. Further, in order to achieve the above-mentioned second object, when the proximity of the input and output sampling clocks is detected, the correct operation order can be determined from the slight time difference between the clocks.
An edge detection circuit that outputs a detection signal when a collision between the first clock signal and the second clock signal is detected, and input processing according to a predetermined ordering when the detection signal is supplied to the edge detection circuit. And a sequential circuit for performing the output operation and the output processing operation.

[0008]

As a result, it is not necessary to operate the counter for determining the coefficient value of the time-varying coefficient filter at high speed, and the operating speed of the entire sampling frequency converter can be reduced, so that high stability and low power consumption can be achieved. ， Applicable to higher sampling frequency. Further, in a system in which the input and output sampling clocks are asynchronous, the data processing is always performed in the correct order and the correct operation result can be obtained, so that a highly accurate and highly stable sampling frequency conversion device can be realized.

[0009]

An embodiment of the present invention will be described in detail below with reference to FIG. The present embodiment is an example of a sampling frequency conversion device suitable for a system _in which input and output sampling clocks f _in and f _out are applied in a synchronized state. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In FIG. 1, an input terminal 1 is connected to an output terminal 12 via a switch 2, a time-varying coefficient filter 3, and a switch 11. On the other hand, the reference clock generator 10 is connected to the switch 2 via the N frequency divider 8 and to the switch 11, the counter 101 and the latch 5 via the M frequency divider 9.
The counter 101 is connected to the time-varying coefficient filter 3 via the latch 5, the memory 102, and the memory 6. The operation of this embodiment will be described below.

The input data applied to the input terminal 1 is first applied to one terminal of the switch 2. This switch 2 has a frequency f generated by the reference clock generator 10.
The reference clock is given a N divider frequencies f / N becomes the input sampling clock f _in, the input data, this is sampled in accordance with the input timing of a clock f _in, is supplied to the variable coefficient filter 3 when . The time-varying coefficient filter 3 takes _in the input data x (t) according to the input timing (input sample rate) of the input sampling clock fin, sequentially shifts the already taken in past data by the number of taps, and internally Data is sequentially updated, while predetermined product-sum calculation processing is performed in accordance with the input timing (output sample rate) of the output sampling ring clock f _out having a frequency f / M obtained by dividing the reference clock by M to convert the sampling frequency. The re-produced data y (t) is output. On the other hand, the counter 101
Is an output sampling clock f _out having a frequency f / M obtained by dividing the reference clock generated by the reference clock generator 10 by M by the M divider 9 as an operation clock signal. The counter 101 is an N-ary counter, takes a counter value from 0 to (N-1), and sequentially outputs the counter value to the latch 5. When the input / output sampling clock signals f _in and f _out are synchronized, the address data given to the memory 6 is 0 to (N− It is a number sequence that takes values up to 1).

Here, a sequence of numbers that complies with this predetermined rule will be specifically described. In this embodiment, the ratio of the frequency of the reference clock f and the input sampling clock f _in the
f / f _in = N, and the frequency ratio between the reference clock and the output sampling clock f _out is f / f _out = M (N and M are positive integers, N> M). The counter value at the sampling time of the output data is given by the remainder obtained by adding M to the counter value at the time of the previous output and dividing by N, and the sequence of elements N is repeated. As a specific example, f
_in = 48 kHz, f _out = 76 kHz, f = 912 kHz
z (N = 19, M = 12) and mod (k, m) is k
Is the remainder divided by m, and the count value of the first output time is 0, 0 → 0 + 12 = 12 → 12 + 12 = 24, mod (24,19) = 5 → 5 + 12 = 17
→ 17 + 12 = 29, mod (29,19) = 10 → 10 + 12 = 22, mod (22,
19) = 3 → 3 + 12 = 15 → 15 + 12 = 27, mod (27,19) = 8 → 8 + 12
= 20, mod (20,19) = 1 → 1 + 12 = 13 → 13 + 12 = 25, mod (25,1
9) = 6 → 6 + 12 = 18 → 18 + 12 = 30, mod (30,19) = 11 → 1
1 + 12 = 23, mod (23,19) = 4 → 4 + 12 = 16 →
16 + 12 = 28, mod (28,19) = 9 → 9 + 12 = 21, mod (21,19) = 2
→ 2 + 12 = 14, → 14 + 12 = 26, mod (26,19) =
7 → 7 + 12 = 19, mod (19,19) = 0, and the sequence is {0,12,5,17,10,3,15,8,1,13,6,18,11,4,
16,9,2,14,7}.

In the present embodiment, as described above, the sequence data in accordance with the predetermined rule is tabulated and stored in the memory 102.
It is stored in advance. On the other hand, the latch circuit 5 receives the time when the output sampling clock f _out is input (that is,
The counter value at the sampling time of the output data) is held, and the held count value is given to the memory 102 as address data. The memory 102 sequentially reads out the sequence data stored at the address, and outputs this sequence data. It is given to the memory 6 as address data. Further, the memory 6 stores the time-varying coefficient α stored at the address.
_n (τ) is read out and given to the time-varying coefficient filter 3.
The time-varying coefficient filter 3 uses the given time-varying coefficient α
Output data y obtained by performing a predetermined multiply-accumulate operation on the input data using _n (t) and then converting the sampling frequency
(T) is output to the switch 11 according to the output sample rate. The output sampling clock f _out is supplied to the switch 11, and the output data y (t) is sampled according to the output sample rate and output to the output terminal 12. In this way, the sampling frequency is converted.

In the embodiment described above, the memory 10
When the count value given to 2 and the value of the time-varying coefficient α _n (τ) are the same and have a one-to-one correspondence, the memory 102 can be deleted and the configuration can be simplified. In this case, the counter value of the counter 101 at the time when the output sampling clock f _out is input is temporarily held by the latch 5, and the held count value is directly given to the memory 6 as address data. The stored time-varying coefficient α _n (τ) may be supplied to the time-varying coefficient filter 3.

Another embodiment of the present invention suitable for a system in which input / output sampling clocks are asynchronously applied will be described with reference to FIG. In FIG. 2, the input terminal 1 is connected to the output terminal 12 via the switch 2, the time-varying coefficient filter 3, and the switch 11. On the other hand, the input sampling clock input terminal 103 is connected to the switch 2 and the counter 108, and is connected to the time-varying coefficient filter 3 via the edge detection unit 104 and the sequential circuit 105. The output sampling clock input terminal 106 is connected to the time-varying coefficient filter 3 via the latch 5 and the memory 6,
On the other hand, the switch 11 and the edge detection unit 104 are connected. Further, the counter clock input terminal 107 is connected to the counter 108. Hereinafter, this operation will be described.

An input sampling clock f _in , an output sampling clock f _out and a counter clock (hereinafter,
f _CNT ) is an independent clock. The counter clock f _CNT is input from the counter clock input terminal 107 and sequentially increments the value of the counter 108. On the other hand, when the input sampling clock f _in is input from the input sampling clock input terminal 13, the input from the input terminal 1 through the switch 2 data x (t) it is taken to the time-varying coefficient filter 3, time-varying coefficient filter 3 The data is sequentially shifted inside the. Also, count 1
In 08, each time the input sampling clock f _in is input, resets the count value. Further, the count value of the counter 108 is held in the latch 5 by the output sampling clock f _out input from the output sampling clock input terminal 106, the count value τ is given to the memory 6 as address data, and the time change from the memory 6 is performed. The coefficient α _n (τ) is read out and given to the time-varying coefficient filter 3. The time-varying coefficient filter 3 performs a predetermined product-sum calculation (interpolation process) using the given time-varying coefficient.

Normally, the system clock at the time of performing the interpolation processing is operated using a frequency higher than the input sampling clock f _in and the output sampling clock f _out , but the rising edges of the input sampling clock and the output sampling clock are It may occur at a time interval shorter than the cycle of the system clock. The operation at this time will be described with reference to FIG. As an example, a time-varying coefficient filter is a general-purpose DSP (Digital Signal Pros).
FIG. 5 shows the relationship among the input sampling clock f _in , the output sampling clock f _out , and the system clock SCLK when the hardware is configured by using (essor). Normally, when a plurality of processes are simultaneously performed by using the DSP, it is often realized by using the interrupt process, and the time required for the DSP to start the interrupt process from the edge of the pulse that activates each interrupt process is It is defined by the number of system clocks. In this embodiment, it is assumed that 3 system clocks are required from the interrupt pulse edge to the start of interrupt processing. As shown in FIG. 5, even if an interrupt occurs due to the input sampling clock within one system clock after the interrupt occurs due to the output sampling clock at a certain time t1, even a slight amount is required to perform correct interpolation processing. It is necessary to perform the process of the one in which the interrupt occurs first. On the other hand, usually
In interrupt processing such as DSP, priority is set as a system, and when interrupt processing occurs at the same time, processing with lower priority is made to wait and processing with higher priority is performed first. . Here, when the higher priority interrupt pulse f _in corresponding to the input sampling clock assigned, despite the edge of the interrupt pulse f _out corresponding to the output sampling pulse is fallen previously, DSP However, since it is considered that an interrupt occurs at the same time and the data input process is performed first, a correct operation result cannot be obtained.

In the present invention, as shown in FIG. 2, the edge detection unit 104 detects which edge of the input sampling clock f _in and the output sampling clock f _out has fallen first, and the difference is 3 system clocks. When it is within the range, by delaying the interrupt pulse that has fallen later in the sequential circuit 15, the processing in the time-varying coefficient filter 3 is controlled to be performed in the correct order.

An application example of the present invention will be described with reference to FIG.
FIG. 4 is a block diagram of a stereo FM broadcast modulator using the present invention. The digital audio signal source 18 is
The sampling frequency converter 19 is connected to the digital stereo modulator 20. Further, the digital stereo modulator 20 is connected to another sampling frequency converter 21, and is connected to the modulated wave output terminal 24 via the digital FM modulator 22 and the DA converter 23. Hereinafter, this operation will be described. The sampling frequency of the digital audio signal source 18 varies depending on the type of signal source such as DAT (digital audio tape recorder) or CD (compact disk). on the other hand,
Since the digital stereo modulation unit 20 performs the insertion of the pilot signal of 19 kHz, the balanced modulation of 38 kHz, etc., the processing speed is preferably based on n × 19 kHz (n; positive integer). Therefore, the sampling frequency of the digital audio signal source 18 is converted into a sampling frequency of n × 19 kHz in the sampling frequency converter 19 and converted into a sampling frequency that can be easily processed by the digital stereo modulator 20. Furthermore, the output is sampled by the sampling frequency converter 21,
The conversion rate of the DA converter 23 is converted to the FM modulation section 22.
After the FM modulation processing is performed by the, the DA converter 23 converts the signal into an analog signal, and the FM-modulated modulated wave is output from the modulated wave output terminal 24.

[0019]

As described above, according to the present invention, when the input / output sampling clocks are synchronized, a high-speed counter is not required, and the input sampling clock or the output sampling clock, whichever is faster, is used. Since they can be operated at the same processing speed, low power consumption and low price are possible. Moreover, since a high-speed counter is not required, it can be applied to conversion processing of higher sampling frequency. Further, in a system in which input / output sampling clocks are given in an asynchronous state, interpolation processing is always performed without erroneous processing procedures, so that the sampling frequency can be converted to a required frequency with high accuracy. Further, by applying the present invention, it is possible to speed up, improve accuracy, reduce power consumption, and reduce the cost of all communication devices for voice and image transmission and data transmission that require digital signal processing. Becomes
Specifically, as application examples of the present invention, in addition to the above-described application examples, commercial communication devices, wireless communication devices such as digital cellular phones, wired communication devices such as modems, etc. are currently being digitized, or in the future. It can be applied to all communication devices in which digitization is promoted.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional technique.

FIG. 4 is a block diagram showing an application example of the present invention.

FIG. 5 is a timing diagram showing the relationship between the operation clocks of the time-varying coefficient filter.

[Explanation of symbols]

1 ... Input terminal 2 ... Switch 3 ... Time-varying coefficient filter 4 ... Counter 5 ... Latch 6 ... Memory 8 ... N divider 9 ... M divider 10 ...
Reference clock generator 11 ... Switch 12 ... Output terminal 101 ... Counter 102 ... Memory 103 ... Input sampling clock input terminal 104
... edge detection unit 105 ... sequential circuit 106 ... output sampling clock input terminal 107 ... counter clock input terminal 108
... Counter 18 ... Digital audio signal source 19 ...
Sampling frequency converter 20 ... Digital stereo modulator 21 ... Sampling frequency converter 22 ... Digital FM modulator
23 ... DA converter 24 ... modulated wave output terminal x (t) ... input before sampling frequency converted data signal y (t) ... output data signals after the sampling frequency conversion alpha _n (tau) ... time-varying coefficient f _in ... Input sampling clock f _out ... Output sampling clock SCLK ... System clock of time-varying coefficient filter

Claims (4)

[Claims] 1. A first having a first sampling frequency
A time-varying coefficient filter for converting the input data sampled with the clock signal into the output data resampled with the second clock signal having the second sampling frequency,
Clocking means for measuring the sampling time of the second clock signal given an operating clock signal of a predetermined frequency, and sampling time data given from the clocking means are inputted as address data and a coefficient determined by the sampling time In the sampling frequency conversion device for providing the time-varying coefficient filter to the time-varying coefficient filter, the clocking means is a clocking means that uses an operating clock signal as the second clock signal. A sampling frequency conversion device comprising: a second storage means for storing the address data given to the first storage means, between the first storage means. 2. A first having a first sampling frequency
A time-varying coefficient filter for converting the input data sampled with the clock signal into the output data resampled with the second clock signal having the second sampling frequency,
Clocking means for measuring the sampling time of the second clock signal given an operating clock signal of a predetermined frequency, and sampling time data given from the clocking means are inputted as address data and a coefficient determined by the sampling time In the sampling frequency conversion device, the sampling means is provided with a first storage means for supplying the time-varying coefficient filter to the time-varying coefficient filter, wherein the clocking means is a clocking means using an operation clock signal as the second clock signal. Frequency converter. 3. A first having a first sampling frequency
A time-varying coefficient filter for converting the input data sampled with the clock signal into the output data resampled with the second clock signal having the second sampling frequency,
Clocking means for measuring the sampling time of the second clock signal given an operating clock signal of a predetermined frequency, and sampling time data given from the clocking means are inputted as address data and a coefficient determined by the sampling time Is provided to the time-varying coefficient filter, and the first storage means is provided.
An edge detection circuit that outputs a detection signal when a collision between the first clock signal and the second clock signal is detected in a sampling frequency conversion device in a system in which the clock signal and the second clock signal are asynchronous with each other; A sampling frequency conversion device, comprising: a sequential circuit connected to the edge detection circuit and controlling a data processing operation in the time-varying coefficient filter according to a predetermined ordering when the detection signal is given. 4. A communication device comprising the sampling frequency conversion device according to claim 1. Description: