WO2014030384A1

WO2014030384A1 - Sampling rate conversion device

Info

Publication number: WO2014030384A1
Application number: PCT/JP2013/060606
Authority: WO
Inventors: 山田　恭裕; 雄一郎小池
Original assignee: Ｎｔｔエレクトロニクス株式会社
Priority date: 2012-08-23
Filing date: 2013-04-08
Publication date: 2014-02-27
Also published as: BR112015003618B1; EP2890008A4; EP2890008A1; US9214921B2; US20150222248A1; JP5573901B2; BR112015003618A2; JP2014042204A; EP2890008B1

Abstract

According to the present invention, a positional coordinate difference calculator (5) calculates the positional coordinate difference between the positional coordinates of an output digital signal and the positional coordinates of an input digital signal proximal thereto. An FIR coefficient memory (9) stores the FIR coefficient of an FIR-LPF having the property of blocking frequency components of at least half the output sampling rate. When the positional coordinate difference is inputted, the FIR coefficient memory (9) outputs an FIR coefficient corresponding to the positional coordinate difference between the output digital signal and a set number of input digital signals present in the vicinity of the positional coordinates of the output digital signal. A parallel FIR computing unit (3) performs an FIR-LPF interpolation computation using the set number of input digital signals and the FIR coefficient, and thereby calculates the output digital signal.

Description

Sampling rate converter

The present invention relates to a sampling rate conversion device used for a digital image size conversion device, digital audio, or the like.

A sampling rate converter is used to convert an input digital signal sampled at the input sampling rate into an output digital signal sampled at the output sampling rate. In the conventional sampling rate conversion apparatus, first, the ratio of the input sampling rate R1 and the output sampling rate R2 is R1: R2 = A · M: A · N = M: N (where A is a constant, M and N Are converted to sampling rates R3 = R1 · N = R2 · M, which is the least common multiple of the output sampling rate R2 (upsample). Next, an output digital signal is obtained by taking out (down-sampling) a sample that matches the output sampling rate R2 from a sequence of N times the sample value of the input digital signal.

FIG. 9 is a diagram for explaining a conventional sampling rate conversion method. A circle in the figure indicates a digital signal having a sampling rate R3. Among them, a circle with hatched lines indicates an input digital signal at the input sampling rate R1, a bold circle indicates an output digital signal at the output sampling rate R2, and a thin white circle indicates other than the input / output digital signal.

These digital signals of sampling rate R3 are calculated from the input digital signal (upsampling). At that time, an interpolation value calculation is performed using an FIR-LPF (Finite Impulse Response Low Pass Filter) having a characteristic of blocking a frequency component that is 1/2 or more of the output sampling rate R2. Then, an output digital signal having an output sampling rate R2 is extracted from the digital signal having a sampling rate R3 (down sampling).

Here, the case where the sampling rate is reduced is called down-sampling. In the case of down-sampling, FIR-LPF is used to block the high frequency component of the input and suppress aliasing noise due to a decrease in sampling rate. On the other hand, the case where the sampling rate is increased is called up-sampling. In the case of up-sampling, it is not necessary to block the high frequency component of the input, but FIR-LPF is used to calculate an interpolation value at a position different from the input digital signal.

FIG. 10 is a diagram showing an impulse response of the FIR-LPF. The impulse response of the filter is expressed by a time function obtained by inverse Fourier transform of a predetermined filter characteristic. When the impulse input is input at time 0, the impulse response waveform exists before and after time 0. In the interpolation value calculation, an output digital signal at time 0 is calculated using an input digital signal in the existence range of the impulse response waveform. In general, the impulse response waveform continues for a long time, but in order to make it practical, the impulse response waveform is cut to a certain finite length to perform signal processing.

In an actual device, the impulse response start time (negative time) is set to 0 or a positive number. Specifically, the impulse response start time -T is converted to 0, and the original time 0 is set to T to perform sampling rate conversion. In digital signal processing, such a time shift process can be performed by using a memory (shift register).

Japanese Unexamined Patent Publication No. 8-84048

Conventionally, a sample sampled at a high sampling rate R3 in which both samples of the sampling rates R1 and R2 are present is generated, and a sample string at the sampling rate R2 is extracted therefrom. For example, if R1 = 15 MHz and R2 = 16 MHz, the sampling rate R3 in which both samples exist is R3 = 15 × 16 MHz = 240 MHz. An apparatus using such a very high sampling rate R3 has been difficult to realize with inexpensive semiconductor technology. Furthermore, the design of a digital circuit having three operation clock frequencies corresponding to the three sampling rates R1, R2, and R3 is complicated and difficult. In addition, a general-purpose sampling rate conversion apparatus that can cope with an arbitrary input / output sampling rate (that is, M and N are arbitrary) is desired.

In order to avoid the use of a high sampling rate R3, it has been proposed to mount a plurality of FIR operation units operating at two sampling rates R1 and R2 in parallel (see, for example, Patent Document 1). However, when a plurality of FIR operation units are mounted in parallel, there is a problem that the circuit scale becomes very large.

The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain an inexpensive and general-purpose sampling rate conversion apparatus with a small circuit scale.

A sampling rate conversion apparatus according to the present invention is a sampling rate conversion apparatus that converts an input digital signal sampled at an input sampling rate into an output digital signal sampled at an output sampling rate. A position coordinate difference calculation unit for calculating a position coordinate difference Dk between the position coordinate of the input digital signal close to the position coordinate Tk of the digital signal Yk and the position coordinate Tk; and a frequency component of 1/2 or more of the output sampling rate. Stores the FIR coefficient F (z) of the FIR-LPF when the position coordinate of the impulse input inputted to the FIR-LPF (Finite Impulse Response Low Pass Filter) having the cutoff characteristic is set to z = 0. When the coordinate difference Dk is input, a certain number (p) of input digital signals Xk (q) existing in the vicinity of the position coordinate Tk of the output digital signal Yk. The position coordinates are Zk (q), (q = 1, 2,..., P), and the FIR coefficient F (Zk (q) −Tk) corresponding to the position coordinate difference (Zk (q) −Tk) is output. FIR coefficient memory, Yk = F (Zk (1) −Tk) * Xk (1) + F (Zk (2) −Tk) * Xk (2) +... + F (Zk (p) −Tk) * Xk (p ) To obtain the output digital signal Yk.

According to the present invention, it is possible to obtain an inexpensive and general-purpose sampling rate conversion apparatus with a small circuit scale.

It is a block diagram which shows the sampling rate conversion apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the parallel FIR calculator which concerns on Embodiment 1 of this invention. It is a figure for demonstrating briefly the principle of FIR-LPF interpolation calculation. It is a figure which shows the positional relationship of an input digital signal and an output digital signal. It is a block diagram which shows the sampling rate conversion apparatus which concerns on Embodiment 2 of this invention. It is a block diagram which shows the sampling rate converter which concerns on Embodiment 3 of this invention. It is a block diagram which shows the serial FIR calculator which concerns on Embodiment 3 of this invention. It is a timing chart which shows operation | movement of the serial FIR calculator which concerns on Embodiment 3 of this invention. It is a figure for demonstrating the conventional sampling rate conversion method. It is a figure which shows the impulse response of FIR-LPF.

A sampling rate conversion apparatus according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a sampling rate conversion apparatus according to Embodiment 1 of the present invention. The apparatus converts an input digital signal sampled at an input sampling rate into an output digital signal sampled at an output sampling rate. Further, the present embodiment aims to convert the sampling rate of the image, and geometrically converts the number of samples in a predetermined area on the screen. Therefore, the sampling rate conversion in this case means two sampling rate conversions for both the horizontal and vertical coordinate axes in the two-dimensional space coordinates.

The apparatus of this embodiment operates with a processing clock having a frequency higher than the input / output sampling rate. Note that in the case of an HD60P image (1920 × 1080 × 60 / sec), the actual clock frequency is about 148.5 MHz. The FIFO memory 1 temporarily stores the input digital signal and then supplies it to the shift register 2 in synchronization with the processing clock. The parallel FIR calculator 3 converts the input digital signal supplied from the shift register 2 into an output digital signal. The FIFO memory 4 temporarily stores the output digital signal and then outputs it in synchronization with the output clock.

The position coordinate difference calculation unit 5 calculates a position coordinate difference Dk between the position coordinate of the input digital signal close to the position coordinate Tk of the kth output digital signal Yk and the position coordinate Tk in synchronization with the processing clock. Here, “an input digital signal close to the position coordinate Tk” means (1) an input digital signal whose position coordinate difference from the position coordinate Tk is 0 or the closest positive number, and (2) a position coordinate with the position coordinate Tk. The closest input digital signal with a difference of 0 or a negative number, or (3) the closest input digital signal obtained by evaluating the absolute value of the position coordinate difference from the position coordinate Tk. Depending on which criterion is adopted, the target input digital signal may be shifted by one input sample period. Specifically, the position coordinate difference calculation unit 5 includes an input integrator 6, an output integrator 7, and an integrated value comparator 8 that controls them. Let C be a constant, M and N be mutually prime positive integers, the sampling period of the input digital signal be C · M, and the sampling period of the output digital signal be C · N. The input integrator 6 integrates M and outputs an integrated value Sm. The output integrator 7 integrates N and outputs an integrated value Sn. The integrated value comparator 8 integrates M in the input integrator 6 when Sm−Sn ≦ N, integrates N into the output integrator 7 when Sn−Sm ≦ M, and sets N into the output integrator 7. Sn-Sm at the time of integration is output as the position coordinate difference Dk.

In this embodiment, it is assumed that the input cycle M = 3 and the output cycle N = 8. The values of M and N are used for sampling rate conversion processing in the horizontal direction when converting an HD image (1920 × 1088) into an SD image (720 × 480). In the case of the vertical direction, M = 4 and N = 9.

The FIR coefficient memory 9 sets z = 0 as the position coordinate of the impulse input inputted to the FIR-LPF (Finite Impulse Response Low Pass Filter) having a characteristic of cutting off frequency components of 1/2 or more of the output sampling rate. The RAM (Random Access Memory) or ROM (Read Only Memory) storing the FIR coefficient F (z) of the FIR-LPF in this case. When the position coordinate difference Dk = Sn−Sm is input from the position coordinate difference calculation unit 5, the FIR coefficient memory 9 stores a certain number (p) of the output digital signal Yk that exists in the vicinity of the position coordinate Tk. Assuming that the position coordinates of the input digital signal Xk (q) are Zk (q), (q = 1, 2,..., P), the FIR coefficient F (Zk ( q) -Tk) is output.

For this purpose, the FIR coefficient memory 9 stores a set of FIR coefficients for each type of position coordinate difference Dk, and selects and outputs a set of FIR coefficients according to the input position coordinate difference Dk. Since there are M output cycles N in the period of the least common multiple M · N of the input cycle M and the output cycle N, there are M types of position coordinate differences Dk, and M sets of FIR coefficients are required.

When the parallel FIR calculator 3 is supplied with the input digital signal from the shift register 2 and is supplied with the FIR coefficient from the FIR coefficient memory 9, Yk = F (Zk (1) −Tk) * Xk (1) + F (Zk (2) −Tk) * Xk (2) +... + F (Zk (p) −Tk) * Xk (p) is calculated to obtain the output digital signal Yk (FIR-LPF interpolation calculation).

FIG. 2 is a block diagram showing the parallel FIR computing unit according to Embodiment 1 of the present invention. This FIR computing unit is an 8-Tap parallel FIR computing unit that performs a parallel product-sum operation using eight input digital signals to obtain one output digital signal.

Each time the input accumulator 6 accumulates M in synchronization with the processing clock, one sample of the input digital signal is sequentially input to the shift registers R0 to R7. When predetermined input digital signals necessary for the operation are input to the shift registers R0 to R7, the input digital signals are output in parallel from the shift registers R0 to R7 to the multipliers A0 to An, and the corresponding FIR coefficients are obtained. The data is output in parallel from the FIR coefficient memory 9 to the multipliers A0 to A7, and multiplication is performed by the multipliers A0 to An. The outputs of the multipliers A0 to A7 are added by the product-sum circuit 10 to calculate an output digital signal.

FIG. 3 is a diagram for briefly explaining the principle of FIR-LPF interpolation calculation. In the figure, circles with hatched lines indicate input digital signals, and white circles indicate output digital signals. The input period M is 4 and the output period N is 5. An output digital signal Yk present at a position Tk that does not exist in the input digital signal is interpolated and calculated from the surrounding input digital signal Xk (q). In general, since the influence of the peripheral input digital signal Xk (q) decreases as the distance from the output digital signal Yk increases, the FIR coefficient F (Zk (q) −Tk) is used. In the case of an image signal, about 30 input digital signals around the output digital signal Yk (15 before and after) are used. In the case of audio, high accuracy is required, and about 50 to 100 peripheral input digital signals are used. The more input digital signals are used, the better the accuracy of the interpolation calculation.

FIG. 4 is a diagram showing the positional relationship between the input digital signal and the output digital signal. The waveform in the figure is an impulse response waveform of the FIR filter. The center of the waveform is set to the position Yk of each output digital signal, and the output digital signal is calculated by FIR-LPF interpolation calculation using the eight input digital signals around it. When the eight input digital signals are X0 to X7 and the amplitude of the impulse response waveform at the position of each input digital signal is F0 to F7, the output digital signal Y is Y = ΣXj · Fj, (j = 0 to 7) Is calculated by When the input / output cycle ratio M is N, the positional relationship of the input digital signal with respect to the output digital signal is M types of repetition. In FIG. 4, since the input / output cycle ratio M: N = 3: 8, the positional relationship is three types of repetition.

Incidentally, an FIR filter having an impulse response waveform that is symmetric about the impulse input position is used. This is to eliminate the waveform distortion by setting the group delay characteristic (change in delay for each frequency) to be flat (uniform). If a symmetric impulse response waveform is used, the FIR coefficient becomes the same value at a symmetrical position with respect to the center, so that the number of FIR coefficients can be halved. For example, when the position coordinate difference Dk, which is a symmetric positional relationship, is 1, and when the position coordinate difference Dk is (M−1), the FIR coefficients are the same numerical values. When the position coordinate difference Dk is 0, the FIR coefficient itself is symmetric.

When Sm and Sn are increased, the number of bits in the position coordinate difference calculation unit 5 such as a register that holds Sm and Sn, an adder / subtractor, and a size determination unit is increased. In order to prevent this, the initial value detection reset unit 11 resets Sm and Sn to the initial values when the difference between Sm and Sn matches the initial value. Note that Sm and Sn are also reset to initial values when a reset signal is input from the outside.

Table 1 shows the transition of the integrated values Sm and Sn when the initial value detection reset unit 11 is not operated.

The initial values of Sm and Sn are set to substantially coincide with each other. Here, the initial values are Sm = 0 and Sn = 2. Therefore, since it corresponds to Sm−Sn ≦ N and Sn−Sm ≦ M, the input accumulator 6 accumulates M and the output integrator 7 accumulates N at the next clock. Modulo (Sn-Sm, M) is a remainder (0 to M-1) obtained by dividing Sn-Sm by M.

In the first clock, M = 3 is accumulated in Sm, N = 8 is accumulated in Sn, and Sm = 3 and Sn = 10. The input digital signal is transferred and shifted simultaneously with adding M to Sm, and the output digital signal is calculated simultaneously with adding N to Sn. At this time, Sn−Sm = 7 corresponding to the position coordinate difference Dk is 1 in Modulo (Sn−Sm, M). Modulo the case of ^{M ≦ 2 B (Sn-Sm} , M) are distinguishable by the lower B bits Sn-Sm. Here Modulo for an M ^{<2 2} is (7,3) can be 2-bit representation, the lower 2-bit number Sn-Sm = 7 is three. Therefore, the set of FIR coefficients when the position coordinate difference Dk = Sn−Sm is 1 in Modulo may be stored in the address 3 of the FIR coefficient memory 9. Thereby, the value of Sn-Sm can be made a narrow numerical range by modulo calculation, and the number of bits expressing the value of M can be made to correspond to the numerical value after the modulo calculation.

* The second and third clocks integrate M, so the input digital signal is transferred and shifted, but there is no N accumulation, so the output digital signal is not calculated. Since M <N, M is always accumulated at each clock.

∙ Since there is an integration of N during the fourth clock, calculate the output digital signal. At this time, Sn-Sm = 6 becomes 0 in Modulo (Sn-Sm, M). The lower 2-bit value of Sn−Sm = 6 is 2. Therefore, the set of FIR coefficients when the position coordinate difference Dk = Sn−Sm is 0 in Modulo may be stored in the address 2 of the FIR coefficient memory 9.

∙ Transfer shift of input digital signal at 5th clock, but do not calculate output digital signal. The output digital signal is calculated at the sixth clock. At this time, Sn-Sm = 8 becomes 2 in Modulo (Sn-Sm, M). The numerical value of the lower 2 bits of Sn−Sm = 8 is 0. Therefore, the set of FIR coefficients when the position coordinate difference Dk = Sn−Sm is 2 in Modulo may be stored at address 0 of the FIR coefficient memory 9.

∙ Transfers the input digital signal at the seventh and eighth clocks, but does not calculate the output digital signal. The output digital signal is calculated at the ninth clock. At this time, Sn−Sm = 7, and the operation is the same as in the first clock. Thereafter, the above operation is repeated.

Sn-Sm indicates the difference in the position of the input / output digital signal. By setting the integration conditions and initial values of Sm and Sn, it is possible to set the position coordinate difference between the input and output digital signals as to how many clocks the output digital signal is calculated. In the above example, the position coordinate difference Sn-Sm at the time of output sample calculation is 6-8, but if the input digital signal is shifted by 2 samples (2 × M = 6), Sn-Sm will be 0-2. This shift can be performed by a circuit configuration. Alternatively, the FIR-LPF coefficient value may be shifted by two samples. Alternatively, if the initial values are Sm = 3 and Sn = 0, Sn−Sm becomes a numerical value in the range of 0 to 2, and therefore Sn−Sm itself can be used as the address of the FIR coefficient memory 9.

Using the fact that the same operation is periodically repeated according to the values of M and N as described above, the initial value detection reset unit 11 resets Sm and Sn to the initial values (reinitialization) at a possible timing. ) As a result, the hardware scale can be reduced. Table 2 shows the transition of the integrated values Sm and Sn when the initial value detection reset unit 11 is operated.

The operation from the initialization operation to the seventh clock is the same as Table 1. Since Sn−Sm coincides with the initial value 2 at the eighth clock, the initial value detection reset unit 11 resets Sm and Sn to the initial values Sm = 0 and Sn = 2. In the case of a clock synchronous operation system, Sn-Sm = 5 one clock before when Sn-Sm = 2 is detected, and synchronous re-reset (synchronization re-initialization) may be performed at the next clock.

The operation from the 9th to the 15th clock is exactly the same as the operation from the 1st to the 7th clock. Reset again at the 16th clock. The operation from the 17th clock to the 23rd clock is exactly the same as the operation from the 1st clock to the 7th clock. Thereafter, the above operation is repeated.

For example, when converting an HD image into an SD image, the horizontal period ratio is M: N = 3: 8, and the range of values of Sm and Sn is about 0 to 1920 × 3 = 0 to 720 × 8 = 0 to 5760. For this reason, a 13-bit register, an adder / subtracter, a magnitude determination device, and the like are required when the above reset control is not performed. On the other hand, when the above reset control is performed, the maximum value of the integrated values Sm and Sn is 26. Therefore, a register, an adder / subtracter, a magnitude determination device, and the like can be configured with 5 bits.

As described above, in the present embodiment, the position coordinates of the input digital signal close to the position coordinates of the output digital signal are specified. Based on the position coordinates and the input sampling rate, the position coordinates of a certain number of input digital signals to be used in the FIR-LPF can be obtained. An output digital signal can be calculated by reading out FIR coefficients to be applied to those input digital signals from the memory and performing FIR-LPF interpolation calculation.

In order to perform such processing, the present embodiment can operate at an arbitrary clock frequency that is not related to the input / output sampling rate in principle. Therefore, it is general purpose because it can cope with an arbitrary input / output sampling rate (that is, M and N are arbitrary). Conventionally, the sampling rate of the least common multiple of the input sampling rate and the output sampling rate has been used, but in the present embodiment, the use of such a high sampling rate can be avoided. However, in order to prevent a delay in operation, it is necessary to use the clock frequency of the higher one of the input sampling rate and the output sampling rate, or one type of clock frequency higher than both.

In addition, the conventional apparatus operates at three clock frequencies, but the apparatus of the present embodiment can operate at one clock frequency. For this reason, the sampling rate conversion apparatus according to the present embodiment can be realized by an inexpensive semiconductor technology.

Also, as a prior art, in order to avoid the use of a high sampling rate, one in which a plurality of FIR operation units are mounted in parallel has been proposed, but there is a problem that the circuit scale becomes very large. On the other hand, in this embodiment, since such a configuration is not necessary, the circuit scale can be reduced.

Further, in the present embodiment, the magnitude relationship between Sm and Sn is determined, M is added to Sm so as to maintain a state where Sm and Sn substantially match, N is added to Sn, and the input / output digital signal is Calculate the positional relationship. Thereby, the position coordinate of the input digital signal close to the position coordinate of the output digital signal can be easily specified.

In addition, the reset control by the initial value detection reset unit 11 can reduce the number of bits of the register, the adder / subtracter, the size determination unit, and the like.

It should be noted that there is a region where there is no input digital signal for performing FIR calculation at the edge of the image. In this case, the pixels at the edge of the image are copied and the image is expanded to the outside of the image (the right side at the right end, the left side at the left end, the upper side at the upper end, the lower side at the lower end), and the FIR calculation is performed. For example, in the case of an 8-Tap FIR calculation, the number of Taps / 2 = 4 samples of pixels is copied and expanded at the edge of the image. Therefore, in FIG. 4, X1 to X4 are actually copies of X5. When the parallel FIR computing unit 3 is an A-Tap filter (A product-sum), the calculation of the output digital signal is started after A input digital signals are first transferred to the shift register 2. Half of the A input digital signals are copies of samples at the edge of the image.

In this embodiment, the input integrator 6 adds M to Sm when Sm−Sn ≦ N, and the output integrator 7 adds N to Sn when Sn−Sm ≦ M. In this case, the difference between Sn and Sm is in the range of 0 to N-1. As another integration control method, the input integrator 6 always integrates M when M <N. If N is an even number, Sm + N / 2 ≧ Sn> Sm−N / 2, and if N is an odd number, Sm + (N− 1) The output integrator 7 may add N to Sn when / 2 ≧ Sn> Sm− (N + 1) / 2. In this case, the difference between Sn and Sm is in the range of −N / 2 to N / 2 or − (N + 1) / 2 to (N−1) / 2. Thereby, the absolute value of the difference between the integrated values Sm and Sn indicating the position of the input / output digital signal can be reduced.

As yet another integration control method, the output integrator 7 always integrates N when M> N. If M is an even number, Sn + M / 2 ≧ Sm> Sn−M / 2, and if M is an odd number, Sn + The input integrator 6 may integrate M to Sm when (M−1) / 2 ≧ Sm> Sn− (M + 1) / 2. In this case, the difference between Sn and Sm is in the range of −M / 2 to M / 2 or − (M + 1) / 2 to (M−1) / 2. Thereby, the absolute value of the difference between the integrated values Sm and Sn indicating the position of the input / output digital signal can be reduced.

As a simple integration control method, the input integrator 6 may integrate M with Sm when Sm ≦ Sn, and the output integrator 7 may integrate N with Sn when Sn <Sm. However, only one of M and N is integrated, and the processing time becomes long. In order to solve this problem, Embodiment 3 (described later) reduces the processing time by pre-determining and controlling the integration of Sm and Sn.

In the first embodiment, the sampling rate conversion in the horizontal direction of the image is assumed, but the difference in the case of the sampling rate conversion in the vertical direction of the image will be described. The conversion in the vertical direction is also called image line number conversion. The configuration of the apparatus is the same in both the horizontal and vertical directions, but a line clock is used in sampling rate conversion. For example, in the case of an HD60P image, the number of effective pixel lines is 1080, the number of invalid pixel lines is 45, and a total of 1125 lines is included, so the frequency of the line clock is 67.5 kHz. Line pixel input / output control and FIR coefficient selection are controlled by the Line frequency, and input pixels for a plurality of Lines are loaded into the memory for processing. Accordingly, when parameters such as FIR coefficient of a certain pixel are determined, the same parameter is applied to all pixels on the same Line. In the case of HD images, since there are 1920 pixels per line, the FIR calculation is common to all 1920 pixels. Eventually, the sampling rate conversion calculation is performed at the same clock frequency as the horizontal calculation. In the horizontal conversion, the input digital signal is transferred to the parallel read shift register and the parallel FIR operation is performed. In the vertical conversion, a plurality of lines of a predetermined input digital signal are accessed in parallel, and the horizontal direction on each line is the same. The output pixel is calculated with reference to the input pixel at the position.

Embodiment 2. FIG.
FIG. 5 is a block diagram showing a sampling rate conversion apparatus according to Embodiment 2 of the present invention. The apparatus according to this embodiment can be implemented when the output sampling rate is higher than the input sampling rate, and operates at the output sampling rate (output clock) of the output digital signal. The FIFO memory 1 temporarily stores the input digital signal and then supplies it to the shift register 2 in synchronization with the output clock. The parallel FIR calculator 3 converts the input digital signal supplied from the shift register 2 into an output digital signal and outputs it.

The position coordinate difference calculation unit 5 further includes a comparison subtracter 12. When E is a positive integer not less than M or not less than N, the comparison subtractor 12 supplies a load clock to the input integrator 6 and the output integrator 7 simultaneously when Sm ≧ E and Sn ≧ E, and the input integrator 6 and Sm-E and Sn-E are supplied to the load terminal of the output integrator 7, respectively.

The integrated value comparator 8 adds M to the input integrator 6 when Sn + N ≧ Sm + M, and outputs Sn−Sm at that time as the position coordinate difference Dk. Here, since M> N, the output integrator 7 always accumulates N.

Table 3 shows changes in the integrated values Sm and Sn when M = 8, N = 3, the initial value of Sm is 4, the initial value of Sn is 1.5, and E = 16 (2 to the 4th power).

The operation from the initialization operation to the fourth clock is the same as in the first embodiment. At the fifth clock, Sm ≧ E and Sn ≧ E, and at the sixth clock, E (= 16) is subtracted from Sm and Sn. At this time, the decimal part of Sm and Sn set as initial values does not change. Thereafter, E is subtracted at the 11th, 16th, and 21st clocks, and E (= 16) is subtracted from Sm and Sn at the 12th, 17th, and 22nd clocks.

In the first embodiment, the reset is performed with a cycle of the least common multiple of the input / output cycles M and N. However, in this embodiment, E may be greater than or equal to M or greater than or equal to N. The number of bits can be further reduced as compared with the first embodiment. If E is smaller than M or N, even if E is subtracted from Sm and Sn, Sm and Sn are not reduced sufficiently, and Sm and Sn continue to increase, so the number of bits cannot be reduced sufficiently.

Further, it is preferable that E is a power of 2 that is M or more or N or more. In this case, if it is detected that the bit indicating the value of E changes from 0 to 1, Sm ≧ E and Sn ≧ E can be easily determined.

For example, if M = 8 and N = 3 and E = 5, two sets of comparison subtractors 12 are required for Sm and Sn. On the other hand, for example, if E = 16, it is determined whether the fifth bit of Sm and Sn is 1 at the same time. If the determination is true, both may be changed from 1 to 0. Therefore, a subtractor for calculating Sm−E and Sn−E and a circuit for determining Sm ≧ E and Sn ≧ E are unnecessary, and a simple gate logic circuit for determining 0 and 1 of the fifth bit of Sm and Sn. The comparison subtracter 12 can be configured.

In the first embodiment, the position coordinate difference between the input and output digital signals is an integer. However, in practice, the position coordinate difference may be less than 1. Therefore, in this embodiment, considering the case where the position of the output digital signal is shifted by 0.5 from the position of the input digital signal, the accuracy of the input integrator 6 and the output integrator 7 is set to 0.5 instead of 1. . Specifically, the integration of M and N is the same as in the first embodiment, but the initial values of Sm and Sn are set to 0.5 units. That is, the accuracy of the input integrator 6 and the output integrator 7 is extended to the decimal part. Thereby, the position of the output digital signal can be arbitrarily shifted.

Such extension to the decimal part is necessary, for example, when the center position of the input / output image is set to the center position of the screen. Note that the type of position coordinate difference Dk used when selecting the FIR coefficient is not affected by the fraction (fractional part) of less than 1 of the initial value, so the number of FIR coefficient sets is the same as in the first embodiment. In addition, the lower 4 bits of Table 3 indicate a part including a fractional part 1 bit, but the LSB (least significant bit) is always “1”. Therefore, the 3 bits excluding the actual LSB become meaningful data, thereby selecting a set of FIR coefficients.

Embodiment 3 FIG.
FIG. 6 is a block diagram showing a sampling rate conversion apparatus according to Embodiment 3 of the present invention. The apparatus of the present embodiment is a sampling rate converter mainly used for digital audio, and an input digital signal sampled at an input sampling rate of 48 kHz (a general frequency of commercial digital audio) is output samples. To an output digital signal sampled at a sampling rate of 44.1 kHz (audio CD). The sampling rate conversion in this case is a one-dimensional sampling rate conversion on the time axis.

The devices of the first and second embodiments are mainly intended for image processing, and the sampling rate of the image (the frequency of the pixel sample string) is about several MHz to 150 MHz. Therefore, a product that refers to several tens of samples per pixel. A parallel FIR calculator 3 is used to perform the sum operation. On the contrary,
The audio sampling rate is as low as several tens of kHz, and even a frequency several hundred times as high as several tens of MHz. Therefore, in this embodiment, the serial FIR calculator 13 is used to reduce the circuit configuration such as a multiplier.

The apparatus according to the present embodiment operates at an input sampling rate (input clock 48 kHz) of an input digital signal. However, since the FIR order of audio (the number of input digital signals to be referred to) is high and the sampling rate is low, the PLL 14 generates a FIR operation clock 12.288 MHz that is 256 times the input clock. The serial FIR calculator 13 operates with this FIR calculation clock and converts the input digital signal into an output digital signal. In the case of 256 times the clock, the order of FIR (the number of input digital signals to be referred to in the FIR calculation) is 255 at the maximum. The FIFO memory 4 stores the output digital signal, and outputs it in synchronization with the output clock 44.1 kHz after an appropriate delay (for example, after about 100 input digital signals have elapsed after initialization).

The position coordinate difference calculation unit 5 operates with an input clock. When the input clock is 48 kHz input and the output clock is 44.1 kHz, the cycle ratio M: N = 147: 160. The integrated value comparator 8 adds N to the output integrator 7 when Sm + M ≧ Sn + N, and outputs Sn−Sm at that time as the position coordinate difference Dk. Here, since N> M, the input accumulator 6 always accumulates M. Similarly to the first embodiment, the initial value detection reset unit 11 resets Sm and Sn to the initial values when the difference between Sm and Sn matches the initial value.

When M = 147 and N = 160, the position coordinate difference Dk is 147 types (0 to 146). If the 147 types of position coordinate differences Dk are 50th-order FIR, 50 terms of FIR coefficients are required. Note that the image signal is generally 8 to 10 bits / sample, but the audio signal is 12 to 24 bits / sample, and high-quality sample value calculation is required. Therefore, the FIR order is several times that of the image. Become. Here, it is 50th for simplicity.

FIG. 7 is a block diagram showing a serial FIR computing unit according to Embodiment 3 of the present invention. FIG. 8 is a timing chart showing the operation of the serial FIR calculator according to the third embodiment of the present invention. This serial FIR computing unit is a 50-Tap serial FIR computing unit that performs serial product-sum operation using 50 input digital signals to obtain one output digital signal.

In the case of serial FIR calculation, the input digital signal is stored in the RAM 15 (Random Access Memory) for each sample, not in the shift register. The input digital signal generates an address by the input counter 16 and is stored in the RAM 15. For simplicity, the RAM 15 is a 2-Port RAM that can perform Write and Read simultaneously. For example, when the RAM 15 stores 256 samples with an 8-bit address, the address of the RAM 15 becomes 0, 1,.

Sn-Sm is supplied from the position coordinate difference calculation unit 5 to the FIR coefficient memory 9, and a set of FIR coefficients corresponding to the address is selected. In synchronization with the input clock, the FIR operation counter 17 is reset to 255, and at the same time, the product-sum register 18 is also reset to 0. Thereafter, 50 input digital signals Xj (j = 0 to 49) for calculating one output digital signal are determined, and the input digital signal and the corresponding FIR coefficient Fj (j = 0 to 49) are multiplied. Multiply by 19. The adder 20 multiplies the Xj · Fj for each FIR operation clock, and the product-sum register 18 stores the product sum. When all the product-sums are finished, the output digital signal Y = X0 · F0 + X1 · F1 +... + X49 · F49 is calculated.

The RAM 15 holds 256 samples even when the FIR calculation counter value is smaller than 49, and is configured in a ring shape. For this reason, the previous sample of n = 0 is held at address 255. Accordingly, the output 0-1 = −1 of the subtractor 21 becomes 255, and appropriate input digital signals are successively referred to in order.

Since the serial FIR calculation ends within the period of one input digital signal, the data in the RAM 15 does not change within that period. When the FIR calculation is 50th order (FIR calculation referring to 50 input digital signals), the FIR calculation is performed when the FIR calculation counter value is between 0 and 49. At that time, the FIR operation counter 17 supplies the window signal of the reference input sample to the product-sum register 18. When the FIR calculation counter value reaches 50, the FIR calculation result at that time is output. No operation is performed between the remaining counter values 51 to 254, and the counter value 255 is reset.

When the operation of the FIR operation counter 17 starts, the subtracter 21 subtracts the value of the FIR operation counter from the value of the input counter 16 used for the write address of the RAM 15. The input digital signal of the Read address corresponding to the subtraction value is referred to in order. That is, the past input digital signal is referred to by one sample from the latest input digital signal. For example, when the input counter value at the start of calculation is n, the FIR calculation counter values 0 to 49 are sequentially subtracted from n, so that the output of the subtractor 21 is n, n−1,..., N−49. As a result, the input digital signals of Read addresses n to n-49 are sequentially referred to. At this time, since the FIR coefficient memory 9 is accessed with addresses of FIR calculation counter values 0 to 49, the FIR coefficient corresponding to the input digital signal Xn is F (0), and Xn−1 is F (1), Xn−2. Then F (2),... Xn-49 becomes F (49). Since the FIR calculation counter value of the sample at the center position of the input digital signal sequence to be referred to is 24 or 25, the input digital signal close to the output digital signal is X24 or X25.

Table 4 shows the transition of the integrated values Sm and Sn in the present embodiment.

First, X0 to X48 (49 samples) of the reference input digital signals X0 to X49 in the 50th-order FIR calculation are written in the RAM 15. Initial reset is performed at time T0, and input / output integrated values Sm and Sn are reset to zero. Input digital signals are written during the reset period, and a total of 50 input digital signals X0 to X49 are written in the RAM 15 after reset.

標本 Sampling rate conversion starts after initialization. At the first clock after initialization (time T1), M is accumulated in Sm, but since Sm + M <Sn + N, N is not accumulated in Sn, so that an output digital signal is not calculated. Sm = 147 and Sn = 0.

At time T2, since Sm + M ≧ Sn + N, M and N are added to Sm and Sn, respectively, and an output digital signal is calculated. Sm = 294 and Sn = 160. Referring to the input digital signals X0 to X49, Y0 = X0 · F0 + X1 · F1 +... + X49 · F49 is calculated to obtain the output digital signal Y0. Here, F0 to F49 are FIR coefficients for X0 to X49, respectively. This set of FIR coefficients is selected from the FIR coefficient memory 9 from an address corresponding to Sn−Sm = 160−294 = −134 and Modulo (−134,147) = 13.

The FIR coefficient memory 9 requires 6 bits for selecting 50 FIR coefficients for the 50th order FIR and 8 bits for selecting 0 to 146 of the position coordinate difference Dk. It consists of a RAM with an address. The selection of 50 coefficients operates at 12.288 MHz, and the selection of the position coordinate difference Dk operates at 48 kHz.

The same applies after time T3. Since the condition of Sm + M ≧ Sn + N is satisfied from time T3 to T12, output digital signals Y1 to Y10 are sequentially calculated. At time T13, since Sm + M = 1911 <Sn + N = 1920, the output digital signal is not calculated, and at time T14, Sm + M ≧ Sn + N, and the output digital signal Y11 is calculated.

After the same operation continues for a while, the difference between Sm and Sn coincides with the initial value at time T160, so Sm and Sn are reset to the initial value 0. The operation after reset is the same as the operation after initialization.

In the present embodiment, the same effects as in the first embodiment can be obtained by the above-described configuration and operation. Also in this embodiment, reset control is performed as in the first embodiment. Image sampling rate conversion always resets at the edge of the image, but since audio does not have a spatial division like an image, the sample value continues infinitely on the time axis and the integrated value becomes infinite. growing. For this reason, reset control is particularly important in a sampling rate converter used for audio.

For example, if M = 147, N = 160, and there is no reset control when the audio sample continues for 24 hours, Sm and Sn are 147 × 48000 × 3600 × 24 = 160 × 44100 × 3600 × 24≈6.1 × 10 ¹¹ ≈2 ^39.2 , and are expressed by 40 bits. The On the other hand, in this embodiment, the reset is performed when both Sm and Sn reach 23360, so the maximum value of Sm and Sn becomes 23360, which can be expressed by 15 bits. Therefore, the accuracy of the adder / subtractor, etc., which required 40 bits in 24-hour continuous operation, can be reduced to 15 bits by the reset control.

In this embodiment, as in the second embodiment, when Sm ≧ E and Sn ≧ E, if E is subtracted from Sm and Sn at the same time, a register, an adder / subtracter, a size determination device, etc. The number of bits can be further reduced. For example, if M = 147 and N = 160, it is preferable to set E to a power-of-two value 256 of 147 or more so that it can be easily configured with binary hardware. In this case, if it is determined whether each 9th bit of Sm and Sn is 1, it can be determined whether Sm and Sn are 256 or more. Therefore, when each 9th bit of Sm and Sn is 1, the 9th bit of Sm and Sn may be set to 0 simultaneously. As a result, the number of bits of the register, the adder / subtracter, the magnitude judgment device, etc. can be made 9 bits.

3 parallel FIR calculator (FIR calculator), 5 position coordinate difference calculator, 6 input integrator, 7 output integrator, 8 integrated value comparator, 9 FIR coefficient memory, 11 initial value detection reset unit, 12 comparison subtractor , 13 Serial FIR calculator (FIR calculator)

Claims

A sampling rate converter for converting an input digital signal sampled at an input sampling rate into an output digital signal sampled at an output sampling rate,
A position coordinate difference calculating unit that calculates a position coordinate difference Dk between the position coordinates of the input digital signal close to the position coordinates Tk of the output digital signal Yk and the position coordinates Tk;
The FIR− when the position coordinate of the impulse input inputted to the FIR-LPF (Finite Impulse Response Low Pass Filter) having the characteristic of cutting off the frequency component of 1/2 or more of the output sampling rate is set to z = 0. When the FIR coefficient F (z) of the LPF is stored and the position coordinate difference Dk is input, a certain number (p) of input digital signals Xk (p) existing in the vicinity of the position coordinate Tk of the output digital signal Yk. The position coordinates of q) are Zk (q), (q = 1, 2,..., p), and the FIR coefficient F (Zk (q) −Tk) corresponding to the position coordinate difference (Zk (q) −Tk) FIR coefficient memory for outputting
Yk = F (Zk (1) −Tk) * Xk (1) + F (Zk (2) −Tk) * Xk (2) +... + F (Zk (p) −Tk) * Xk (p) A sampling rate conversion apparatus comprising: an FIR computing unit for obtaining the output digital signal Yk.
C is a constant, M and N are mutually prime positive integers, the sampling period of the input digital signal is C · M, the sampling period of the output digital signal is C · N,
The position coordinate difference calculation unit
An input integrator that integrates M and outputs an integrated value Sm;
An output integrator for integrating N and outputting an integrated value Sn;
When Sm-Sn is less than or equal to a predetermined value, M is accumulated in the input integrator, and when Sn-Sm is less than or equal to a predetermined value, N is accumulated in the output integrator, and N is accumulated in the output integrator. 2. The sampling rate converter according to claim 1, further comprising an integrated value comparator that outputs Sn-Sm at the time as the position coordinate difference Dk.
The sample according to claim 2, wherein the position coordinate difference calculation unit further includes an initial value detection reset unit that resets Sm and Sn to an initial value when a difference between Sm and Sn matches an initial value. Conversion rate converter.
The position coordinate difference calculation unit further includes a comparison subtractor that subtracts E from Sm and Sn simultaneously when Sm ≧ E and Sn ≧ E, where E is a positive integer not less than M or not less than N. The sampling rate conversion apparatus according to claim 2.
The sampling rate conversion apparatus according to any one of claims 2 to 4, wherein the accuracy of the input integrator and the output integrator is expanded to a decimal part.