JPH04235407A - Analog/digital conversion system - Google Patents

Abstract

PURPOSE:To provide the system converting the analog signals into plural digital signals having plural sampling frequency based on the single clock. CONSTITUTION:The analog signal is converted into a first digital signal in an A/C converter 10. A second digital signal is generated by performing the interpolation for the first digital signal in an interpolation device 41. After the components of the folded noise are removed by a digital filter 42 for the second digital signal, a third digital signal is obtained by thinning out in a D-type flip flop 43. The sampling frequency of the third digital signal is changed into the expected frequency by selecting the ratios of these interpolation and thinning out properly. A selector 44 gives the interpolation clock to the interpolation device 41 after selecting the interpolation clock, ROM 45 gives the factor data to the digital filter 42 and a selector 46 gives the output clock to the D-type flip flop 43 by selecting the output clock.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an analog/digital (A/D) conversion method for converting an analog signal into a digital signal, and in particular, an overflow method for performing A/D conversion at a higher frequency than the sampling frequency of an output digital signal. This relates to a sampling type A/D conversion method.

0002

[Background Art] With the development of digital technology in recent years,
BACKGROUND ART Analog signal to digital signal conversion (A/D conversion) technology has become extremely important. There are various standards for the sampling frequency when performing A/D conversion depending on the frequency band of the signal. For example, in the case of audio signals, three types are widely used: 32 KHz, 44.1 KHz, and 48 KHz. Conventionally, A/D conversion using these sampling frequencies required a clock corresponding to each frequency. This situation will be explained using FIG. 5.

FIG. 5 shows a conventional analog/digital (A/
D) is a block diagram showing an example of a configuration of a conversion method. 50
is an A/D converter, which converts an analog input into a digital signal using a given clock as a sampling frequency. Here, A/D conversion is performed using a sampling frequency of 3072 KHz. A digital filter 51 limits the band of the input digital signal. Here, in order to perform 64:1 thinning, a frequency equal to or higher than 1/128 of the sampling frequency is set as a cutoff region. Reference numeral 52 denotes a D-type flip-flop (DFF), to which a digital output sampling frequency of 48 KHz is applied as a clock. This clock is A/D
This can be easily obtained by dividing the conversion clock by 64.

Next, the operation of FIG. 5 will be explained. The analog input is converted into a digital signal by an A/D converter 50. The sampling frequency at this time is 3072 KHz given as an A/D conversion clock. The obtained digital signal is subjected to a digital filter 51 which limits the signal band to 1/128th of the sampling frequency or less, and a DFF 52 which performs 64:1 thinning.
This is a digital output with a sampling frequency of 48KHz. That is, this is a so-called 64 times oversampling A/D conversion method in which A/D conversion is performed at a frequency 64 times the sampling frequency of the digital output to be finally obtained.

[0005] The frequencies of each clock shown here are those when the sampling frequency of the digital output is 48 KHz, and for example, the final frequency is 32 KHz, 44.1 KHz.
To obtain a digital output with a sampling frequency of Hz, each A/D conversion clock requires 2048K.
Hz and 2822.4 KHz, and it was necessary to provide clocks of 32 KHz and 44.1 KHz as output clocks, respectively.

[0006]

However, in the conventional method described above, when attempting to obtain a plurality of digital outputs having a plurality of sampling frequencies, it is necessary to prepare a plurality of clocks. To obtain these clocks from one oscillator, an oscillator with a frequency corresponding to a common multiple of multiple clocks is required.For example, in the case of the above conventional example, the frequency is extremely high at 903.168 KHz, which is not practical. . Therefore, it is common to switch and use different oscillators for each of the plurality of clocks, which poses a problem of increasing the circuit scale.

Furthermore, since the oscillator is used by switching, devices such as digital audio tape recorders (DATs) that control mechanical systems and operation systems using a microcontroller require a dedicated clock for the microcontroller. Since two systems of clocks exist simultaneously, there is a problem in that a means for preventing mutual interference is required.

Furthermore, in order to obtain a plurality of digital signals at the same time, it is necessary to use a plurality of A/D converters.

[0009] The present invention solves these problems.
The present invention provides a method for converting an analog signal into multiple digital signals having multiple sampling frequencies based on a single clock.

0010

To achieve this object, the present invention converts an analog signal into a first digital signal at a first sampling frequency, and performs interpolation on the first digital signal. A second digital signal having a second sampling frequency higher than the first sampling frequency is generated, aliasing noise components are removed from the second digital signal by a digital filter, and then thinning is performed to generate a third signal. An analog/digital conversion method is used to obtain a third digital signal having a sampling frequency.

Further, the present invention converts an analog signal into a first digital signal at a first sampling frequency, performs a plurality of interpolations on the first digital signal, and performs a plurality of interpolations higher than the first sampling frequency. a plurality of second digital signals having a second sampling frequency of This is an analog/digital conversion method that obtains a plurality of third digital signals having a sampling frequency of .

Further, the present invention converts an analog signal into a first digital signal at a first sampling frequency, performs a plurality of interpolations on the first digital signal, and performs a plurality of interpolations higher than the first sampling frequency. a plurality of second digital signals having a second sampling frequency of This is an analog/digital conversion method in which one or more third digital signals having one or more third sampling frequencies are obtained by thinning out after removing the signals.

[0013]

[Operation] With the above configuration, the analog/digital conversion method of the present invention converts an analog signal into a first digital signal at a first sampling frequency, and performs a combination of interpolation and thinning on the obtained first digital signal. By performing the signal processing, one or more third digital signals having one or more third sampling frequencies can be obtained. At this time, if multiple digital filters are used, multiple third digital signals can be obtained simultaneously, and if the coefficients of the digital filters can be selected according to the third sampling frequency, the A/D converter's The circuit scale can be reduced.

[0014]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an analog/digital (A/D) conversion system according to the present invention. 10 is an A/D converter which converts an analog input into a digital signal using a given A/D conversion clock as a sampling frequency. Here, 784 KHz is given as the A/D conversion clock. 11, 14, 17
are interpolators that perform interpolation at different ratios, respectively 1:
Interpolation is performed at a ratio of 3, 1:9, 1:2. Therefore, the interpolation clock is 3 times the A/D conversion clock and 9 times the A/D conversion clock, respectively.
2352KHz, 7056KHz, equivalent to twice,
1568KHz is given. Note that there are many methods for interpolation, but here we use zero-order interpolation that maintains the same data. Digital filters 12, 15, and 18 have different transfer characteristics, and limit the band of the input digital signal. 13, 16, and 19 are D-type flip-flops (DFF), each with 4 output clocks.
8KHz, 44.1KHz, and 32KHz are given.

Next, the operation of FIG. 1 will be explained. First, an analog input is converted into a digital signal by the A/D converter 10. The sampling frequency at this time is given A/
The frequency of the D conversion clock is 784 KHz. The digital signal output from the A/D converter 10 is sent to an interpolator 11,
14 and 17. The digital signal input to the interpolator 11 is 1 based on the 2352 KHz interpolation clock 1.
By interpolating :3, the sampling frequency is tripled to 23
After reaching 52 KHz, it is input to the digital filter 12. The input digital signal has its signal band limited by the digital filter 12, and the signal band is limited by the DFF 13 to 49:
The data is decimated by 1, resulting in a digital output of 1 with a sampling frequency of 48 KHz. Similarly, in interpolator 14, 70
A 1:9 interpolation is performed using an interpolation clock 2 of 56 KHz, and after the signal band is limited by a digital filter 15, a 160:1 thinning is performed by a DFF 16 to obtain a digital output 2 with a sampling frequency of 44.1 KHz. Furthermore, the interpolator 17 performs 1:2 interpolation using the 1568 KHz interpolation clock 3, and after the signal band is limited by the digital filter 18, the DFF 19 performs 49:2 interpolation.
A decimation of 1 is performed to obtain a digital output 3 with a sampling frequency of 32 KHz.

As described above, by repeating interpolation and thinning of the A/D converter output, a digital output having a sampling frequency of an integer ratio is obtained. Here, the frequency characteristics of the digital filters 12, 15, and 18 will be explained in detail.

FIG. 2 shows the digital filter 1 in FIG.
2 is a characteristic diagram showing specific examples of frequency characteristics of frequencies 2, 15, and 18. FIG. In FIG. 2, (a) shows the frequency characteristics of the digital filter 12, (b) shows the frequency characteristics of the digital filter 15, and (c) shows the frequency characteristics of the digital filter 18.

First, in FIG. 2(a), in order to change the sampling frequency from 2352 KHz to 48 KHz, 49 (=2
352÷48): represents the frequency characteristic for thinning out 1. Here, the signal band is 0 to 20 KHz, and by thinning out 49:1 (48n±20) KHz.
(n is an integer, 1≦n≦48) band components are aliased into the signal band and become so-called aliasing noise, so 28 to 2
The 324 KHz band is collectively defined as a cutoff region.

FIG. 2(b) shows that the sampling frequency is 705.
160 (=7) to go from 6KHz to 44.1KHz
056÷44.1): represents the frequency characteristic for thinning out 1. The signal band is 0-20KHz, 24.
The band from 1 to 7031.9 KHz is set as a cutoff region.

FIG. 2(c) shows that the sampling frequency is 156
49 (=1568
÷32): represents the frequency characteristic for thinning out 1. Signal band is 0~14KHz, 18~1550K
The Hz band is the cutoff region.

FIG. 3 is a timing diagram illustrating the process of obtaining digital output 1 among the operations of the embodiment of the A/D conversion system shown in FIG. In FIG. 3, (a) is an A/D
(b) is the output of the A/D converter 10, (c) is the interpolation clock 1 (2352KHz).
Hz), (d) the output of the interpolator 11, (e) the output of the digital filter 12, and (f) the output clock 1.
(48KHz), and (g) represents digital output 1, respectively.

Next, the operation of FIG. 1 will be explained using FIG. 3. A/D converter 1 in synchronization with the A/D conversion clock (a)
The digital signal (b) output from 0 is input to the interpolator 11, and 1:3 interpolation is performed by the interpolation clock 1(c). Since the interpolation at this time is zero-order interpolation in which the same data is held as described above, the output of the interpolator 11 is data in which the same data is repeated three times as shown in (d).

Now, the output (d) of the interpolator 11 is input to the digital filter 12, and after being band-limited as shown in FIG. 2(a), it becomes an output as shown in FIG. 2(e). This data string is defined as (P0, P1, P2,...). Next, the output (e) of the digital filter 12 is D
Input to FF13, output clock 1(f) causes 49
:1 thinning is performed. Therefore, digital output 1 (
g) is (P0, P49,...).

The above explanation of the operation relates to the process of obtaining digital output 1, but the processes of obtaining digital output 2 and digital output 3 are similar except that the interpolation and thinning ratios are different. be.

FIG. 4 is a block diagram showing another embodiment of the analog/digital (A/D) conversion system according to the present invention. 40 is an A/D converter which converts an analog input into a digital signal using a given A/D conversion clock as a sampling frequency. Here, 784 KHz is given as the A/D conversion clock 1. An interpolator 41 performs interpolation based on an interpolation clock given from a selector 44. 42 is a digital filter;
It limits the band of the input digital signal, and its frequency characteristics are determined by coefficients provided by the ROM 45. 43 is a D type flip-flop (
DFF), and performs thinning based on the output clock given from the selector 46. 44 is a selector;
Interpolated clock 1 based on sampling frequency control signal
(2352KHz), interpolation clock 2 (7056KHz)
) and interpolation clock 3 (1568 KHz) and outputs it to the interpolator 41. A read-only memory (ROM) 45 selects predetermined coefficient data based on the sampling frequency control signal and outputs the selected coefficient data to the digital filter 42 . 46 is a selector which selects output clock 1 (48K) based on the sampling frequency control signal.
Hz), output clock 2 (44.1KHz) and output clock 3 (32KHz), and select one from DFF4.
Output to 3.

Next, the operation of FIG. 4 will be explained. First, an analog input is converted into a digital signal by an A/D converter 40 and input to an interpolator 41. The sampling frequency at this time is the frequency 784 of the given A/D conversion clock.
It is KHz. The digital signal input to the interpolator 41 is interpolated using an interpolation clock given from the selector 44 and is input to the digital filter 42 . The input digital signal is filtered by the digital filter 42.
After receiving the signal band limit determined by the coefficient given from OM45, it is input to DFF43, and then
At step 3, the data is thinned out using the output clock provided from the selector 46 and becomes a digital output.

At this time, the interpolation clock, the frequency characteristics (coefficients) of the digital filter, and the output clock are determined by the sampling frequency control signal. For output clock 1, the characteristics of interpolated clock 1 and Figure 2 (a) are the same, and for output clock 2, the characteristics of interpolated clock 2 and Figure 2 (b) are
) is the interpolated clock 3 for the output clock 3.
and the characteristics shown in FIG. 2(c) are selected in correspondence with each other. In other words, the operation in FIG. 4 is equivalent to selecting the system that outputs digital output 1, the system that outputs digital output 2, and the system that outputs digital output 3 in FIG. 1 by the sampling frequency control signal. be.

As explained above, when trying to obtain multiple digital signals with multiple sampling frequencies, it is not necessary to prepare multiple oscillators, but by dividing a single oscillation frequency, the necessary You can get all the clocks you want. The oscillation frequency of the oscillator at this time is A/D
It may be a common multiple of the conversion clock, interpolation clock, and output clock; for example, in the method shown in Figure 1, 14112K
The frequency may be Hz or a multiple thereof.

Further, the ratio between the A/D conversion clock and the sampling frequency of the digital output can be any rational number (both the denominator and numerator are fractions of integers).

[0031] In this embodiment, the A/D is 784KHz.
Conversion is being performed, but the frequency is n times 784KHz (n is an integer)
may be used. In this case, in order to keep the output clock and signal band constant, all interpolated clocks are n
In addition, the thinning ratio also increases by n times. In addition, for example, (7056m/n) KHz (m, n are integers)
/D conversion clock, sampling frequency 48KHz
1:n interpolation and 147m:1 for the digital output of
For decimation, 1:n interpolation and 160m:1 decimation may be performed for 44.1KHz output, and 1:2n interpolation and 441m:1 decimation for 32KHz output. .

Furthermore, although this embodiment has shown an A/D conversion method that outputs digital signals having three types of sampling frequencies, there is of course no restriction on the types of output sampling frequencies. For example, in the method shown in Figure 1, the sampling frequency is 1.
It is also possible to add a process to obtain a 6KHz digital output.

Further, in the embodiment shown in FIG. 4, three types of processing are performed in one processing system using one each of an interpolator, a digital filter, and a DFF, but any number of types of processing can be performed as necessary. Moreover, it goes without saying that such a processing system is not limited to one, and a method using a plurality of processing systems is also possible.

[0034]

[Effect of the invention] As explained above, the analog/
The digital conversion method can be achieved by performing A/D conversion with a single clock when trying to obtain multiple digital signals with multiple sampling frequencies. All can be obtained by dividing the frequency. Also, since the frequency of the A/D conversion clock is single, multiple digital signals can be converted into a single A/D conversion clock.
They can be obtained simultaneously using a D conversion device. Further, since the ratio between the A/D conversion clock and the sampling frequency of the digital output can be any rational number (the denominator and the numerator are both integer fractions), the oscillation frequency of the oscillator can have a large degree of freedom.

Furthermore, if it is not necessary to obtain all the plurality of digital signals at the same time, A /
The circuit scale of the D conversion device can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an analog/digital conversion method according to the present invention.

[Fig. 2] Digital filters 12, 15, in Fig. 1;
Characteristic diagram showing specific examples of 18 frequency characteristics

FIG. 3 is a timing diagram explaining the process of obtaining digital output 1 among the operations of the embodiment of the A/D conversion method in FIG.

FIG. 4 is a block diagram showing another embodiment of the analog/digital conversion method according to the present invention.

[Figure 5] Block diagram showing an example of a configuration of a conventional analog/digital conversion method

[Explanation of symbols]

10, 40 A/D converter 11, 14, 17, 41 Interpolator 12, 15, 18, 42 Digital filter 13,
16, 19, 43 D-type flip-flop (DFF) 44, 46 Selector

Claims (5)

[Claims] 1. Converting an analog signal into a first digital signal at a first sampling frequency, performing interpolation on the first digital signal to obtain a second sampling frequency higher than the first sampling frequency. Analog/digital conversion that generates a second digital signal having a third sampling frequency, removes aliasing noise components from the second digital signal by a digital filter, and then performs thinning to obtain a third digital signal having a third sampling frequency. method. 2. Converting an analog signal into a first digital signal at a first sampling frequency, and performing a plurality of interpolations on the first digital signal to obtain a plurality of second digital signals higher than the first sampling frequency. A plurality of second digital signals having a sampling frequency of An analog/digital conversion method for obtaining a plurality of third digital signals with 3. Converting an analog signal into a first digital signal at a first sampling frequency, and performing a plurality of interpolations on the first digital signal to obtain a plurality of second digital signals higher than the first sampling frequency. a plurality of second digital signals having a sampling frequency of An analog/digital conversion method that is subsequently thinned out to obtain one or more third digital signals having one or more third sampling frequencies. Claim 4: The first sampling frequency is (784n)
KHz (n is a positive integer), and performs three types of interpolation, 1:3, 1:9, and 1:2, on the first sampling frequency to obtain the second sampling frequency (2352n)KH.
z, (7056n) KHz, (1568n) KHz 3
The second sampling frequency is thinned out by 49n:1, 160n:1, and 49n:1, respectively, and the third sampling frequency is set to 48KHz,
4. The analog/digital conversion method according to claim 3, wherein the analog/digital conversion method is of three types: 44.1 KHz and 32 KHz. Claim 5: The first sampling frequency is (7056 m
/n) KHz (m, n are positive integers), and the first sampling frequency is 1:n, 1:n, 1:2n.
A type of interpolation is performed to change the second sampling frequency to (70
56m) KHz, (7056m) KHz, (14112
m) 3 types of KHz, respectively 147 m: 1,160 m: 1,441 for the second sampling frequency.
4. The analog/digital conversion method according to claim 3, wherein m:1 thinning is performed to set the third sampling frequencies to three types, 48 KHz, 44.1 KHz, and 32 KHz.