JPH07212190A - Sampling frequency converter - Google Patents

Abstract

PURPOSE:To prevent the degradation of a reproduced audio signal due to different sampling frequencies and to realize the mixing by a free sampling frequency conversion by using a simple constitution. CONSTITUTION:A buffer memory 2 for resampling stores the input signal Dsi of the input sampling frequency Fsi inputted from an input terminal 1. An interpolation processing circuit 3 performs an interpolation processing for the signal read from a buffer memory 2 for resampling. A sampling frequency ratio detection circuit 7 detects the ratio of the sampling frequency of an input sampling frequency Fsi to be supplied from an input terminal 5 and an output sampling frequency Fso to be supplied from an input terminal 6 by each of a short time cycle ts and a long time cycle tL. A controller 8 controls the buffer memory for resampling and the interpolation processing circuit 3 according to the sampling frequency ratio Rs or RL of the short time cycle ts or the long time cycle tL of the sampling frequency ratio detection circuit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling frequency converter for re-sampling a sampling frequency of an input signal and converting it to an arbitrary sampling frequency.

[0002]

2. Description of the Related Art Recently, a digital audio signal reproducing apparatus for transmitting an audio signal as it is as a digital signal using an optical cable or a coaxial cable and reproducing it through a digital audio interface has become widespread. In this digital audio signal reproducing apparatus, a phase locked loop (hereinafter referred to as PLL) including a phase comparator and a voltage controlled oscillator (hereinafter referred to as VCO) when receiving the digital audio signal.
Is used to generate the clock. However, when this clock is generated, digital / analog (hereinafter referred to as D / A) conversion processing characteristics may be deteriorated due to the jitter of the PLL VCO. Therefore, in a device for reproducing a digital audio signal recording medium such as a compact disc (hereinafter referred to as CD) player or a digital audio tape (hereinafter referred to as DAT) player, a digital audio signal is reproduced by using a quartz clock. In some cases, it may be possible to obtain a good audio signal without distortion by converting the analog audio signal by the A / A conversion process and then transmitting the analog audio signal.

Further, at present, in a recording medium as a source of a digital audio signal, for example, a CD, an optical disc smaller than a CD, a digital audio tape smaller than a DAT, a sampling frequency at the time of recording a digital audio signal. For example, 44.1KHz, 48KHz, 32
It is one of KHz and is not unified. Further, the sampling frequency of satellite broadcasting (hereinafter referred to as BS), which is not a recording medium but serves as a source of a digital audio signal, is one of the sampling frequencies. Therefore, for example, DAT and BS whose sampling frequency is 48 KHz
The sampling frequency of the digital audio signal from
When recording on a small optical disk of KHz, the DAT and BS digital audio signals having a sampling frequency of 48 KHz are converted into analog signals by D / A conversion processing, and then again analog / digital (hereinafter referred to as A /
Called D. ) Due to the conversion process, the sampling frequency is 44.1KHz
Must be converted into a digital audio signal of
Deterioration of characteristics due to distortion was unavoidable.

Further, in the case where a digital audio signal is mixed and recorded by using DAT, each digital audio signal to be mixed is converted into an analog signal when the sampling frequency and the synchronization method are different. It is necessary to mix from.

As described above, in order to prevent the performance deterioration due to the occurrence of clock jitter and the deterioration of the reproduced digital audio signal due to the different sampling frequencies and realize the digital mixing by the free sampling frequency conversion, the asynchronous sampling is used. It has been desired to develop a digital frequency converter.

Generally, this sampling frequency conversion device uses a resampling time address to specify a resampling point for resampling a signal input at a sampling frequency Fsi at a sampling frequency Fso. . This resampling time address is the ratio of the sampling frequency of the input signal (hereinafter referred to as the input sampling frequency) Fsi to the sampling frequency of the signal to be resampled (hereinafter referred to as the output sampling frequency) Fso. Is generated according to.

Specifically, the sampling frequency ratio R between the input sampling frequency Fsi and the output sampling frequency Fso is the cycle of the output sampling frequency Fso (hereinafter referred to as the output sampling cycle) Tso.
N times the cycle t (= N · Tso) of the input sampling frequency Fsi
M times the input reference clock (hereinafter referred to as the input master clock) MCKi (= M · Fsi) to detect the jitter components such as Fsi, MCKi, and Fso while averaging and removing them. The frequency ratio R and the resampling time are cumulatively added to generate the resampling time address. Then, the sampling frequency is converted by reading out the resampling point stored in the resampling buffer memory with the resampling time address.

[0008]

By the way, in order to perform more accurate sampling frequency conversion, that is, conversion for obtaining a resampling frequency using a resampling time address,
It is necessary to improve the resolution of the resampling time address. Therefore, it is conceivable to increase the magnification N to increase the detection cycle (time) t for detecting the sampling frequency ratio R of the input sampling frequency Fsi and the output sampling frequency Fso. However, in this case, in an application in which the input sampling frequency Fsi and the output sampling frequency Fso are varied, there is an inconvenience that an error is excessively generated between the value of the sampling frequency ratio R and the actual Fsi / Fso. Will occur.

Therefore, highly accurate sampling frequency conversion has been realized under the condition that the input sampling frequency Fsi and the output sampling frequency Fso are constant. However, in recent years when the diversification of the digital audio signal source is advanced, the input sampling frequency F as described above is used.
The condition that si and the output sampling frequency Fso are always constant narrows the range of application of the sampling frequency conversion device.

On the other hand, the input master clock MCKi
It is also conceivable to improve the resolution of the resampling time address without considering the shortening of the detection cycle t by increasing the. However, in this case, the problems of the limit of the circuit operation speed of the counter and the absorption and removal of the input clock jitter are raised. Therefore, it is impossible to simply increase the frequency of the input master clock MCKi to improve the resolution of the resampling time address.

The present invention has been made in view of the above circumstances, and adaptively switches between generation of a re-sampling time address at high speed or high accuracy in accordance with the sampling frequency ratio, and differs. An object of the present invention is to provide a sampling frequency conversion device capable of preventing deterioration of a reproduced audio signal due to a sampling frequency and realizing mixing by free sampling frequency conversion with a simple circuit configuration.

[0012]

A sampling frequency conversion device according to the present invention is a sampling frequency conversion device for converting a sampling frequency of an input signal into an arbitrary sampling frequency, and a storage means for storing the input signal. An interpolation processing unit that interpolates the signal read from the storage unit, and a sampling frequency ratio between the sampling frequency of the input signal and the arbitrary sampling frequency in a short time period and a long time period. Sampling frequency ratio detection means for detecting the sampling frequency ratio, and control means for controlling the storage means and the interpolation processing means in accordance with the sampling frequency ratio of the sampling frequency ratio detection means in a short time period or a long time period. The above problem is solved by having

In this case, the sampling frequency ratio detecting means determines whether or not the detected value in the short time period and the detected value in the long time period match within a predetermined accuracy,
It is also possible to select and output the detection value in the above long time period when they match and the detection value in the above short time period when they do not match.

The determination of coincidence or non-coincidence is performed by comparing the sampling frequency ratio in the short time period and the sampling frequency ratio in the long time period by the comparison means.
The determination within the predetermined accuracy can be performed by comparing the sampling frequency ratio in a long time period and the sampling frequency ratio in a short time period only within a predetermined digit range. For example, when treating the sampling frequency ratio as a digital value, from the most significant bit of the sampling frequency ratio with a large number of bits to a predetermined bit (for example, according to the total number of bits of the sampling frequency ratio with a small number of bits) , By comparing all bits of the sampling frequency ratio with a small number of bits.

The sampling frequency ratio detecting means is sufficiently fast with respect to the sampling frequency of one of the sampling frequency of the input signal and the arbitrary sampling frequency and the other sampling frequency. The sampling frequency ratio may be detected by counting the period of one of the sampling frequencies with a clock that is an integral multiple of.

Also, the interpolation processing means performs oversampling processing on the signal read from the storage means by the control means in accordance with the control signal supplied from the control means, so that the two adjacent processing means. It is preferable to obtain a piece of oversampling data and then perform linear interpolation processing on these two pieces of oversampling data.

Here, the two pieces of oversampling data obtained by the above-mentioned oversampling processing are obtained by the two acyclic filters.

Further, the control means supplies the re-sampling time address and the data write address, which are data read addresses, to the storage means. The control means supplies the interpolation processing means with a selection control signal of an oversampling coefficient used in the oversampling processing and linear interpolation coefficients for leading and trailing trailing used in the linear interpolation processing. ing.

When the sampling frequency of the input signal is higher than the arbitrary sampling frequency, it is preferable to limit the band of the output signal of the interpolation processing means.

[0020]

The sampling frequency ratio detecting means detects the sampling frequency ratio between the sampling frequency of the input signal and an arbitrary sampling frequency in a short time period and a long time period, respectively, and detects in a short time period. When the value and the detection value in the long time cycle match within a predetermined accuracy, the detection value in the long time cycle is selected, and when they do not match, the detection value in the short time cycle is selected and output to the control means. Therefore, when the sampling frequency ratio is large, that is, when the changing speed is large, the control means is fast based on the sampling frequency ratio in a short time period, and when the sampling frequency ratio is small, that is, when the changing speed is small, it is long. Highly accurate based on the sampling frequency ratio in the cycle,
The interpolation means is made to adaptively perform the interpolation processing. Therefore, the sampling frequency conversion device of the present invention can prevent deterioration of the reproduced audio signal due to different sampling frequencies and realize mixing by free sampling frequency conversion with a simple configuration.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the sampling frequency converter according to the present invention will be described below with reference to the drawings.

First, the first embodiment will be described with reference to FIG. The first embodiment is a sampling frequency conversion device that resamples the sampling frequency Fsi of the signal Dsi input from the input terminal 1 and converts it into a signal Dso of an arbitrary sampling frequency Fso. A completely asynchronous sampling frequency conversion process, that is, a sampling frequency conversion process with a free ratio having no synchronous relationship between input and output signals is realized. Hereinafter, the input sampling frequency Fsi of the input signal Dsi will be referred to as the input sampling frequency Fsi, and an arbitrary sampling frequency Fso will be referred to as the output sampling frequency Fso.

The sampling frequency conversion apparatus of the first embodiment has a re-sampling buffer memory 2 for storing an input signal Dsi having an input sampling frequency Fsi input from an input terminal 1.
An interpolating circuit 3 for interpolating the read signal from the re-sampling buffer memory 2, the input sampling frequency Fsi supplied from the input terminal 5, and the output sampling supplied from the input terminal 6. A sampling frequency ratio detection circuit 7 for detecting the ratio of the sampling frequency to the frequency Fso in a short time period and a long time period, and a sample of a short time period or a long time period of the sampling frequency ratio detection circuit 7. It has a controller 8 for controlling the resampling buffer memory 2 and the interpolation processing circuit 3 according to the digitized frequency ratio. The interpolation processing circuit 3 whose interpolation processing is controlled by the controller 8 is output from the output terminal 4. The signal Dso of the output sampling frequency Fso is output.

The sampling frequency ratio detection circuit 7 determines a sampling frequency ratio Rs and a sampling frequency ratio RL which are ratios of the input sampling frequency Fsi and the output sampling frequency Fso in a short time period ts and a long time period tL. It is detecting.

Then, the sampling frequency ratio detection circuit 7
Determines whether the sampling frequency ratio Rs at the short cycle ts and the sampling frequency ratio RL at the long cycle tL match or do not match within a predetermined accuracy, and when they match, at the long time cycle tL. The sampling frequency ratio RL to be detected and the sampling frequency ratio Rs to be detected in a short period ts when they do not match are selected and output to the controller 8.

The controller 8 generates a re-sampling time address, which is a data read address, according to the sampling frequency ratio RL or Rs supplied from the sampling frequency ratio detection circuit 7, and stores it in the re-sampling buffer memory 2. We are supplying.
In addition, the controller 8 has a resampling buffer memory 8
The data write address is also supplied to. In addition, the controller 8 selects the oversampling coefficient selection control signal used in the oversampling process performed by the interpolation processing circuit 3 according to the sampling frequency ratio RL or Rs, and the preceding reading signal used in the linear interpolation process. A linear interpolation coefficient for trailing trailing is generated and supplied to the interpolation processing circuit 3.

The interpolation processing circuit 3 reads a necessary data group from the resampling buffer memory 2 based on the resampling time address, and resampling is performed by, for example, a non-recursive (hereinafter referred to as FIR) filter processing. Two adjacent high-order interpolation data corresponding to the time address are created, and the respective data are linearly interpolated and then added to generate the signal Dso of the output sampling frequency Fso.

Here, the sampling frequency ratio detection circuit 7 determines whether the sampling frequency ratio Rs at the short cycle ts and the sampling frequency ratio RL at the long cycle tL match or do not match within a predetermined accuracy. For the following reason, it is determined that the sampling frequency ratio RL to be detected in the long time period tL is selected in the case of coincidence and the sampling frequency ratio Rs to be detected in the short period ts in the case of disagreement is selected and output to the controller 8. .

If the sampling frequency ratio of the input sampling frequency Fsi and the output sampling frequency Fso is detected in a short time period ts, the error Es becomes small as shown in FIG. 2A, and a high speed response to the error is possible. However, the resolution is small and it is difficult to obtain accuracy. On the other hand, the input sampling frequency F
If the sampling frequency ratio between si and the output sampling frequency Fso is detected in a long time period tL, the error EL becomes large as shown in FIG. 2B, and it is difficult to improve the response to the error, but the resolution is high. Can be large and highly accurate.
For the above reasons, the sampling frequency ratio detection circuit 7 determines whether or not the sampling frequency ratio Rs in the short time period ts and the sampling frequency ratio RL in the long time period tL match within a predetermined accuracy. , The sampling frequency ratio RL is selected when the values match, and the sampling frequency ratio Rs is selected when the values do not match, and the selected sampling frequency ratio Rs is output to the controller 8.

Here, the determination within the predetermined accuracy means that the sampling frequency ratio RL in the long time period tL and the short time period t.
This can be done by comparing the sampling frequency ratio Rs at s with a range of a predetermined number of digits. For example, when the sampling frequency ratio is treated as a digital value, a predetermined bit from the most significant bit of the sampling frequency ratio RL having a large number of bits (for example, according to the total number of bits of the sampling frequency ratio Rs having a small number of bits) Up to all the bits of the sampling frequency ratio Rs having a small number of bits.

Therefore, the sampling frequency conversion apparatus of the first embodiment adaptively switches the generation of the re-sampling time address according to the sampling frequency ratio between high speed and high precision, and performs sampling. When the frequency fluctuation does not occur within the predetermined accuracy, the sampling frequency conversion processing is performed according to the re-sampling time address generated with high accuracy, and the fluctuation of the sampling frequency occurs within the predetermined accuracy. Sometimes, the sampling frequency conversion process is performed according to the re-sampling time address generated at high speed. Therefore, the sampling frequency conversion apparatus according to the present embodiment can prevent deterioration of a reproduced audio signal due to different sampling frequencies and realize mixing by free sampling frequency conversion with a simple configuration.

Next, a second embodiment will be described with reference to FIGS. In the second embodiment as well, as in the first embodiment described above, the signal D input from the input terminal 11 is used.
A sampling frequency conversion device that resamples the sampling frequency Fsi of si and converts it into a signal Dso of an arbitrary sampling frequency Fso, and a sampling frequency conversion process in which the input / output system is completely asynchronous,
That is, the sampling frequency conversion processing of a free ratio having no synchronous relationship between the input and output signals is realized. Below, the input signal Dsi
The sampling frequency Fsi of is used as the input sampling frequency Fsi, and an arbitrary sampling frequency Fso is used as the output sampling frequency Fso.

The sampling frequency conversion apparatus of the second embodiment is 8Fs oversampling for oversampling the input signal Dsi of the input sampling frequency Fsi input from the input terminal 11 of FIG. 3 into 8Fsi for resampling. A filter 12, a re-sampling buffer memory 13 for writing and reading an input signal of 8 Fs by the 8 Fs oversampling filter 12, and an interpolation process for interpolating a read signal from the re-sampling buffer memory 13. An input reference clock (hereinafter, referred to as an input master clock) MCKi (= M · Fsi) that is an integral multiple of the sampling frequency Fsi supplied from the circuit 14 and the input terminal 22.
The sampling frequency with improved resolution by counting the cycle t (= N · Tso) N times the cycle of the output sampling frequency Fso (hereinafter referred to as the output sampling cycle) Tso supplied from the input terminal 23. A sampling frequency ratio detection circuit 24 for detecting the ratio in a short time period and a long time period, respectively,
A controller 25 for controlling the re-sampling buffer memory 13 and the interpolation processing circuit 14 according to the sampling frequency ratio of the sampling frequency ratio detection circuit 24 in the short time period or the long time period, and the interpolation processing by the controller 25. The sampling frequency of the output signal from the controlled interpolation processing circuit 14 is thinned out to obtain an output sampling frequency Fso which is, for example, 2, 4, 8 times, and one of them is provided by the multiplexer 19a.
Resampling frequency signal output circuit 1 switched and selected by
9 and a band limiting filter 2 for band limiting the output signal from the re-sampling frequency signal output circuit 19 and outputting the output signal Dso of the output sampling frequency Fso from the output terminal 21.
0 and.

8Fs oversampling filter 12
The digital signal having the sampling frequency of 8Fsi generated in (4) is input to the resampling buffer memory 13 as described above. The resampling buffer memory 13 is, for example,
It is a buffer RAM of 20 bits and 64 words, and has a buffer eight times the input sampling frequency time.

As shown in FIG. 4, the sampling frequency ratio detecting circuit 24 has an integral multiple of a short time period ts input from the input terminal 23a by the input master clock MCKi supplied from the input terminal 22. Sampling period Ns ・
A short cycle counter 30 for counting Tso, a latch 31 for latching the count output from the short cycle counter 30 based on the Ns · Tso, and an input master clock MCKi supplied from an input terminal 22 are input from an input terminal 23b. Multiple sampling period NL over a long time period tL
A long cycle counter 32 that counts Tso, a latch 33 that latches the count output from the long cycle counter 32 based on the above NL · Tso, and a comparison that compares the latch output of the latch 31 and the latch output of the latch 32. The circuit 34 and the selection circuit 3 for selecting and outputting any one of the latch outputs to the controller 25 according to the comparison result in the comparison circuit 34.
5 and.

The short cycle counter 30 counts Ns · Tso by the input master clock MCKi, and the count result is latched by the latch 31 to obtain the short cycle t.
The sampling frequency ratio Rs at s will be determined. Further, the long cycle counter 32 counts NL · Tso by the input master clock MCKi and the count result is latched by the latch 33, whereby the sampling frequency ratio RL at the long cycle tL is obtained. That is,
The latch cycle of the latch 31 is a short cycle ts, and the latch cycle of the latch 33 is a long cycle tL. The latch periods ts and tL are determined so that the error of the sampling frequency ratio RL in the conversion at the time when the maximum input / output sampling frequency ratio change rate is the maximum and the resolution of the sampling frequency ratio Rs match.

Here, the input master clock MCKi
Is a clock that is sufficiently fast for Ns.Tso and NL.Tso, and is an integral multiple M of the input sampling frequency Fsi as described above.

The comparison circuit 34 determines whether the sampling frequency ratio Rs and the sampling frequency ratio RL match or do not match within a predetermined accuracy. When the comparison circuit 34 determines that the sampling frequency ratio Rs and the sampling frequency ratio RL match or do not match, the comparison circuit 34 supplies a selection control signal according to the determination information to the selection circuit 35.

The selection circuit 35 selectively outputs the sampling frequency ratio Rs or the sampling frequency ratio RL from the latch 31 or the latch 33 according to the selection control signal supplied from the comparison circuit 34.

In the comparison in the comparison circuit 34, the sampling frequency ratio RL having a large number of bits and the sampling frequency ratio Rs having a small number of bits are compared. At the time of the comparison, For example, by comparing all the bits of the sampling frequency ratio Rs from the most significant bit of the sampling frequency ratio RL to a predetermined bit (corresponding to the total number of bits of the sampling frequency ratio Rs). By doing so, it is possible to discriminate between the coincidence and the disagreement within a predetermined range. When the comparison circuit 34 determines that the sampling frequency ratio RL and the sampling frequency ratio Rs match within a predetermined accuracy, the selection circuit 35 selects the sampling frequency ratio RL at the long cycle tL. The selection control signal for outputting is supplied. On the other hand, when the comparison circuit 34 determines that the sampling frequency ratio RL and the new sampling frequency ratio Rs do not match within a predetermined accuracy, the comparison circuit 34 sends the sampling frequency ratio Rs at the short cycle ts to the selection circuit 35. A selection control signal for selecting and outputting is supplied.

The selection circuit 35 receives the sampling frequency ratio RL at the long cycle tL or the sampling frequency ratio R at the short cycle ts according to the two selection control signals supplied from the comparison circuit 34.
It outputs s to the adder 36 of the controller 25.

The controller 25 cumulatively adds the sampling frequency ratios RL or Rs supplied from the sampling frequency ratio detection circuit 24 by using the adder circuit 36 and the flip-flop circuit 39, as shown in FIG. , The data read address of the resampling buffer memory 13 is generated. Further, the controller 25 uses the adder circuit 36 and the flip-flop circuit 39 to select and control the coefficient for oversampling to the interpolation processing circuit 14,
The linear interpolation coefficients LIP.FL and LIP.FT for leading and trailing trailing are generated.

These data read address, oversampling coefficient selection control signal and linear interpolation coefficient are
For example, the data of the upper bit range, the middle bit range, and the lower bit range of one data string is output from the controller 25.

Here, the flip-flop circuit 37 is D
It is preferably a flip-flop circuit, and a clock of 8 Fso is supplied from the input terminal 38 in accordance with the sampling frequency 8 Fso of the output signal of the second embodiment.
Of course, when the sampling frequency of the output signal is 4 or 2Fso, a clock of 4 or 2Fso is supplied. Further, an initialization signal is supplied from the input terminal 39.

The interpolation processing circuit 14, as shown in FIG.
An FIR filter (L) & × which performs over-sampling processing and linear interpolation on the data read from the resampling buffer memory 13 by the resampling time address which is the data read address supplied from the controller 25. LIP.F.L15 and FIR filter (T)
& × LIP.F.T17 and these FIR filters (L) & × LI
Coefficient ROM 1 for supplying coefficients for oversampling to the PFL 15 and FIR filter (T) & × LIP.F.T 17.
6 and an adder 18 for adding the output signal of the FIR filter (L) & × LIP.F.L15 and the output signal of the FIR filter (T) & × LIP.F.T17. Where the coefficient R
The OM 16 has, for example, 32 24-bit 7-word oversampling coefficients.

The operation of the interpolation processing circuit 14 will be described with reference to FIG. The resampling buffer memory 13 is
FIR filter (L) & × LIP.F.L15 and FIR based on the read address supplied from the controller 25
The filter (T) & × LIP.F.T17 is supplied with, for example, seven pieces of data for each Tsi / 8 as shown in FIG. FI
The R filter (L) & × LIP.F.L15 and the FIR filter (T) & × LIP.F.T17 are the resampling buffer memory 1
The coefficient ROM1 is added to, for example, 7 pieces of data supplied from
For example, 7 coefficients read from 6 are subjected to sum-of-products operation to generate data of 256 Fsi.

FIG. 5B shows two adjacent data of the 256 Fsi data. 5A,
The broken line surrounding area E1 shown in FIG. 5B is Tsi / 8, and the broken line surrounding area E2 shown in FIG. 5B is Tsi / 8.
It is two adjacent data of 256 Fsi at / 256 intervals.

Next, the FIR filter (L) & × LIP.F.L1
5 and FIR filter (T) & × LIP.F.T17 sets the linear interpolation coefficient supplied from the controller 25 to Tsi / 256.
After multiplying two pieces of data adjacent to each other with an interval, the data is added by the adder 18, and linear interpolation as shown in FIG. 5C is performed.

By repeating such oversampling and linear interpolation, the second embodiment produces the data Dso of the sampling frequency Fso as shown in FIG. 5D.

Here, the linear interpolation coefficient will be described. As linear interpolation coefficients, leading leading data coefficient LIP.FL and trailing follow-up data coefficient LIP.FL.
There is FT. These linear interpolation coefficients are generated by the controller 25 using lower data of the cumulatively added value, for example, 12 bits. Specifically, the trailing follow-up data coefficient LIP.FT is given by the lower 12-bit data, and the leading preceding data coefficient LIP.FL is given by the 1's complement of the lower 12 bits.

FIG. 5C shows data Dso obtained by multiplying the two data Dsa and Dsb at Tsi / 256 intervals in the broken line enclosing area E3 by the linear interpolation coefficient.

The data output from the interpolation processing circuit 14 is 8Fso data. This 8 Fso data is supplied to the resampling frequency signal output circuit 19. The resampling frequency signal output circuit 19 performs a thinning process on 8Fso, converts it to 4Fso or 2Fso, and outputs 8Fso, 4Fso or 2Fso.
One of Fso is switched and selected by the multiplexer 19a.

The band limiting filter 20 is a filter for preventing aliasing noise from occurring in the output data.
When the input sampling frequency FSi is higher than the output sampling frequency Fso, aliasing noise may occur. Therefore, the output signal from the multiplexer 19a is band-limited.

Therefore, the sampling frequency conversion apparatus of the second embodiment adaptively determines whether the response of generation of the re-sampling time address is highly accurate or high speed according to the sampling frequency ratio. , And when the sampling frequency does not fluctuate very much, highly accurate sampling frequency conversion is performed,
When the fluctuation of the sampling frequency is large to some extent, high-speed conversion of the sampling frequency is performed, and high-precision and high-speed response can be compatible with each other.

The re-sampling frequency conversion device according to the present invention can be provided with three or more re-sampling frequency ratio detection circuits to finely correspond to high accuracy and high-speed response.

Further, in the resampling frequency conversion apparatus according to the present invention, the sampling frequency ratio detecting circuit can be constructed as shown in FIG. An embodiment provided with a sampling frequency ratio detection circuit as shown in FIG. 6 will be described below as another embodiment. Since the other embodiments have a configuration in which only the sampling frequency ratio detection circuit is different from the sampling frequency conversion device of the second embodiment, the description of the other configurations will be omitted here.

In the other embodiment, in constructing the sampling frequency ratio detecting circuit, a short cycle counter and a long cycle counter are not provided separately as in the second embodiment, but a short cycle counter is used. With respect to the sampling frequency ratio Rs of the provided short-period sampling frequency ratio detection circuit 43, the addition circuit 44 for generating the re-sampling time address of the controller is shared in a time division manner to perform cumulative addition, and adaptively. Since the sampling frequency ratio Rn is obtained, the long cycle counter can be omitted.

That is, in the sampling frequency ratio detection circuit of the other embodiment, the sampling frequency Fsi of the signal input from the input terminal 42 is calculated by counting with the divided clock supplied from the clock frequency divider 41. The sampling frequency ratio Rs at the short cycle ts and the sampling frequency ratio Rs are cumulatively added by using the adder circuit 44 and the cumulative addition latch 45, and are counted by the long cycle latch 46 using the divided clock. The comparison circuit 47 detects whether or not the obtained sampling frequency ratio RL in the long cycle tL matches or does not match within a predetermined accuracy, and when the matching is found, the sampling frequency ratio RL in the long cycle tL is detected. The selection circuit 48 selects the sampling frequency ratio Rs at the period ts and outputs it to the controller. Where clock divider 4
Reference numeral 1 denotes a reference clock supplied from the input terminal 40 to divide the divided clock into a short cycle sampling frequency ratio detection circuit 4
3, cumulative addition latch circuit 45 and long cycle latch circuit 46
Is being supplied to.

Therefore, in this other embodiment, a long period sampling frequency ratio detection circuit having a long period counter is unnecessary, and the response of generation of the re-sampling time address according to the sampling frequency ratio is highly accurate. Mode or high speed is adaptively switched, high-precision sampling frequency conversion is performed when there is little fluctuation in sampling frequency, and high-speed sampling frequency is used when fluctuation in sampling frequency is large to some extent. Is being converted.

[0060]

The sampling frequency converter according to the present invention comprises:
In a sampling frequency conversion device for converting a sampling frequency of an input signal into an arbitrary sampling frequency, storage means for writing and reading the input signal, and interpolation processing means for interpolating the signal read from the storage means. , A sampling frequency ratio detecting means for detecting a sampling frequency ratio between the sampling frequency of the input signal and the arbitrary sampling frequency in a short time period and a long time period, respectively, and the sampling frequency ratio detecting means. Since it has a control means for controlling the storage means and the interpolation processing means according to each sampling frequency ratio of a short time period or a long time period, the re-sampling time address is generated according to the sampling frequency ratio. It is possible to adaptively switch between high speed and high precision. Therefore, it is possible to prevent deterioration of reproduced audio signals due to different sampling frequencies and realize mixing by free sampling frequency conversion with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a sampling frequency conversion device according to a first exemplary embodiment of the present invention.

FIG. 2 is a diagram for explaining detection of a sampling frequency ratio in a short cycle and detection of a sampling frequency ratio in a long cycle.

FIG. 3 is a block diagram showing a schematic configuration of a sampling frequency converter according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a schematic configuration of a sampling frequency ratio detection circuit and a controller of the sampling frequency converter of the second embodiment shown in FIG.

FIG. 5 is a diagram for explaining the operation of the interpolation processing circuit of the sampling frequency converter of the second embodiment shown in FIG.

FIG. 6 is a block diagram showing a schematic configuration of a sampling frequency ratio detection circuit of a sampling frequency conversion device according to another embodiment of the present invention.

[Explanation of Codes] 2 Resampling Buffer Memory 3 Interpolation Processing Circuit 7 Sampling Frequency Ratio Detection Circuit 8 Controller

Claims (5)

[Claims] 1. A sampling frequency conversion device for converting a sampling frequency of an input signal into an arbitrary sampling frequency, and a storage unit for storing the input signal, and an interpolation process for the signal read from the storage unit. Interpolation processing means, sampling frequency ratio detecting means for detecting a sampling frequency ratio between the sampling frequency of the input signal and the arbitrary sampling frequency in a short time period and a long time period, respectively, and the sampling frequency A sampling frequency conversion device comprising: a control means for controlling the storage means and the interpolation processing means in accordance with each sampling frequency ratio of the frequency ratio detection means in a short time period or a long time period. 2. The sampling frequency ratio detecting means determines whether or not the detected value in the short time period and the detected value in the long time period match within a predetermined accuracy, and when they match, the long value is detected. 2. The sampling frequency conversion device according to claim 1, wherein the detection values in the time period are selected and output when the detection values in the short time period are selected when they do not match. 3. The sampling frequency ratio detecting means is sufficiently fast with respect to the cycle of one of the sampling frequencies of the input signal and the arbitrary sampling frequency and the other sampling frequency. 2. The sampling frequency conversion device according to claim 1, wherein a cycle of the one sampling frequency is counted with a clock that is an integral multiple of. 4. The interpolation processing means performs an oversampling process according to a control signal supplied from the control means on a signal read from the storage means by the control means, thereby adjoining two of them. 2. The sampling frequency conversion device according to claim 1, wherein a plurality of oversampling data are obtained, and linear interpolation is performed on these two oversampling data. 5. The band limitation is applied to the output signal of the interpolation processing means when the sampling frequency of the input signal is higher than the arbitrary sampling frequency.
The sampling frequency conversion device described.