JPH05235698A - Sampling frequency converter - Google Patents

Abstract

PURPOSE:To coexist easy constitution with superior conversion accuracy in a sampling frequency converter to convert an input sample string to an output sample string asynchronous to it. CONSTITUTION:The input sample of sampling frequency fs1 supplied from digital equipment 10 is written on an asynchronous RAM buffer 22 after being eight times over sampled by an octuple over-sampling filter 20. The address in accordance with an input/output sampling frequency Fs measured by a sampling frequency ratio measuring means 30 of the input sample written on the asynchronous RAM buffet 22 is read out, and polynomial 7th-order interpolation by a polynomial 7th-order interpolation means 36 is applied to it, and furthermore, linear interpolation by a linear interpolation means 38 is applied to it, and it is converted to a sampling frequency fs2, then, it is inputted to digital equipment 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling frequency converter for converting an input sample sequence into an output sample sequence asynchronous with the input sample sequence, and has a simple structure and good conversion accuracy.

[0002]

2. Description of the Related Art Various sampling frequencies such as 32 kHz, 44.1 kHz, and 48 kHz are used in digital equipment such as digital audio equipment, and when equipment with different sampling frequencies are connected, the equipment on the sending side sends them. It is necessary to convert the sample sequence to the sampling frequency of the receiving device. For example, when dubbing a master recording recorded in the studio at a sampling frequency of 48 kHz for a CD (compact disc), it is necessary to convert the sampling frequency to 44.1 kHz.

Similarly, when digital devices which have the same sampling frequency but are driven by different master clocks are connected to each other, the sample sequence sent from the sending device is synchronized with the sampling frequency of the receiving device. It is necessary, and this also corresponds to the sampling frequency conversion in a broad sense. For example, the sampling frequency is 4
When reproducing a 4.1 kHz CD and dubbing it with a digital recording device with a sampling frequency of 44.1 kHz, if the CD player and the digital recording device are driven by different master clocks, the digital signal reproduced from the CD. Sampling frequency conversion is required to synchronize the sampling frequency with the sampling frequency of digital recording equipment.

As a conventional sampling frequency conversion method, there has been a method of once D / A converting an input sample string to return it to an analog signal, and again A / D converting it at the sampling frequency of the output sample string.

As another sampling frequency conversion method, there is a method of oversampling the input sample sequence at a sampling frequency of the least common multiple of the input sample sequence and the output sample sequence, and extracting the samples forming the output sample sequence from the oversampling. there were.

[0006]

The above-mentioned method of once D / A converting and then A / D converting again has a drawback that a quantization error becomes large because of requantization and distortion becomes large in the case of an acoustic signal. It was

Further, the method of oversampling the input sample sequence has a drawback that the device scale becomes large unless the ratio of the sampling frequencies of the input sample sequence and the output sample sequence is a simple integer ratio.

Therefore, the method based on this oversampling is improved so that the input sample sequence is oversampled by a multiple that does not increase the device size so much that the samples created by this oversampling are interpolated and output. A method of making a sample row was also considered. However, since this method uses linear interpolation, the conversion accuracy is poor and there is a drawback that distortion becomes large in the case of an acoustic signal.

The present invention intends to solve the above-mentioned drawbacks of the prior art and to provide a sampling frequency converter having both a simple structure and good conversion accuracy.

[0010]

The invention according to claim 1 is
Oversampling means for oversampling an input sample sequence, RAM, write control means for writing oversampling data output from the oversampling means to the RAM at a clock synchronized with the oversampling data, and the input sample Sampling frequency ratio measuring means for measuring the frequency ratio between the sampling frequency of the sequence and the sampling frequency of the output sample sequence, and for obtaining the interpolated data at two points before and after the output sample that realizes the measured sampling frequency ratio by polynomial interpolation. Read-out control means for reading out the oversampling data of the RAM from the RAM, and the read-out control means for the RAM
Polynomial interpolation means for obtaining the above-mentioned two-point interpolation data by polynomial interpolation based on the oversampling data read from, and the two-point polynomial interpolation data obtained by this polynomial interpolation are linearly interpolated to obtain the sampling frequency ratio. And a linear interpolation means for obtaining an output sample value to be realized.

According to a second aspect of the present invention, in the first aspect of the invention, the sampling frequency ratio measuring means is composed of a counter for counting a clock synchronized with the input sample sequence, The count value of the counter within a multi-word cycle is output as the sampling frequency ratio, and the read control means accumulates the count value of the counter for each output sample cycle into three sections. The upper data of the divided data is used as the read address data of the RAM, and the polynomial interpolation means sets the intermediate data of the divided bits of the integrated value into three sections by using the interpolation coefficient for the polynomial interpolation. The linear interpolation means divides the bits of the integrated value into three sections by using the stored address data of the ROM. And it is characterized in the use of lower data of that Tsu as coefficient data for the linear interpolation.

[0012]

According to the first aspect of the invention, the input sample sequence is oversampled by an appropriate multiple, and the samples created by this oversampling are interpolated by polynomial interpolation.
An output sample sequence is created by interpolating the samples created by this polynomial interpolation by linear interpolation.

According to this, the circuit scale can be reduced as compared with the case where the output sample string is created only by oversampling. Further, since the samples created by oversampling are not directly linearly interpolated but are interpolated by polynomial interpolation and then linearly interpolated, the conversion accuracy is improved. Moreover, the circuit scale can be reduced by using polynomial interpolation and linear interpolation as compared with the case where the same multiple is obtained by oversampling. In addition, this simplifies the configuration and achieves good conversion accuracy.

According to a second aspect of the present invention, the bits of the count value obtained by counting the clock synchronized with the input sample sequence within the multiple read period of the output sample sequence are divided into three sections, and the polynomial interpolation is performed from the top. R that stores the read address data of the RAM and the polynomial interpolation coefficient
Since it is used as the read address data of the OM and the coefficient data for the linear interpolation, the interpolation value can be easily generated.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below. First, the schematic configuration is shown in FIG. Here, the sampling frequency converter 12 converts the sampling frequency fs2 from the data output from the digital device 10 (for example, a digital audio reproducing device) operating at the sampling frequency fs1.
Digital device 14 (eg, digital audio recording device, digital audio
It shows the case of inputting to a mixer, etc.).

The data (input sample sequence) output from the digital device 10 is input to the sampling frequency converter 12 via the data input terminal 16 and digitally input.
The audio interface receiver 18 synchronizes the internal clock of the sampling frequency converter 12 with the input word clock (frequency is fs1).
Clock) and an input bit clock (clock of the minimum unit of input data (reproduction clock, etc.)), and a clock that is 256 times the input word clock is used in this embodiment. ) Is played.

The input sample sequence synchronized with the internal clock is the 8 × oversampling filter 20.
8 times oversampling is performed by the (oversampling means) and sequentially written in the asynchronous RAM buffer 22 (RAM). The write control means 24 controls this writing, and instructs a write address to the asynchronous RAM buffer 22 according to the input word clock.

The digital device 14 outputs an output word clock (sampling frequency fs2 clock used in the digital device 14) and an output bit clock (minimum unit clock used in the digital device 14), and the clock input terminal 26 , 28. The sampling frequency ratio measuring means 30 compares the sampling frequency fs1 on the input side with the sampling frequency fs2 on the output side, and outputs data indicating the sampling frequency ratio Fs.

The read control means 32 performs asynchronous R conversion on the 8-fold oversampling data necessary for producing an output sample sequence realizing the measured sampling frequency ratio Fs by interpolation.
Control to read from the AM buffer 22 is performed. It also outputs the read address of the inter-polynomial coefficient ROM and the coefficient for linear interpolation.

The interpolation calculator 34 is the asynchronous RAM buffer 2
Using the 8 times oversampling data read from No. 2, the polynomial interpolating means 36 finds two points of interpolated data before and after the target output sample by polynomial interpolation. Here, Lagrange 7th-order interpolation is used as the polynomial interpolation. Further, the linear interpolation means 38 linearly interpolates between these two points of polynomial (Lagrange) interpolation data to obtain a desired output sample value.

In this way, the output sample sequence sequentially output from the interpolation calculation section 34 at the sampling frequency fs2 synchronized with the digital device 14 is the data output terminal 40.
Output to the digital device 14 as it is, and the necessary processing is performed.

The process of the above sampling frequency conversion is shown in FIG. Shows the input sample sequence A1, A2, ..., which is to be converted into the output sample sequence a1, a2, .. There is.

Is 8 in the section of the input samples A4 and A5.
New sample A4-by double oversampling
, A4-2, ..., A4-7 are inserted at equal intervals to divide the section A4, A5 into eight. In this oversampling, all oversampling data are sequentially created and written in the asynchronous RAM buffer 22 regardless of the sampling frequency ratio.

Is the A4, A5 containing the target output sample a3 by using the oversampling data.
7 shows data obtained by performing Lagrange 7th-order interpolation on the section. Here, a case where one section of the oversampling data is divided into 128 equal parts by Lagrange 7th-order interpolation is shown. The actual calculation is the interpolation data A4-4-
1, A4-4-2, ..., A4-4-127 are not all calculated, but the data required for linear interpolation, that is, the output sample a3 of interest, is interpolated and interpolation data of two points before and after that (here Then A4-4-45, A4-4-46)
Only create. Note that which position the interpolation data is created is determined by the sampling frequency ratio Fs as described later.

Is Lagrange interpolation data A4-4-
45 shows data obtained by linearly interpolating the section 45, A4-4-46. Here, the case where two adjacent points of the Lagrange interpolation data are equally divided into 2 ¹¹ by linear interpolation is shown. The actual calculation is the interpolation data A4-4-4.
5-1, A4-4-45-2, ..., A4-4-45-
Instead of calculating all (2 ¹¹ -1), only the interpolation data of the target output sample a3 is created. The position of the interpolation data to be created depends on the sampling frequency ratio Fs as described later.

Through the above steps, the sample value of the output sample a3 can be obtained with high accuracy. The next output sample a4
Is obtained by obtaining the output sample at a time point 1 / fs2 away from the output sample a3 in the same manner as above.

Next, the sampling frequency converter 1 of FIG.
A specific example of No. 2 is shown in FIG. Each part of FIG. 3 will be described. (1) Control circuit 31 The control circuit 31 sends a control signal CONT to each part of the circuit of FIG. 3 to perform the control necessary for each part to perform a predetermined operation. In addition, the signal CONT 'from each part
Enter.

(2) Sampling frequency ratio measuring means 30 The sampling frequency ratio measuring means 30 comprises a free-run counter 42 of 22-bit word length, which measures the sampling frequency ratio Fs. The free-run counter means a circulation-type counter that performs free-run without resetting. The 22-bit counter 42 counts the input bit clock having a frequency of 256 times the input sampling frequency fs1,
The count number of the 22-bit counter 42 in the period synchronized with the output sampling frequency fs2 is measured. This count number increases as the input sampling frequency fs1 increases (or the output sampling frequency fs2 decreases), and decreases as the input sampling frequency fs1 decreases (or the output sampling frequency fs2 increases). The count number corresponds to the frequency ratio Fs of the sampling frequencies fs1 and fs2.

Here, in order to improve the measurement accuracy (resolution) of the sampling frequency ratio Fs, as shown in FIG. 4, a period as long as 8192 output word clocks is set as one measurement cycle, and the 22-bit counter 42 is provided during this period. The counted number is output as the average value of the sampling frequency ratio Fs during the period of the 8192 output word clock.

Specifically, this measurement is performed as follows. In FIG. 3, the count value of the 22-bit counter 42 is sequentially transferred to the registers 44 and 46 at every 8192 output word clock. The subtractor 48 subtracts the count values held in the registers 44 and 46 to determine the count number of the 22-bit counter 42 in the immediately preceding 8192 output word clock period as the sampling frequency ratio Fs.
Output as data. Therefore, the data of the sampling frequency ratio Fs is updated every 8192 output data words.

The data of the sampling frequency ratio Fs is supplied to the read control means 32 via the selector 60, and the read address of the asynchronous RAM buffer 22, Lagrange 7 is supplied.
It is used to determine the read address of the next interpolation coefficient ROM 86 and the linear interpolation coefficient _Coef .

By the way, when the sampling frequency ratio Fs changes drastically on the time axis for some reason, the sampling frequency ratio Fs is measured every 8192 output word clocks. However, the measured value cannot follow, and the accurate sampling frequency ratio Fs at that time cannot be shown. Therefore, in the asynchronous RAM buffer 22, there is a possibility that a read address may overtake or overtake a write address to cause a large noise.

As a solution to such a problem, the count value of the 22-bit counter 42 for each output word clock is sequentially stored in the RAM for the past 8192 times, and the present count value and the count before the 8192 output word clock are counted. A method is conceivable in which the difference from the value is sequentially obtained for each output word clock and is output as the sampling frequency ratio Fs at each time point. By doing so, a new sampling frequency ratio is obtained for each output word clock, so that the followability to changes in the sampling frequency ratio Fs is improved, but on the other hand, there is a drawback that a RAM having a very large capacity is required. is there.

Therefore, here, a method for improving the followability to the variation of the sampling frequency ratio Fs without using a RAM having a large capacity is proposed. As shown in FIG. 5, this means that the cycle of measuring the sampling frequency ratio Fs is 16
As the output word clock, the count value of the 22-bit counter 42 for each output word clock is sequentially stored in the RAM for the past 16 times, and the difference between the current count value and the count value 16 word clocks before is output for each output word. The clock frequency is sequentially obtained for each clock and is output as data of the sampling frequency ratio Fs at each time point.

In this way, a new sampling frequency ratio Fs is obtained for each output word clock, so that the measured value follows the fluctuations of the sampling frequency ratio Fs. Further, in this way, the time for averaging the sampling frequency ratio Fs becomes shorter (81
It seems that the resolution decreases at a glance because it changes from 92 output word clocks to 16 output word clocks. However, when the frequency ratio fluctuates, the shorter the averaging period, the stronger the fluctuation influence appears and the actual sampling. A measured value close to the frequency ratio Fs will be obtained. However, if the averaging time is too short, the effect of jitter will also occur.
A period called the output word clock is set.

The count value for the 16 (= 2 ⁴ ) output word clock is 2 ⁴ ÷ 2 ¹³ = 2 ^-9 compared to the count value for the 8192 (= 2 ¹³ ) output word clock. Therefore, to match the measurement value of the sampling frequency Fs with the 8192 output word clock,
At the time of measurement with the 16-output word clock, the value obtained by shifting up the output of the lower 13 bits of the 22-bit counter 42 excluding the upper 9 bits by 9 bits is set as the sampling frequency ratio Fs.

Sampling frequency ratio measuring means 30 of FIG.
Then, the measurement with 16-output word clock is performed as follows. The register 52 fetches the output of the lower 13 bits of the 22-bit counter 42 every one output word clock. In the RAM 54, the count value taken in the register 52 is sequentially written, and the past 1 is always seen from the present time.
The count value for 6 pieces is held. The subtractor 56 is RAM5
The difference between the oldest count value stored in 4 and the latest count value (that is, the number of counts within the period of 16 output word clocks) is obtained, and this is taken as the average value of the sampling frequency ratio Fs during this period. , Output for each output word clock. As a result, when the sampling frequency ratio Fs fluctuates, the measured value immediately following the fluctuation is obtained from the subtractor 56.

The variation of the sampling frequency ratio Fs is detected by
This is done as follows. The comparison unit 51 subtracts the measured value of the sampling frequency ratio Fs of 22-bit precision and the measured value of sampling frequency ratio of 13-bit precision updated for each output word clock, as shown in FIG. It is output as 13-bit difference data. The difference data has a small value when the fluctuation of the sampling frequency ratio Fs is small, and has a large value when the fluctuation is large.
Therefore, as shown in FIG. 6, the comparison unit 51 sets upper and lower thresholds 1 and 2, and normally measures the sampling frequency ratio Fs with 22-bit accuracy (that is, the selector 60).
To output 22-bit precision sampling frequency ratio measurement data. ), If the difference data exceeds the threshold value 1 (11 bits) in this state, it is determined that the fluctuation is large, and the measurement is switched from the 22-bit precision to the 13-bit precision (the selector 60 outputs the 13-bit precision sampling frequency ratio measurement data). Yes.). Then, when the difference data becomes equal to or less than the threshold value 2 (13 bits) during the measurement with 13-bit accuracy, it is determined that the fluctuation is small, and the 13-bit accuracy is returned to the 22-bit accuracy. In this way, the sampling frequency ratio Fs is measured with hysteresis. As a result, even if the sampling frequency ratio Fs continuously changes by using a variable pitch in the digital recorder, it is immediately switched to the 13-bit precision sampling frequency ratio with good tracking, and the distortion is slightly deteriorated. However, the generation of noise that adversely affects the hearing is suppressed.

The delay circuit 58 delays the sampling frequency ratio measurement value of 22-bit precision by 3 samples (= 8192 output word clock × 3). This is for reliably returning to a stable state and then returning to 22-bit precision after the sampling frequency ratio Fs has changed and switched from 22-bit precision to 13-bit precision. That is,
If the sampling frequency ratio Fs fluctuates while measuring with 22-bit precision, the effect immediately appears in the measurement value with 13-bit precision, so that the difference data becomes large and the measurement is immediately switched to 13-bit precision. On the other hand, when the sampling frequency ratio Fs returns to a stable state from the state of 13-bit precision measurement, the 13-bit precision measurement value immediately returns to a stable state, but the 22-bit precision measurement value is delayed. Since the circuit 58 is delayed by 3 samples, it does not return to the stable state immediately, and the difference data remains large during that time, and the 13-bit measurement is continued.
After three samples, the measurement value with 22-bit precision also returns to a stable state, the difference data becomes smaller, and the measurement with 22-bit precision is restored. In this way, the switching timing has a hysteresis. The delay time is not limited to 3 samples and can be set appropriately.

(3) Write control means 24 The write address counter 24 constitutes a write control means, and counts clocks whose frequency synchronized with 8 times oversampling data is 8 times fs1 and counts the same. The value is output as write address data. The write address data is sequentially supplied to the asynchronous RAM buffer 22 via the selector 62, and the input data that has been 8 times oversampled is sequentially written to the asynchronous RAM buffer 22. (4) Read Control Means 32 The measured sampling frequency ratio Fs indicates the interval at which the output sample sequence should be output with respect to the input sample sequence, so that it is used to read the asynchronous RAM buffer 22 and add interpolation coefficients. By doing so, an output sample sequence can be generated.

Therefore, the read control means 32 of FIG. 3 integrates the measurement data of the sampling frequency ratio Fs output from the sampling frequency ratio measuring means 30 for each cycle of the output sampling frequency fs2, and the integrated value. Is output as a base address data which is a combination of the read address data of the asynchronous RAM buffer 22, the read address data of the coefficient ROM for Lagrange 7th-order interpolation, and the linear interpolation coefficient data at every output sampling cycle. In this case, when the sampling frequency ratio Fs is measured with 22-bit accuracy, the measurement value is updated every 8192 output word clocks, and therefore the same measurement value is accumulated 8192 times until it is updated. Will be used. Also, 1
When measuring with 3-bit accuracy, the measured value is updated every output word clock, and thus the updated measured value is sequentially integrated.

The structure of the base address is shown in FIG. For the base address, as described above, the measured value of the sampling frequency ratio Fs of 22 bits (the measured value with 13-bit precision is set to 22 bits by adding 9 bits "0" to the lower) is output for each word clock. It is generated by integrating,
The whole consists of 25 bits. The measurement value of the sampling frequency ratio Fs is originally 81 times the input bit clock which is 32 (= 2 ⁵ ) times the 8 times oversampling data.
92 (= 2 ¹³ ) Since the value is counted over the output word clock, the value obtained by halving the base address is ¹⁸ times oversampling the input sample sequence and asynchronous R
It is associated with one sample stored in the AM buffer 22. Therefore, the upper 7 bits of the base address are read out from the asynchronous RAM buffer 22 (total 2 bits).
⁷ = 128 addresses) and the lower 18 bits are 8
It is used as data for interpolation that divides the ¹⁸ × oversampled sample into 2 ¹⁸ divisions. Here, of the 18-bit interpolation data, the upper 7 bits are used as the read address of the Lagrange 7th-order interpolation coefficient ROM 86 that divides the ⁷ × oversampled samples by 2 ⁷ = 128, and the lower 11 bits are used. It is used as a linear interpolation coefficient C _oef for dividing 2 ¹¹ = 2048 between two Lagrange 7th-order interpolated samples (see FIG. 2).

The generation of the base address by the read control means 32 is performed as follows. Sampling frequency ratio measuring unit 30 outputs sampling frequency ratio F
The measured value of s is input to one input end of the full adder 64 via the selector 62. The full adder 64 selects the integrated value up to the previous time stored in the register 66 from the selector 68.
Is input to the other input terminal via and the two inputs are added, and this is held in the register 66 as a new integrated value. This integration operation is performed for each output word clock. Register 66
The integrated value held in is transferred to the latch circuit 70 as a base address for each output word clock, and the upper 7 bits of the integrated value are used as a RAM read address in the selector 6
Is supplied to the asynchronous RAM buffer 22 via 2, and the middle 7 bits are the read address of the Lagrange interpolation coefficient ROM 86 and the lower 11 bits are the linear interpolation coefficient C.
It is supplied to the interpolation calculation unit 34 as _oef .

(5) Asynchronous RAM buffer 22 As shown in FIG. 8, the asynchronous buffer 22 is formed into a ring buffer having a total of 128 addresses, and 8 times oversampling data is sequentially written. The data required for interpolation are read out sequentially. In this case, the Lagrange 7th-order interpolation operation uses oversampling of a total of 8 samples of 4 samples before and after the target output sample, and the read address indicated by the upper 7 bits of the base address is, for example, The address of the oversampling data immediately before the target output sample shall be shown, and this address, 3 addresses before this and 4 addresses after that, total 8
The data of the samples are read sequentially to produce one output sample.

If there is no change in the input / output sampling frequency ratio Fs, the write address and the read address are kept at a constant distance, but when the input / output sampling frequency ratio Fs changes, the write address advances and the read is performed. In some cases, the address may overtake the address, or conversely, the write address may be delayed and overtaken by the read address. In either case, the data becomes discontinuous and becomes a large noise.

Therefore, here, guards are provided on both sides of the write address so as to be spaced apart from each other so that the address immediately before any of the addresses of the eight 8 times oversampling data read at the read address or the target output sample is obtained. By correcting the read address so that if the address of the 8-fold oversampling data enters the guard, it is forced to return to the outside of the guard, thereby preventing overtaking or overtaking and generating a large noise. To prevent.

The correction of the read address is performed as follows. The write address information output from the write address counter 24 and synchronized with the input side is converted into output side synchronization by the asynchronous address latch circuit 72. The asynchronous address latch circuit 72 is composed of latch circuits 74 to 76 connected in cascade in three stages, and sequentially transfers write address data by strobe signals 1 to 3 to synchronize with the clock on the output side.

The operation of the asynchronous address latch circuit 72 is shown in FIG. The strobe signal 1 for latching the latch circuit 74 is output at a timing synchronized with the input word clock. That is, the mask a for a predetermined period is started at the rising timing of the input word clock, the strobe signal 1 is output at the central portion thereof, and the write address information is latched in the latch circuit 74. The strobe signal 2 for transferring from the latch circuit 74 to the latch circuit 75 is output at the timing synchronized with the output word clock. That is, the mask b for a predetermined period is started at the rising timing of the output word clock, the strobe signal 2 is output at the central portion thereof, and the write address latched by the latch circuit 74 is transferred to the latch circuit 75. The strobe signal 3 is output at the rising timing of the output word clock and is transferred from the latch circuit 75 to the latch circuit 76. With this, the information of the write address is converted into the data synchronized with the output side.

The masks a and b are the latch circuits 74,
This is to prevent the latch timings of 75 from overlapping. That is, when the mask b is started during the period of the mask a, the mask b is not started, and the predetermined period t is longer than that.
The alternative mask b'is started at a timing delayed by one, and the strobe signal 2 is output at the center thereof. The mask a is a fixed mask which always starts at the rising edge of the input word clock.
Once the alternative mask b'is issued, the timings of the mask a and the mask b'are compared again, and when the mask b'is started during the period of the mask a, the mask b is not started and the next mask is started. Start b. In this way, the latch timing is transferred from the latch circuit 74 to the latch circuit 75 so that the latch timings do not overlap with each other, and the write address information correctly synchronized with the output word clock is obtained from the latch circuit 76.

In this way, when the asynchronous address latch circuit 72 obtains the information of the write address synchronized with the output side, the guard is created by using this as the reference address (virtual write address). That is, as shown in FIG. 8, an address 8 addresses backward from the reference address (slightly behind the actual write address) is set as the guard A, and further 48 addresses backward (56 addresses backward from the reference address). Is set as the guard B. Then, when the read address advances and approaches the write address and crosses the guard A, the read address is forcibly delayed by 4 addresses and exited from the guard A. When the read address is delayed and approaches the write address from the opposite direction and crosses the guard B, the read address is forcibly advanced by, for example, 4 addresses and is exited from the guard B. When the read address leaves the guards A and B due to the large correction values -4 and +4, a small correction is continuously performed at a rate of, for example, -1, +1 address for several output word clocks, and an intermediate address between the guards A and B is obtained. "1
27 ". In this correction operation, the read address is the guard A.
Or it is performed every time B is exceeded. By such a correction operation, the read address is stored between the guards A and B, and it is prevented that the write address is overtaken or overtaken, and large noise is prevented.

Although the output signal is distorted to some extent by the correction, it takes only 4 samples at maximum as compared with the case where the read address overtakes or is overtaken by the write address (jumps by 128 samples). Therefore, the distortion is negligible. Also, after correcting the four addresses once to avoid the read address from overtaking or overtaking the write address for the time being, the central address "127" is gradually increased (one address for several output samples). Since it is corrected toward, the distortion of the output waveform hardly occurs. In this way, the read address is corrected without significantly impairing the continuity of the waveform.

The above read address correction is performed in the read control means 32. In order to correct this read address, the read control means 32 uses the guard A, B creation register 78, the memory 80 for storing the values 8, 56 of the guards A, B, the large correction value +4, and the small correction of -4 addresses. It comprises a memory 82 for storing the values +1, -1 addresses. The correction of the read address by the read control means 32 is performed by the following procedure in response to a command from the control circuit 31. In this correction process, every time a new base address is held in the register 66 (that is, every time an output sample is generated), this base address is latched by the latch circuit 7.
It is performed within the period until it is transferred to 0.

I) Calculation of Guard A "8" is read from the memory 80 as a numerical value for creating the guard A, and is input to one input end of the full adder 64 via the selector 68. Further, the reference address obtained by converting the write address into the synchronization on the output side is input to the other input end of the full adder 64 via the selector 62. Full adder 64
Subtracts "8" from the reference address and guard A
The value is stored in the register 78 as the address of the.

Ii) Comparison of guard A and RAM read address The address of guard A held in register 78 is input to one input terminal of full adder 64 via selector 68. Further, the base address (all not only the upper 7 bits of the RAM read address portion but also the 25 bits) held in the register 66 is input to the other input end of the full adder 64 via the selector 62. Then, the full adder 64 performs an operation of (address of guard A)-(base address) on the corresponding bit. Bit comparator 8
Reference numeral 4 determines whether the result of this operation is positive or negative. When the result is negative, it is determined that the base address has crossed the guard A and is close to the write address, and the base address is corrected. That is, the correction value -4 is read from the memory 82, and the selector 6
It is input to one input terminal of the full adder 64 via 8. Further, the data (base address value) of the register 66 is input to the other input end of the full adder 64 via the selector 62. Then, the full adder 64 adds the correction value -4 to the data in the register 66 for correction, and holds the correction result in the register 66. In this way, the RAM read address (actually, the entire base address) is corrected, and the correction result is transferred from the register 66 to the latch circuit 70. When the calculation result is positive, it is transferred to the latch circuit 70 as it is without correction.

After a large correction of -4, a small correction value -1 is read from the memory 82 every time several output samples are generated, and the base address is corrected in the same manner. When the address “127” is gradually approached and the address “127” is reached or when the address “127” is exceeded, the correction process is ended. If the base address exceeds the guard again during the small correction, the correction is restarted from the correction with the large correction value.

Iii) Operation of Guard B "56" is read from the memory 80 as a numerical value for creating the guard B, and is input to one input end of the full adder 64 via the selector 68. Further, the reference address obtained by converting the write address into the synchronization on the output side is input to the other input end of the full adder 64 via the selector 62. Full adder 6
4 subtracts "56" from the reference address and holds the value in the register 78 as the address of the guard B.

Iv) Comparison of Guard B and RAM Read Address The address of the guard B held in the register 78 is input to one input end of the full adder 64 via the selector 68. Further, the base address (all not only the upper 7 bits of the RAM read address portion but also the 25 bits) held in the register 66 is input to the other input end of the full adder 64 via the selector 62. Then, the full adder 64 performs an operation of (base address)-(address of guard B) on the corresponding bit. Bit comparator 8
Reference numeral 4 determines whether the result of this operation is positive or negative. When the result is negative, it is determined that the base address has crossed the guard B and has approached the write address, and the base address is corrected. That is, the correction value +4 is read from the memory 82, and the selector 6
It is input to one input terminal of the full adder 64 via 8. Further, the data (base address value) of the register 66 is input to the other input end of the full adder 64 via the selector 62. Then, the full adder 64 adds the correction value +4 to the data in the register 66 for correction, and holds the correction result in the register 66. In this way, the RAM read address (actually, the entire base address) is corrected, and the correction result is transferred from the register 66 to the latch circuit 70. When the calculation result is positive, it is transferred to the latch circuit 70 as it is without correction.

After making a large correction of +4, a small correction value +1 is read from the memory 82 every time several output samples are generated, and the base address is corrected in the same manner. When the address “127” is gradually approached to reach the address “127”, or when the address “127” is exceeded, the correction process is ended. If the base address exceeds the guard again during the small correction, the correction is restarted from the correction with the large correction value.

(6) Interpolation Calculation Unit 34 The interpolation calculation unit 34 performs Lagrange 7th order polynomial interpolation and linear interpolation. The Lagrange 7th-order interpolation uses asynchronous RA by using an interpolation coefficient as shown in FIG.
8 times oversampling data A4, A4-1, A4- which are read from the M buffer 22 as shown in FIG.
2, ..., A4-7 are convolved with each other to generate interpolation data that divides each data into 128. However, here, only the calculation is performed to interpolate the output sample a3 required for the next linear interpolation and to obtain the interpolated data of two points before and after that (in this example, points A4-4-45 and A4-4-46). ..

The Lagrange 7th-order interpolation coefficient in FIG. 10A is a coefficient that zero-crosses from the center position to the left and right symmetrically at intervals of 8 times oversampling data, and here, at each of these intervals (total 8 sections). It is composed of 128 coefficients each (total of 128 × 8 sections = 1024 coefficients).

The calculation of the Lagrange interpolation value is first performed at point A4.
-4-45, followed by point A4-4
Do about -46. That is, first, point A4-4-4
5 is made to coincide with the center position of the coefficient in FIG. 10A, and each coefficient is convolved with each sample. In this case, 8 times oversampling data A4, A4-1, A4-2,
.., all 127 sample values that fill the space between A4 and 7 need to be treated as 0, so these do not have to be calculated, and in the end, eight samples A4, A4-1, which are 8 times oversampled A4-2, ..., A4-7 and the respective corresponding coefficients are multiplied by a total of eight times and added to obtain a point A4-.
The Lagrange 7th-order interpolation value of 4-45 is obtained.

When the interpolated value of the point A4-4-45 is obtained,
The sample A is shifted by 1 so that the point A4-4-46 coincides with the central position of the Lagrange 7th-order interpolation coefficient and corresponds to eight samples A4, A4-1, A4-2, ..., A4-7, respectively. The Lagrange 7th-order interpolated value of A4-4-46 is obtained by multiplying by 8 times and the coefficient.

Two points A4 sandwiching the target output sample
When the Lagrange 7th-order interpolated values of 4-45 and A4-4-46 are obtained, these are connected by a straight line as shown in FIG. 11, and the sample value X of the target output sample a3 is obtained by the linear interpolation. That is, assuming that the sample value of the point A4-4-45 is x1 and the sample value of the point A4-4-46 is x2, the sample value X of the output sample a3 is X = (x2-x1) C _oef + x1 where C _oef : _Calculated by linear interpolation coefficient. Here, the linear interpolation coefficient is the output sample point a
The position of 3 is a value indicating the position of the 2 ¹¹ division between the two points.

The Lagrange 7th-order interpolation and the linear interpolation operation by the interpolation calculation unit 34 of FIG. 3 will be described. The latch circuit 88 has eight samples A4 to be convolved.
A4-1, A4-2, ..., A4-7 are read from the asynchronous RAM buffer 22 and latched. Coefficient RO
The M86 has a Lagrange 7 as shown in FIG.
The next interpolation coefficient is stored. Interpolation is performed by the following procedure.

I) Calculation of Lagrange 7th-order interpolated value immediately before the target output sample The latch circuit 88 has eight samples A4, A4-1, A4-2, ..., A4-convoluted. 7 is sequentially read from the asynchronous RAM buffer 22 and latched. In addition, the latch circuit 90 first has a point A4-4-45.
The eight coefficient values required to obtain the Lagrange 7th-order interpolated value are sequentially read from the coefficient ROM 86 and latched by the coefficient ROM read address represented by the middle 7 bits of the base address. The coefficient ROM read address is the input sample A4, A4-1, A4-2, ...
The coefficient multiplied by A4-7 indicates what number of coefficients the Lagrangian 7th-order interpolation coefficient is divided into 128 between the zero-cross points (the same position is set between the zero-cross points). (See FIG. 10A)), 1
Eight coefficient values corresponding to one coefficient ROM read address are read out in time series (every time of multiplication and addition) and latched by the latch circuit 90.

That is, first, the sample A4 is read by the latch circuit 88, one coefficient by which the sample A4 is multiplied is read, and the selectors 92, 9 are respectively read.
They are mutually multiplied by the multiplier 96 via 4. The multiplication value is held in the register 104 via one input end of the register 98, the selector 100 and the adder 102. Subsequently, the latch circuit 88 reads the next sample A4-1, the latch circuit 90 reads one coefficient to be multiplied, and the multiplier 96 similarly multiplies the coefficient. This multiplication value is input to one input end of the adder 102 via the selector 100, and the previous multiplication value held in the register 104 is input to the other input end of the adder 102 via the selector 108 to perform addition. Both are added in the container 102,
The added value is held in the register 104. This multiplication and addition operation is performed for each sample A4, A4-1, A4-2.
The point A4-4-45 immediately before the target output sample a3 by repeating A4-7 eight times in total.
The Lagrange 7th-order interpolation value of FIG. 10B is obtained and stored in the register 106.

Ii) Operation of Lagrange 7th-order interpolated value immediately after the target output sample The latch circuit 88 has eight samples A4, A4-1, A4-2, ... A4-7 is sequentially read from the asynchronous RAM buffer 22 and latched. Further, in the latch circuit 90, the eight coefficient values necessary for obtaining the Lagrange's seventh-order interpolated value at the point A4-4-46 are next to the coefficient ROM read address represented by the middle 7 bits of the base address. Coefficient ROM 8 by address
The data is sequentially read from 6 and latched.

First, one sample A is provided in the latch circuit 88.
4 is read and is multiplied by the latch circuit 90 by 1
Two coefficients are read out and multiplied by each other in the multiplier 96 via the selectors 92 and 94, respectively. The multiplication value is held in the register 104 via one input end of the register 98, the selector 100 and the adder 102. Subsequently, the latch circuit 88 reads the next sample A4-1, the latch circuit 90 reads one coefficient to be multiplied, and the multiplier 96 similarly multiplies the coefficient. This multiplication value is input to one input end of the adder 102 via the selector 100, and the previous multiplication value held in the register 104 is input to the other input end of the adder 102 via the selector 108 to perform addition. Both are added in the container 102, and the added value is held in the register 104. This multiplication and addition operation is performed for each sample A4, A4-1, A4-2 ,.
The point A4-4-46 immediately after the target output sample a3 by repeating A4-7 eight times in total (see FIG. 10).
The Lagrangian 7th-order interpolation value of (b)) is obtained and held in the register 104.

The following method is conceivable as a method of reading from the coefficient ROM 86 each eight coefficient values required to obtain the Lagrange's seventh-order interpolated values immediately before and after the output sample. That is, the coefficient ROM 86
Does not store all the 1024 coefficients at the address in the same order, but stores them in the order of dividing the eight sections into 128. That is, 1024 coefficients are first divided into 128 groups having the same division position and arranged in the order of division positions, and further, eight coefficients constituting each group in each group are arranged in the order of sections in the coefficient ROM 86. Store at address.

Then, by using a 4-bit counter (referred to as a coefficient read counter) operating at a predetermined high-speed clock, the count value is added to the least significant bit of the middle 7-bit data of the base address, The added value is used as the read address of the coefficient ROM 86.

For example, if the medium 7-bit data of the base address is 00000001, Is used as a read address of eight coefficients for obtaining the Lagrange 7th-order interpolation value immediately before the target output sample. further, Is used as a read address of eight coefficients for obtaining the Lagrange 7th-order interpolation value immediately before the target output sample.

Since the interpolation coefficient in FIG. 10A is symmetrical with respect to the central position, the coefficient ROM 86 can be miniaturized by storing only the left and right halves in the coefficient ROM 86.

Iii) Two points A4-4-45 and A4- immediately before and after the target output sample a3 in the linear interpolation registers 106 and 104, respectively.
When the Lagrange 7th-order interpolation data x1 and x2 of 4-46 are held, linear interpolation is performed based on the data to obtain the sample value of the target output sample a3. This calculation is performed as follows.

First, the interpolation data stored in the register 106 is input to one input terminal of the adder 102 via the selector 100. Further, the interpolation data held in the register 104 is added via the selector 108 to the adder 10
It is input to the other input terminal of 2. The adder 102 subtracts both inputs to obtain x2-x1 and outputs the calculation result to the register 1
Hold at 04.

Subsequently, the subtracted value x2-x1 held in the register 104 is passed through the selectors 108 and 92 to the multiplier 9
6, the linear interpolation coefficient C _oef represented by the lower 11 bits of the base address is input to the multiplier 96 via the selector 94, and the multiplication of both is performed. The multiplication result (x2-x1) C _oef is held in the register 104 via the register 98, the selector 100, and the adder 102.

The calculated value (x2 held in the register 104
_-X1 ) _Coef is an adder 102 via the selector 108
It is input to one input terminal of. Further, the value x1 held in the register 106 is added via the selector 100 to the adder 10
It is input to the other input terminal of 2. The adder 102 adds both inputs and obtains a target output sample value X as X = (x2-x1) C _oef + x1. The obtained output sample value X is rounded by the rounding circuit 110, and the noise shaper 11
At 2, the quantization noise is driven to the high frequency range and output from the data output terminal 40. The above interpolation calculation is repeated for each output sample period within the output sample period.

As described above, the sampling frequency converter 12 of FIG. 3 converts the input data of the sampling frequency fs1 into the output data of the sampling frequency fs2 which is asynchronous with the input data. And according to such a configuration,
For example, if the word length of the input sample data is 22 bits, the coefficient word length of the Lagrange 7th-order interpolation is 25 bits, and the data length of the sampling frequency ratio Fs is 22 bits, a conversion error of about 20 bits is realized on the simulation. It was possible, and the distortion rate was improved compared to the conventional one.

[0078]

As described above, according to the invention described in claim 1, the input sample sequence is oversampled by an appropriate multiple, and the samples created by this oversampling are interpolated by polynomial interpolation. Since the output sample string is created by interpolating the samples created by the polynomial interpolation by the linear interpolation, the circuit scale can be reduced as compared with the case where the output sample string is created only by oversampling. Further, since the samples created by oversampling are not directly linearly interpolated but are interpolated by polynomial interpolation and then linearly interpolated, the conversion accuracy is improved. Moreover, the circuit scale can be reduced by using polynomial interpolation and linear interpolation as compared with the case where the same multiple is obtained by oversampling. In addition, this simplifies the configuration and achieves good conversion accuracy.

According to the second aspect of the present invention, the bit of the count value obtained by counting the clock synchronized with the input sample sequence within the multiple read cycle of the output sample sequence is divided into three sections, and the polynomial interpolation is performed from the top. R that stores the read address data of the RAM and the polynomial interpolation coefficient
Since it is used as the read address data of the OM and the coefficient data for the linear interpolation, the interpolation value can be easily generated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a sampling frequency conversion process by a sampling frequency converter 12 of FIG.

3 is a block diagram showing a specific configuration example of a sampling frequency converter 12 of FIG.

FIG. 4 is a time chart showing a measurement state with 22-bit accuracy by the sampling frequency ratio measuring means 30 of FIG.

5 is a conceptual diagram showing a measurement state with 13-bit accuracy by the sampling frequency ratio measuring means 30 of FIG.

FIG. 6 is a diagram showing a precision switching operation of sampling frequency ratio measurement by a comparison unit 52 in FIG.

7 is a diagram showing a configuration of a base address generated by the read control means 32 of FIG.

8 is a diagram illustrating a configuration of the asynchronous RAM buffer 22 of FIG. 3 and a relationship between a write address and a read address.

9 is an operation explanatory diagram of the asynchronous address latch circuit 72 of FIG.

10 is an explanatory diagram of an example of a Lagrange 7th-order interpolation coefficient stored in the coefficient ROM 86 of FIG. 3 and a convolution operation using the coefficient.

11 is an explanatory diagram of an operation of linear interpolation in the interpolation coefficient unit 34 of FIG.

[Explanation of symbols]

12 sampling frequency converter 18 8 times oversampling filter (oversampling means) 22 asynchronous RAM buffer (RAM) 24 writing control means 30 sampling frequency ratio measuring means 32 reading control means 36 polynomial interpolation means 38 linear interpolation means 42 22 bits Counter (counter)

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Koji Niimi 10-1 Nakazawa-machi, Hamamatsu-shi, Shizuoka Prefecture Yamaha Stock Company

Claims (2)

[Claims] 1. Oversampling means for oversampling an input sample sequence, RAM, and write control means for writing oversampling data output from the oversampling means to the RAM at a clock synchronized with the oversampling data. And sampling frequency ratio measuring means for measuring the frequency ratio of the sampling frequency of the input sample string and the sampling frequency of the output sample string, and two points of interpolated data before and after the output sample for realizing the measured sampling frequency ratio. Reading control means for reading out oversampling data for obtaining by polynomial interpolation from the RAM, and a polynomial interpolation procedure for obtaining the interpolation data of the two points by polynomial interpolation based on the oversampling data read from the RAM by the reading control means. When the polynomial interpolation data of two points obtained in this polynomial interpolation and linear interpolation, sampling frequency converter according to and a linear interpolation means for obtaining an output sample values for realizing the sampling frequency. 2. The sampling frequency ratio measuring means is composed of a counter that counts clocks synchronized with the input sample sequence, and the count value of the counter within the multiple word period of the output sample sequence is the sampling frequency ratio. The read control means uses, as read address data of the RAM, the upper data of the bits of the integrated value obtained by integrating the count value of the counter for each output sample period divided into three sections. The polynomial interpolating means uses middle-order data among the bits of the integrated value divided into three sections as address data of a ROM storing interpolation coefficients for the polynomial interpolation, and the linear interpolating means is , The lower-order data of the bit of the integrated value divided into three sections is the coefficient data for the linear interpolation. Sampling frequency converter according to claim 1, characterized by using as.