JPH03124139A - Data transfer system and timing controller - Google Patents

Abstract

PURPOSE:To optionally set a timing of data transfer and data transmission quantity and to provide the inexpensive system and equipment capable of performing both data serial transmission and high speed transmission by structuring properly an address information string generated from a main controller. CONSTITUTION:Sets of each address information fed from a main controller 101 are outputted from a timing controller 102 in a prescribed order and in a prescribed timing, and when sets comprising 1st and 2nd address information are integrated in an address information string, the data transmission from a transmitter 103 to a receiver 104 in the timing when the sets of the address information are outputted. When the address information string is configurated so that the sets comprising 1st and 2nd address information are outputted from the timing controller 102 repetitively at a prescribed period, the data transfer from the transmitter 103 to the receiver 104 is executed periodically. Moreover, when the address information string comprising the 1st and 2nd address information are outputted frequently, lots of data are sent from the transmitter 103 to the receiver 104 in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a data transfer system suitable for use in processing digital audio signals.

"Prior Art" Conventionally, as a data transfer method between digital devices, there has been a data transfer method using a serial data bus group and a matrix switch. This method, as shown in Figure 6,
Serial data bus group A.

~A7 and the serial data bus groups B0 to Bn are provided with a matrix switch 60, thereby appropriately setting the connection relationship between the two buses.

Furthermore, general-purpose computers and the like employ a data transfer method using a so-called VME bus.

This is an asynchronous bus that directly connects boards, and is configured so that the sending side waits until the receiving side confirms that the receiving side has completed data reception, thereby making it possible to transfer data with various data lengths.

"Problem to be Solved by the Invention" By the way, each of the above-mentioned methods had problems to be solved.

First, data transfer methods using serial data buses and matrix switches have the disadvantage that high-speed transmission is difficult due to serial data transmission) (
Furthermore, when the number of data buses is increased, the structure of the matrix switch 60 becomes complicated and expensive.

On the other hand, in the data transfer method using the VME bus,
Since the timing of data transfer is uncertain, when used for transferring real-time signals such as digital audio signals, the transferred data must always be corrected in real time, which is inconvenient.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a data transfer system and a timing control device that are inexpensive and enable both serial and high-speed data transmission.

"Means for Solving the Problem" In order to solve the above problem, in the invention recited in claim 1, as illustrated in FIG.
A transmitting device 103 transmits data when the second address information is supplied, and a receiving device 104 receives the data when the second address information is supplied, forming a set of two pieces of address information. Consisting of multiple pairs,
a main controller lO1 that generates an address information string including the first and second address information; and the main controller 10.
When the address information string is supplied from 1, each set of address information constituting this is sent to the transmitting device 103 and the receiving device 1 in a predetermined order and at a predetermined timing.
04.

In addition, in the invention recited in claim 2, as illustrated in FIG. When supplied, the first storage device 20 outputs the contents of the address specified by the address information.
1, a second storage device 202 that outputs the contents of the address specified by the address information when the address information is supplied; and a second storage device 202 that outputs the contents of the address specified by the address information; the first and second
switching means 2 that alternately supplies storage devices 201 and 202 of
04, and a data update means 205 for updating the contents of the first or second storage device 201 or 202 on the side to which the address information is not supplied.

"Operation" In the invention described in claim 1, each set of address information supplied from the main control device 101 is outputted from the timing control device 102 in a predetermined order and at a predetermined timing. Therefore, when a set of first and second address information is included in an address information string, data transfer from transmitting device 103 to receiving device 104 is executed at the timing when this set of address information is output.

Therefore, if an address information string is configured such that a set of first and second address information is repeatedly output from the timing control device 102 at a constant period, data transfer from the transmitting device 103 to the receiving device 104 can be performed periodically. is executed.

Furthermore, if the address information string is configured so that a set of first and second address information is output frequently, a large amount of data can be transmitted from the transmitting device 103 to the receiving device 104 in a short period of time.
can be transferred to.

As described above, in the present invention, by appropriately configuring the address information string generated by the main control device 101, the timing of data transfer and the amount of data to be transmitted can be arbitrarily set.

Further, in the invention described in claim 2, the address information generated by the address information generating means 203 is
The first and second storage devices 20 via the switching means 204
1.202 alternately. Then, the storage device to which the address information is supplied outputs data in accordance with the address information. On the other hand, the contents of the other storage device are updated by data updating means 205.

In this way, in the present invention, the address information generation means 203 controls the timing of data output from each storage device 201, 202, and the data update control 205 sets the data content. Since both parties control different storage devices instantaneously, there is no conflict between their control.

"Example" Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing the electrical configuration of the musical tone synthesis system according to the first embodiment of the present invention.

In the figure, 5.6.8.9 are an A/D module, a waveform storage module, a D/A module, and a DSP module, respectively, and are connected to a control bus 11, a data bus 2, and an address bus 3. Each of these modules is assigned a predetermined address number. When that address number appears on the address bus 3, the corresponding module inputs and outputs digital signals to and from the data bus 2. A main controller 11 includes a central processing unit, a storage device, etc. (not shown), and issues various instructions to each of the modules. The main controller 11 also supplies an address signal to the address bus 3 via the bus controller 10, thereby specifying a module to transmit data and a module to receive the data. A keyboard 12 inputs performance information to the main control device 11. Reference numeral 13 denotes an operation panel, which inputs various control signals to the main controller 11. The bus controller 10 generates a timing signal for input/output operations of each module, synchronizes the address signal supplied from the main controller 11 with this timing signal, and supplies it to the address bus 3.

Next, the functions of each module will be explained. When the A/D module 5 receives an audio signal from the microphone 4, it converts it into a digital signal and outputs it to the data bus 2. Also,
The waveform storage module 6 stores various musical instruments (e.g. piano,
Main controller 1
Based on the performance information supplied from 1, a musical tone signal is output. Further, the D/A module 8 converts the digital audio signal input via the data bus 2 into an analog audio signal, and outputs this to the audio system 7.

The audio system 7 amplifies the supplied analog audio signal and produces sound from the speaker 7a. Further, the DSP module 9 functions as a mixer equalizer or an effector by performing waveform synthesis and waveform processing using digital calculations.

Next, details of the bus controller 10 will be explained with reference to FIG. In the figure, 21 and 22 are RAMs (read/write storage devices), which are connected to address terminals ADD and 22, respectively.
It has a data terminal DATA, a select terminal, and a write terminal 7 below. In these RAMs, when a 0" level signal is supplied to the select terminal port and an "L" level signal is supplied to the write terminal WK, the contents of the address specified by the address signal are transferred to the data terminal DATA.
is output to. Furthermore, when signals of "0" level are supplied to both the select terminal and the write terminal 71, the contents of the data supplied to the data terminal DATA are written to the address specified by the address signal. Further, when the signals supplied to the select terminal and the write terminal τ1 are in a state other than the above, the data terminal DATA becomes a high impedance state, and data input/output is impossible.

Reference numerals 23 and 24 denote switching devices, which control each internally provided switch based on a control signal S from the RAM switching control circuit 25, and set the connection destination of each terminal of the RAMs 21 and 22. For example, in the illustrated state, each terminal of the RAM 21 is connected to the main controller 11 via each switch. Thereby, the main control device 11 can freely read and write to the RAM 21.

On the other hand, since a '0' level signal is always supplied to the select terminal of the RAM 22 and a '1' level signal is always supplied to the write terminal v1, the operation of the RAM 22 is limited to read operation. , address terminal A of RAM22
DD is connected to the output terminal of the counter 26, and the data terminal DATA is connected via a tri-state buffer 30 to the address bus 3 of the tone synthesis system f (see FIG. 2). As a result, the contents of the address specified by the output signal S of the counter 26 are read from the RAM 22, and the contents are supplied to the address bus 3.

On the other hand, when each switch inside the changeover device 23, 24 is switched to the opposite side from that shown in the figure, the state is reversed to the above. That is, the RAM 22 can be accessed and written to by the main controller 11, and the contents of the RAM 21 are supplied to the address bus 3 in accordance with the output signal of the counter 26.

27 is a timing generation circuit, which generates a control signal S for each time slot from a clock signal. is generated and supplied to the control lot l via the buffer 28. Here, a time slot is a unit of time for data transmission in the musical tone synthesis system shown in FIG. 2, and each module 5.6.8.9 performs an input/output operation for each time slot in accordance with the control signal Sc. (Details will be explained later). Further, the timing generation circuit 27 outputs a clock signal S for each time slot, and this is supplied to the counter 26.

The counter 26 is in the range from "0" to a predetermined number rNJ,
Repeatedly counts the clock signal S, and sends the counting result to the signal S.
, output as . The output signal S, as mentioned above, is R
It is supplied to the address terminal ADD of AM21 or RAM22. Then, when the count result of the counter 26 changes from rNJ to "0", the sample timing signal S4 is output.

Here, a sample is a unit of time for data transmission,
l samples equal rN+IJ time slots. Furthermore, l samples are also equal to the sampling period of each digital audio signal (details will be described later).

The sample timing signal S4 becomes a signal indicating a break between each sample. The sample timing signal S4 is sent to the control bus! via the buffer circuit 29. It is also supplied to the RAM switching control circuit 25.

The RAM switching control circuit 25 receives the sample timing signal S.
, outputs a control signal S that reverses the connection state of the switching devices 23 and 24. Therefore, R.A.
M21.22 are alternately connected to the main controller 1.
1 and its data contents are updated. Further, the RAM on the side not connected to the main controller 11 sequentially supplies its contents to the address bus 3 in accordance with the output signal S of the counter 26. The RAM switching control circuit 25 monitors input/output operations between the main control device 11 and the RAMs 21 and 22, and is configured not to output the control signal S during this input/output operation.

Next, the overall operation of this embodiment will be explained.

First, in FIG. 3, the main controller 11 writes data corresponding to the first sample (that is, data corresponding to the 0th to Nth time slots in the first sample) into the RAM 21. This data specifies the module that transmits data and the module that receives that data in each time slot. On the other hand, the counter 26 counts the clock signal S, and outputs the sample timing signal S4 when the count result changes from rNJ to "0". As a result, the RAM switching control circuit 25 switches the connection states of the switching devices 23 and 24 in the opposite direction to that shown in the drawing.

Next, the contents of the RAM 21 are sequentially read out according to the count result of the counter 26 and supplied to the address bus 3 via the tristate buffer 730.

On the other hand, data corresponding to the second sample is written into the RAM 22 from the main controller 11. And R.A.
When the reading of data from M21 is completed, the switch 23
．． The connection state of 24 is switched in the direction shown.

Thereafter, the output signal S of the counter 26 is generated in the same manner.

Accordingly, the contents of one of the RAMs 21 and 22 are read out and supplied to the address bus 3. Also, the other RA
Data corresponding to the next sample is written into M by the main controller 11, and this data is sent to the switch 23, 24.
The signal is supplied to the address bus 3 at the same time as the switching.

The signals supplied to address bus 3 are constantly monitored by each module 5.6.8.9 in FIG. Each module 5.6.8.9 performs a corresponding operation when that module is designated as an input end or an output end. The details will be explained with reference to FIG. Note that FIG. 5 is an explanatory diagram of the operation of this embodiment.

In FIG. 5, SA is a signal supplied to the address bus 3, which includes a sending address signal SAS and a receiving address signal SAR. Further, SL) is a signal supplied to the data bus 2. These signals are updated every l time slots. The module specified in a certain time slot of a certain sample of this sending address signal SAS is assumed to be a sending module 4. The transmitting module 41
In the illustrated example, it is either the A/D module 5, the waveform storage module 6, or the DSP module 9. Furthermore, the module specified by the reception address signal SAR in the same time slot is assumed to be the reception module 42. In the example of FIG. 2, the receiving module 42 includes:
D/A module 8, waveform storage module 6, or D
This will be one of the SP modules 9.

The transmitting module 41 sends its own address (the address assigned to the transmitting module 41) and the transmitting address signal SA! When a match with + is detected, digitized musical tone data is supplied to the data bus 2. On the other hand, the receiving module 42 receives its my address and the received address signal SA.
When a match with R is detected, data is read from the data bus 2. In this way, a transmitting module and a receiving module are set for every l time slots, and data is transferred between these modules. That is, within a period of l samples, it is possible to perform multiple data transmissions specifying various transmitting and receiving modules.

Here, if the time slot number for transferring data from the transmitting module 41 to the receiving module 42 is constant (in the example of FIG. 5, the fourth time slot in each sample), the interval at which the data is transferred is is equal to one sample. Therefore, if the data to be transferred is a digital audio signal, if the sampling period of the digital audio signal is set to the same time as one sample, the data can be transmitted in synchronization with the sampling period. For example, there is no need to perform time correction or the like in the module 42.

When transmitting a large amount of data in a short period of time to 42, multiple time slots within 1 sample may be used for transmission. Needless to say, such changes in transmission timing or transmission capacity can be made by changing the RAM 2 by the main controller 11.
This can be easily achieved by rewriting the contents of 1.22.

In this way, in this embodiment, the transmitting module, receiving module, transmission timing, and transmission capacity can be freely set even while the musical tone synthesis system is in operation.

Note that the present invention is not limited to the above embodiments,
Needless to say, various applications are possible. For example, the present invention can be applied to the audio system shown in FIG. In the figure, 46 is a disk control module, through which the hard disk 45
Data can be input and output to. Further, digital input/output is possible for a digital audio device 48 equipped with an input/output interface different from that of this audio system. Further, this system is provided with constituent elements (designated with the same reference numerals as in FIG. 2) corresponding to each part in FIG. 2. These components enable recording, processing, reproduction, etc. of audio signals.

"Effects of the Invention" As explained above, according to the present invention, it is possible to provide a data transfer system and a timing control device that are inexpensive and enable both serial and high-speed data transmission.

[Brief explanation of drawings]

Figures 1 (a) and (b) are block diagrams illustrating the configuration of the present invention, Figure 2 is a block diagram illustrating the configuration of an embodiment of the present invention, and Figure 3 is a block diagram of the main parts of Figure 2. , FIG. 4 is a block diagram of a modification of the embodiment, FIG. 5 is an explanatory diagram of the operation of the embodiment, and FIG. 6 is an explanatory diagram of the operation of a matrix circuit according to the prior art. 5...A/D module (transmission device), 8...
...D/A module (receiving device), 10...
...Bus controller (timing control device), l!・
...Main controller (data update means) 21...
...Read/write storage device (first storage device), 22
. . . Read/write storage device (second storage device), 23° 24 . . . Switcher (switching means), 25
...RAM switching control circuit (switching means), 26.
... Counter (address information generation means), 27.
... Timing generation circuit (address information generation means), 101 ... Main control device, 102 ...
- Timing control device, 103... Transmission device,
104... Receiving device, 201... First
storage device, 202...Second storage device, 20
3...Address information generation means, 204...
...Switching means, 205... Data updating means.

Claims (2)

[Claims] (1) A transmitting device that transmits data when first address information is supplied, and a receiving device that receives the data when second address information is supplied, forming a set of two pieces of address information. a main controller that generates an address information string that is made up of a plurality of address information sets and includes the first and second address information; a timing control device that supplies each set of address information to the transmitting device and the receiving device in a predetermined order and at a predetermined timing. (2) address information generating means that generates address information that circulates at a predetermined period; a first storage device that, when supplied with the address information, outputs the contents of the address specified by the address information; and the address a second storage device that outputs the contents of the address specified by the address information when the information is supplied; and a second storage device that outputs the contents of the address specified by the address information; Timing control characterized by comprising: switching means for alternately supplying the address information to storage devices; and data updating means for updating the contents of the first or second storage device to which the address information is not supplied. Device.