JPH04336826A - Information transmission system for dealing with high speed transmission line - Google Patents

Abstract

PURPOSE:To realize the start-stop synchronization transmission with small scale TTL circuit constitution when a terminal equipment with a low speed data transmission speed is connected to a high speed transmission line to carry out communication. CONSTITUTION:Let a transmission frequency of a high speed transmission line 22 be fH and a transmission frequency of a transmission/reception terminal equipment be fL, then an information transmission section 21 generates transmission information formed by adding a start stop bit to transmission information at an (N+2) bits controlled by an N-bit [N>=2fL/(fH-fL)] serial parallel converter 31 (synchronously with the frequency fL) and an (N+2)-bit parallel serial converter 32 (synchronously with the frequency fH) controlled by a timing generator 33 and sends the information to a transmission line 22. An information reception section 23 generates reception information formed by eliminating a start stop bit from the transmission information at an (N+2)-bit serial parallel converter 34 (synchronously with the frequency fH) and an N-bit parallel serial converter 35 (synchronously with the frequency fL) controlled by a timing generator 36. Thus, the information transmission with a very small signal delay time is realized while ensuring the consecutive bit information.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an information transmission system compatible with high-speed transmission lines, and is applied to digital line interfaces when connecting low-speed transfer rate information processing terminals to high-speed transmission lines such as LAN and ISDN. The purpose is to perform efficient information transmission using a simple and small-scale transfer rate conversion circuit.

0002

[Prior Art] Recently, OA and FA have been developed to improve the efficiency of clerical work in offices and productivity in factories.
In order to achieve this, LAN is increasingly being adopted as a means of communication between computers and terminals on the premises.
Also, ISDN, which comprehensively handles voice communication, data communication, and image communication, is beginning to become popular among public communication networks. The above-mentioned LAN and ISDN are digital transmission lines with high data transmission speeds [about several tens (K bits/second) to 100 (M bits/second)], and a large amount of data is transmitted between connected terminals. By transmitting information in a short time, extremely efficient communication is possible.

By the way, since the data transfer speed of a general data processing terminal such as a personal computer is lower than that of a high-speed transmission line such as a LAN, it is connected to the transmission line side through a digital line interface, and high-speed transmission is performed by that interface. Send/receive digital information while synchronizing with the roadside. In this case, the interface will transmit/receive serially transmitted information continuously or intermittently while detecting the status of the transmission line, but since there is no element for synchronization on the transmission line itself, In many cases, a transmission method (start-stop method) is used in which a start bit and a stop bit are added to separate information.

[0004] Therefore, in order to function as a so-called transceiver, the above-mentioned interface has a buffer memory and two units that execute information R/W to the memory while synchronizing with the transmission path side and the terminal side. It has a built-in transmitter and receiver.

[0005]

[Problem to be Solved by the Invention] However, in frequently used LANs, the information sent by each terminal often collides on the transmission path, and the above-mentioned It is necessary to provide a large capacity buffer memory. In addition, the memory has a high-speed R/W that can support the data transmission speed on the high-speed transmission line side.
Something with performance is required. As a result, the circuit scale of the digital line interface itself becomes large and the system becomes expensive.

Therefore, the present invention provides an information transmission method in which a digital line interface for synchronizing between a high-speed transmission line and a terminal can be constructed from an extremely simple transfer rate conversion circuit, and which can realize efficient start-stop communication. Created for the purpose of providing.

[0007]

[Means for Solving the Problems] The principle of the present invention is shown in Figs. is sent to the high-speed transmission line 3 while synchronizing with the data transmission speed of the high-speed transmission line 3, and the information receiving section 4
In the information transmission method, each terminal 2 receives the information from the high-speed transmission line 3 while synchronizing with the data transmission rate, converts it to a low data transfer rate, and sends it to the receiving terminal 5. , 5 data transfer frequency is f
When the data transmission frequency of the high-speed transmission line 3 is fH, the information sending section 1 receives N bits [however, N≧2・f
A serial/parallel converter 6 having a register of (N+2) bits, a parallel/serial converter 7 having a register of (N+2) bits, and an ST/parallel converter 7 for writing a start bit and a stop bit to the parallel/serial converter 7. SP writing means 8 is provided, and on the other hand, the information receiving section 4 has a serial-to-parallel converter 9 having an (N+2)-bit register, a parallel-to-serial converter 10 having an N-bit register, and a serial-to-serial converter 9 to write to the serial-to-parallel converter 9. ST/SP to remove embedded start and stop bits
A removing means 11 is provided, and when the digital bit information is transferred from the transmitting terminal 2 to the information transmitting section 1, the serial-to-parallel converter 6 in the information transmitting section 1 sequentially converts the serial to parallel converter 6 in synchronization with the fL clock of the transmitting terminal. Take in that bit information, ST/SP
Every time the writing means 8 detects that N bits of information have been transferred by referring to the fL clock, the N bits of information are latched in the parallel to serial converter 7, and the remaining 2 bits of the parallel to serial converter 7 are latched. The start bit and stop bit are written to the register of (N+
2) Bits of information are sent to the high-speed transmission line 3 in synchronization with the fH clock of the high-speed transmission line 3, and on the other hand, when the information receiving section 4 receives the information sent to the high-speed transmission line 3, , in the information receiving section 4, the serial-to-parallel converter 9 connects to the high-speed transmission line 3.
The bit information is sequentially fetched in synchronization with the fH clock of , and every time the ST/SP removal means 11 detects a stop bit, N bits of information excluding the start bit and stop bit at that time are converted into parallel to serial. 10, and the parallel-to-serial converter 10 sends out N bits of information to the receiving terminal 5 in synchronization with the fL clock of the receiving terminal 5. Regarding the method.

[0008]

[Operation] Since the information sending unit 1 takes in information in synchronization with the data transfer frequency fL of the sending terminal 2 side using the serial/parallel converter 6, the time for inputting N bits of information is N/fL, On the other hand, the parallel-to-serial converter 7 sends (N+2) bits of information, which is obtained by adding a start bit and a stop bit to the N-bit information, to the high-speed transmission line 3 in synchronization with the data transmission speed fH on the high-speed transmission line 3 side. The required time is (N+2)/fH. Here, in order to avoid bottlenecks in information transmission, the latter time must be shorter than the former time, and N/fL≧(N+2)/
The relationship fH must hold true. Therefore, from the relational expression, the condition N≧2・fL/(fH−fL) is determined, and the serial-parallel converter 6 must have an N-bit register that satisfies the above condition, and Naturally, the parallel-serial converter 7 has an (N+2) bit register. Although the parallel/serial relationship of each converter is opposite to the above, the same condition applies on the information receiving section 4 side, and the serial/parallel converter 9 is configured to have (N+2) bit registers connected in parallel/serial manner. The converter 10 consists of an N-bit register.

Next, the procedure and movement of information according to the system of the present invention will be explained with reference to FIGS. 1 to 4. First, when digital bit information D0 to DN-1 is sent from the transmitting terminal 2 to the information sending unit 1, the serial/parallel converter 6 synchronizes with the fL clock of the transmitting terminal 2 and transfers the information to the register. It is imported sequentially, and at the import stage, ST/S
The P writing means 8 refers to the fL clock of the sending terminal 2 and monitors the number of captured bits. When the ST/SP writing means 8 detects that N bits of information have been transferred to the serial/parallel converter 6, as shown in FIG. The data is latched in parallel to the register of the converter 7, and a start bit (ST) and a stop bit (SP) are written to the register for the remaining two bits of the parallel-to-serial converter 7 corresponding to the bits before and after the latched information.

After the above writing, the parallel-to-serial converter 7 immediately sends information to the high-speed transmission line 3 in order from the start bit in synchronization with the fH clock of the high-speed transmission line 3. The following information D'0 to D'N-1 is f
It is imported in synchronization with the clock of L, but fH>fL
Therefore, as shown in FIG. 2, the speed at which the signal is sent from the parallel-serial converter 7 to the high-speed transmission line 3 is faster than the speed at which it is taken into the serial-parallel converter 6. As a result, as shown in FIG. , and the information has already been taken into the serial/parallel converter 9 of the information receiving section 4. Note that the serial-parallel converter 9 takes in information in synchronization with the fH clock of the high-speed transmission line 3.

On the other hand, in the information receiving section 4, the start bit, the information D0 to DN-1, and the stop bit are taken into the serial/parallel converter 9 at the above-mentioned stage. The appearance of a stop bit is monitored, and when a stop bit is detected, only information D0 to DN-1 of the serial/parallel converter 9 is latched into the parallel/serial converter 10. That is, the start bit and stop bit are removed, and only text information D0 to DN-1 is latched as received information (see FIG. 3).

Thereafter, the parallel-to-serial converter 10 transfers the latched information D0 to DN-1 to the receiving terminal 5 in synchronization with the fL clock of the receiving terminal 5, as shown in FIG. The transfer is completed before the ST/SP removing means 11 detects the stop bit related to the following information D'0 to D'N-1. That is, the parallel-to-serial converter 7 of the information sending section 1 converts the start bit, the information D'0 to D'N-1, and the stop bit into serial-to-parallel signals in the information receiving section 4 via the high-speed transmission path 3 in the same manner as described above. The subsequent information D
The transfer is completed before '0 to D'N-1 are latched by the parallel-to-serial converter 10 to prepare for the next parallel latch.

[0013] Through the above procedure, the present invention enables smooth information transmission, but if the value of N is set to 2·fL
/(fH-fL), as shown in FIG.
Information D'0 to D' that follows at the timing when latched to
N-1 can be transmitted from the information sending section 1 side, and the most efficient information transmission without delay can be realized.

[0014]

[Embodiment] Next, an embodiment of the present invention will be described in detail using FIGS. 6 to 8. FIG. 6 shows a circuit diagram of an information sending section and an information receiving section of a transmitting/receiving transceiver when the present invention is applied to a LAN. In the same figure, 21 is an information transmitter to which a transmitter terminal (not shown) is connected, 22 is a high-speed transmission path, and 23 is an information receiver to which a receiver terminal (not shown) is connected. The low-speed information transferred from the terminal in synchronization with the transfer clock (frequency;
fH) is converted into high-speed information synchronized with the high-speed transmission line 22.
On the other hand, the information receiving unit 23 receives the high-speed information in synchronization with the transmission clock of the high-speed transmission line 22, and further transmits the received information to the transmission clock (frequency;
fL) is converted into low-speed information synchronized with fL) and transferred to the receiving terminal. In addition, in this example, the optimum example of the present invention is adopted, and there is a relationship of fH=2・fL, and N≧2
・Of the N that should satisfy the condition of fL/(fH-fL), N
A configuration in which the information transmitting section 21 and the information receiving section 23 are configured with =2 will be described.

[0015] In the above system, the information sending section 21
It is composed of a serial-parallel converter 31 composed of a 2-bit shift register, a parallel-serial converter 32 composed of a 4-bit shift register, and a timing generator 33. Here, the serial/parallel converter 31 takes in digital bit information transferred from the transmitting terminal from the terminal D in synchronization with the transfer clock (terminal CLK) of the transmitting terminal, and shifts the bit information to the terminals QA, Outputs in parallel to QB. The parallel-serial converter 32 has an input terminal SER,
A, B, C, D, output side terminal QD, control signal (SH/L
D signal) and a clock input terminal CLK, the terminal SER, A is always at "H", and the terminal D is always at "L".
”, and the QA of the above-mentioned serial-parallel converter 31
, QB outputs are input to terminals B and C, and the latch timing of the input signal is controlled by the SH/LD signal.
The input bit information of terminals A, B, C, and D is shifted in synchronization with the transmission clock of the high-speed transmission line 22 input to LK, but only the bit information of D after latching is transferred to the high-speed transmission line via terminal QD. output to 22. Further, the timing generator 33 refers to the transmission clock of the transmitting side terminal and the transmission clock of the high-speed transmission line 22, outputs the SH/LD signal to the parallel-to-serial converter 32 at a predetermined timing, and outputs the SH/LD signal to the parallel-serial converter 32.
2 controls the bit information latch and transmission output.

On the other hand, the information receiving section 23 includes a serial-parallel converter 34 composed of a 4-bit shift register, a parallel-serial converter 35 composed of a 2-bit shift register,
It consists of a timing generator 36. Here, the serial/parallel converter 34 takes in the digital bit information transmitted from the high-speed transmission line 22 from the terminal D in synchronization with the transmission clock (terminal CLK) of the high-speed transmission line 22, and shifts the bit information to the terminal D. Outputs in parallel to QA, QB, QC, and QD. The parallel-serial converter 35 has input terminals A and B.
, an output side terminal QB, an input terminal for a control signal (SH/LD signal), and a clock input terminal CLK. While the latch timing of the input signal is controlled by the LD signal, the input bit information of terminals A and B is shifted in synchronization with the transmission clock of the high-speed transmission line 22 input to the terminal CLK, but the bit information of B after latching is only is output to the receiving terminal via terminal QB. Further, the timing generator 36 monitors whether or not a stop bit is detected from the high-speed transmission line 22, and also monitors whether or not a stop bit is detected from the high-speed transmission line 22.
2 and the transmission clock of the receiving terminal, the SH/
The LD signal is output, and the latch and transfer output of bit information by the converter 35 is controlled.

Next, the transfer rate conversion operation involving the addition of start bits and stop bits by the information sending section 21 will be explained with reference to the timing chart shown in FIG. First, when the transmitting terminal transfers bit information in synchronization with its transfer clock, the serial/parallel converter 31 takes in the bit information from terminal D one bit at a time and shifts it to the register at each falling edge of the clock. I'll let it happen. Therefore, the next input bit information is output from the terminals QA and QB of the serial-to-parallel converter 31 at each falling edge of the clock.

Then, the timing generator 33 counts the transfer clock, and when it detects the fall of the transfer clock at the even count, it outputs an "L" signal corresponding to a half period of the transfer clock as the SH/LD signal. Output to parallel-serial converter 32. On the other hand, when the parallel-to-serial converter 32 receiving the SH/LD signal detects the rising edge of the transmission clock on the high-speed transmission line 22 within the time of the "L" signal, the terminal A becomes "H" and the terminal B , C and the QA and QB outputs of the serial-to-parallel converter 31 and terminal D.
L'' is latched in a register, and the bit information is shifted in synchronization with the transmission clock of the high-speed transmission line 22.

As a result, the terminal QD of the parallel-serial converter 32
The output is always (“L” corresponding to the start bit) →
It is repeated in the order of (digital information for two consecutive bits)→(“H” corresponding to a stop bit). That is, the information sending unit 21 configures the digital bit information transferred from the sending terminal in synchronization with a low-speed transfer clock (frequency: fL) into 4-bit units including a start bit and a stop bit, and sends it to the high-speed transmission line. High-speed transmission line 2 is synchronized with the high-speed transmission clock (frequency: fH) of 22.
2 in chronological order. In addition, in that case, the above-mentioned 4-bit information can be sent out continuously,
The phase difference between the input and output timings is also within a small phase delay range of one and a half cycles of fL.

Next, the transfer rate conversion operation involving the removal of start bits and stop bits by the information receiving section 23 will be explained with reference to the timing chart of FIG. First, when the bit information is sent from the information sending unit 21 to the high-speed transmission line 22, the serial-parallel converter 34 transfers the bit information to the high-speed transmission line 22.
In synchronization with the transmission clock No. 2, bit information is taken in from terminal D to the register one bit at a time at each rising edge of the clock and shifted. Therefore, the next input bit information appears at the terminals QA, QB, QC, and QD of the serial-to-parallel converter 34 every time the clock rises.

Here, the timing generator 36 monitors the signal input from the high-speed transmission line 22 to the terminal D of the serial/parallel converter 34, and when an "H" signal corresponding to a stop bit is detected, the timing generator 36 immediately An "L" signal corresponding to a half cycle of the transfer clock of the receiving terminal is outputted to the parallel-to-serial converter 35 as the SH/LD signal. On the other hand, the parallel-to-serial converter 35 that receives the SH/LD signal latches the QB and QC outputs of the serial-to-parallel converter 34 at that point in the register via terminals A and B, and transfers them to the receiving terminal. Shift in synchronization with the transfer clock. That is, at each terminal of the serial-parallel converter 34 at that time, an "H" signal corresponding to a stop bit is sent to terminal QA, consecutive 2-bit information is sent to terminals QC and QB, and a signal corresponding to a start bit is sent to terminal QD. “L”
“This means that a signal has appeared, but the parallel-to-serial converter 3
5 latches only the outputs of the terminals QC and QB, the start bit and stop bit are excluded, and only continuous 2-bit information is output from the terminal QB of the parallel-serial converter 35.

As a result, the information receiving section 23 automatically removes the start bit and stop bit from the 4-bit information transferred from the high-speed transmission line 22 in synchronization with the high-speed transfer clock (frequency: fH). , it becomes possible to transfer only text information to the receiving terminal in synchronization with the low-speed transfer clock (frequency: fL) of the receiving terminal. Further, the text bit information in this case can be transferred continuously, and the phase difference between the input and output timings is within the range of a small phase delay of two cycles of fL.

Therefore, the signal delay time between the transmitting terminal and the receiving terminal in this embodiment also remains extremely small, within four periods of fL. Further, each of the converters 31, 32, 34, and 35 used in this embodiment does not require a special circuit, and can use a shift register configured with a normal TTL circuit, and the number of bits thereof is also as described above. An extremely small one is sufficient.

[0024]

[Effects of the Invention] The present invention has the above-described configuration, so that when an information processing terminal with a low data transfer rate is connected to a high-speed transmission line such as a LAN or ISDN, a general-purpose TT
A digital line interface consisting of L circuits and the like and having an extremely small circuit scale enables start-stop synchronous transmission of digital bit information. Furthermore, if the data transfer frequency of each terminal on the transmitting side and the receiving side is fL, and the data transmission frequency of the high-speed transmission line is fH, then the serial-to-parallel converter in the information sending section is N[=2・fL/(fH -fL
)] bits, a parallel-to-serial converter is configured to (N+2) bits, and a serial-to-parallel converter in the information receiving section is configured to (N+2) bits.
By configuring parallel-to-serial converters for N bits, it is possible to realize information transmission with extremely small signal delay time while ensuring continuity of bit information.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of an information transmission method compatible with high-speed transmission lines according to the present invention, and also showing a state at a stage when digital bit information is transferred from a transmitting terminal to an information sending unit.

FIG. 2 is a diagram showing a state in which digital bit information is being transmitted from an information sending section to an information receiving section via a high-speed transmission path.

FIG. 3 is a diagram illustrating a state in which digital bit information is transmitted to an information receiving unit.

FIG. 4 is a diagram showing a state in which digital bit information is being transferred from an information receiving unit to a receiving terminal.

FIG. 5 is a diagram showing a state in which digital bit information is transmitted to an information receiving section when the number of bits of each converter is selected to an optimum value.

FIG. 6 is a diagram showing a circuit diagram of an embodiment when the present invention is applied to a LAN.

FIG. 7 is a signal timing chart showing the operation of the information sending section.

FIG. 8 is a signal timing chart showing operations on the information receiving section side.

[Explanation of symbols]

1... Information sending unit, 2... Sending side terminal, 3... High speed transmission path, 4
...Information receiving unit, 5...Receiving side terminal, 6, 9...Series parallel converter, 7, 10...Parallel serial converter, 8...ST/SP writing means, 11...ST/SP removing means, D0 to DN-1 ,D
'0~D'N-1...Digital bit information, fH...Data transmission frequency of high-speed transmission line, fL...Data transfer frequency of transmitting side terminal and receiving side terminal, ST...Start bit, S
P...stop bit.

Claims (1)

[Claims] Claim 1: An information sending unit sends digital bit information transferred from a sending terminal at a low data transfer rate to a high-speed transmission line while synchronizing with the data transmission rate of the high-speed transmission line; In an information transmission method in which the information is received from the high-speed transmission path while synchronizing with the data transmission speed, and the data is converted to a lower data transmission speed and sent to the receiving terminal, the data transfer frequency of each terminal is When fL is the data transmission frequency of the high-speed transmission line, and fH is the data transmission frequency of the high-speed transmission line, the information transmission section has N bits [however,
A serial-parallel converter having a register of N≧2・fL/(fH-fL)], a parallel-serial converter having a (N+2)-bit register, and an ST that writes a start bit and a stop bit to the parallel-serial converter.・Provide SP writing means,
On the other hand, the information receiving section includes a serial-parallel converter having an (N+2) bit register, a parallel-serial converter having an N-bit register, and removes the start bit and stop bit written in the serial-parallel converter. An ST/SP removal means is provided, and when digital bit information is transferred from the transmitting terminal to the information transmitting section, the serial/parallel converter in the information transmitting section sequentially converts the bits in synchronization with the fL clock of the transmitting terminal. The information is taken in, and the ST/SP writing means writes that fL.
Each time it detects that N bits have been transferred by referring to the clock of A bit is written, and the parallel-to-serial converter sends out the (N+2) bits of information to the high-speed transmission line in synchronization with the fH clock of the high-speed transmission line, while converting the information sent to the high-speed transmission line into information. When the receiving section receives the bit information, the serial/parallel converter in the information receiving section sequentially takes in the bit information in synchronization with the fH clock of the high-speed transmission line, and each time the ST/SP removing means detects the stop bit, the serial/parallel converter takes in the bit information. The N bits of information excluding the start bit and stop bit at the time are latched into the parallel-serial converter, and the parallel-serial converter transfers the N bits of information to the receiving terminal in synchronization with the fL clock of the receiving terminal. An information transmission method that supports high-speed transmission lines and is characterized by sending data to terminals.