JPH03124140A - Data transfer system - Google Patents

Abstract

PURPOSE:To optionally set a timing of data transfer, data transmission quantity, a single or plural receivers receiving the data and to provide the inexpensive system and equipment capable of both data serial transmission and high speed transmission by structuring properly an address information string generated from a main controller. CONSTITUTION:Sets of each information fed from a main controller 101 are outputted from a timing controller 102 in a prescribed order and in a prescribed timing, and when sets comprising transmission address information and 1st reception address information are integrated in an address information string, the data transmission from a transmitter 103 to a receiver 104 in the timing when the sets of the address information are outputted. When the address information string comprising the sets of the address information are configurated to be outputted frequency, lots of data are sent from the transmitter 103 to the receiver 104 in a short time. When sets comprising the transmission address information and 2nd reception address information are included in the information string, the data transfer from the transmitter 103 to the receiver 104 is executed. When sets comprising the transmission address information and group information are included in the information string, the data transfer from the transmitter 103 to the receivers 104, 105 is executed simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a data transfer system suitable for use in processing digital audio signals.

"Prior Art" Conventionally, as a data transfer method between digital devices, there has been a data transfer method using a serial data bus group and a matrix switch. This method, as shown in Figure 5,
Serial data bus groups A0 to An and serial data bus group B. -Bn, and a matrix switch 60 is provided between the buses and the buses, thereby appropriately setting the connection relationship between the two buses.

Furthermore, general-purpose computers and the like employ a data transfer method using a so-called VME bus.

This is an asynchronous bus that directly connects boards, and is configured so that the sending side waits until the receiving side confirms that the receiving side has completed data reception, thereby making it possible to transfer data with various data lengths.

"Problem to be Solved by the Invention" By the way, each of the above-mentioned methods had problems to be solved.

First, data transfer methods using serial data buses and matrix switches have the disadvantage that high-speed transmission is difficult because the source-to-destination transmission is performed serially.Furthermore, when the number of data buses is increased, The structure of the matrix switch 60 is complicated and has the disadvantage of being expensive.

On the other hand, in the data transfer method using the VME bus,
Since the timing of data transfer is uncertain, when used for transferring real-time signals such as digital audio signals, the transferred data must always be corrected in real time, which is inconvenient.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a data transfer system that is inexpensive and enables both serial and high-speed data transmission.

"Means for Solving the Problem" In order to solve the above problem, in the invention recited in claim 1, as illustrated in FIG. Transmitting device t l
03, and a first receiving device 1 that receives the data when first receiving address information or group information is supplied.
04, and a second receiving device 10 that receives the data when the second receiving address information or group information is supplied.
5, an information string consisting of a set of one address information and one group information, or two pieces of address information, and a plurality of these sets, the sending address information and the first receiving address information. , a main control device 101 that generates an information string including the second reception address information and the group information, and when the information string is supplied from the main control device lot, each piece of information constituting the information string is the transmitting device 103 in a predetermined order and at a predetermined timing for each group;
The first receiving device 104 and the second receiving device 10
5 and a timing control device 102 for supplying the same.

Further, in the invention set forth in claim 2, in the invention set forth in claim 1, when the timing control device 102 outputs the group information, the timing control device 102 generates an identification signal indicating the output of the group information. is supplied to the first and second receiving devices 104, +05, and the first and second
The receiving devices 104 and 105 are characterized in that they identify whether the supplied information is address information or group information using the identification signal.

"Operation" In the invention described in claim 1, each set of information supplied from the main control device 101 is output from the timing control device 102 in a predetermined order and at a predetermined timing. Therefore, when a set of sending address information and first receiving address information is included in an information string, data transfer from transmitting device 103 to receiving device 104 is executed at the timing when this set is output. Therefore, if the information string is configured such that the timing at which this set is output is repeated at a constant period, the transmitting device 103 can send the ! Receiving device 1
Data transfer to 04 is performed periodically. Furthermore, by configuring the information string so that this set is frequently output, a large amount of data can be transferred from the transmitting device 103 to the first receiving device 104 in a short time.

Furthermore, if a set consisting of the sending address information and the second receiving address information is included in the information string, the sending device 1
03 to the second receiving device 105 is executed.

Furthermore, when the set of transmission address information and group information is included in the information string, data transfer is executed from the transmission device +03 to the first and second reception devices 104 and 105 at the same time.

As described above, in the present invention, by appropriately configuring the information string generated by the main controller 101, the timing of data transfer, the amount of data to be transmitted, and the number of receiving devices that receive data can be adjusted. can be set arbitrarily.

Further, in the invention recited in claim 2, the first and second receiving devices 104.1
The type of information supplied to 05 (ie, address information or group information) can be easily determined.

"Example" (A) Configuration of example Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing the electrical configuration of a musical tone synthesis system according to an embodiment of the present invention.

In the figure, 5.6.8.9 is an A/D monoyl, a waveform storage module, a D/A module, and a DSP module, which are connected to a control bus 1, a data bus 2, and an address bus 3, respectively. Each of these modules is assigned a predetermined address number. When that address number appears on the address bus 3, the corresponding module outputs a digital signal to the data bus 2. Further, II is a main control device, which is equipped with a central processing unit, a storage device, etc. (not shown), and is a module that supplies address signals to the address bus 3 via the bus controller IO and thereby transmits data. , and the module that receives the data.

That is, the address bus 3 has two lines indicating a module that transmits data and a module that receives that data.
type of address information is provided.

Furthermore, in this embodiment, it is possible to set a plurality of modules that receive data. In this case, a group consisting of a plurality of modules is set in advance, and each module is made to store the group number to which the module belongs. The address bus 3 is supplied with address information indicating a module that transmits data and group information indicating a group number of a module that receives this data. When each module detects a match between its group information and a group number stored in advance, it performs a receiving operation (details will be described later).

I2 is a keyboard/operation panel, from which the main control bag RI l
Performance information, control signals, etc. are input to the controller.

The bus controller IO generates a timing signal for input/output operations of each module, synchronizes the address signal supplied from the main controller 11 with this timing signal, and supplies it to the address bus 3.

Note that the bus controller IO can be configured in various ways, but for example, in the patent application "Data Transfer System and Timing Control Device" dated the same day by the present applicant, there is an example in which the bus controller IO is configured using two RAMs. is listed.

Next, the functions of each module will be explained. When the A/D module 5 receives an audio signal from the microphone 4, it converts it into a digital signal and outputs it to the data bus 2. Also,
The waveform storage module 6 stores various musical instruments (e.g. piano,
The main controller l
! Based on the performance information supplied from the controller, a musical tone signal is output. Further, the D/A module 8 converts the digital audio signal input via the data bus 2 into an analog audio signal, and outputs this to the audio system 7.

The sound system 7 9 amplifies the supplied analog audio signal and produces sound. Furthermore, the DSP module 9 functions as a mixer, equalizer, or effector by performing waveform synthesis and waveform processing using digital calculations.

(B) Operation of the embodiment Next, the operation of this embodiment will be explained.

The operating modes of this embodiment include an l-to-l mode in which there is one module each for transmitting and receiving data, and a broadcast mode in which there is one module for transmitting data and multiple modules for receiving data. There is a mode.

(2) The operation in the ll vs. l mode vs. 1 mode will be explained with reference to FIG. 3(a).

In the figure, S^ is a signal supplied to the address bus 3, which includes a sending address signal SAS specifying a module to send data, a receiving address signal 5AIl specifying a module receiving this data, and an operation mode. It consists of a mode signal SAW. Here, when the value of the mode signal SAM is "1", the operating mode is the 1-to-1 mode, and when it is "0", the operating mode is the broadcast mode. In the illustrated example, since the value of the mode signal SAM is "1", the operation mode is the 1 vs. 1 mode. Further, So is a data signal supplied to the data bus 2.

The above-mentioned signals S As5S AR% S AM are supplied from the main control device 11 to the bus controller 10, and are supplied to the address bus 3 by the bus controller IO at every predetermined unit time. Hereinafter, 1, this unit time will be referred to as a time slot. Further, a time period in which a predetermined number of time slots are consecutive is called a sample. In the illustrated example, l samples are composed of the 0th time slot to the Nth time slot. Furthermore, l samples are set to be equal to the sampling period of the digital audio signal in the musical tone synthesis system (see FIG. 2).

Also, in a certain time slot, the transmission address signal S
The modimail designated by the AS is set as the sending module 41. In the example of FIG.
/D module 5, waveform storage module 6, or DS
P module 9. Furthermore, the module specified by the reception address signal SAR in the same time slot is assumed to be the reception module 42. In the example of FIG. 2, the receiving module 42 includes the D/A module 8,
This can be either a waveform storage module 6 or a DSP module 9.

When the transmitting module 41 detects a match between its own address (the address assigned to the transmitting module 41) and the transmitting address signal, SAS, the transmitting module 41 supplies the digitized musical tone data to the data bus 2.

On the other hand, the receiving module 42 reads data from the data bus 2 when detecting that the operation mode is the one-to-one mode and detecting a match between the my address and the received address signal SAR.

In this way, a transmitting module and a receiving module are set for each time slot, and data is transferred between these modules. That is, within a period of l samples, it is possible to perform multiple data transmissions specifying various transmitting and receiving modules.

Here, the time slot number for transferring data from the transmitting module 41 to the receiving module 42 is fixed (see Fig. 3).
In the example of (a), if the third time slot in each sample is used, the interval at which the transfer is performed becomes equal to l samples. That is, the timing of data transfer becomes equal to the sampling period of the digital audio signal. therefore,
For example, there is no need to perform time correction or the like in the receiving module 42.

On the other hand, when transmitting a large amount of data from the transmitting module 41 to the receiving module 42 in a short time, the data may be transmitted using a plurality of time slots in one sample.

In this manner, in the 1-to-1 mode, the transmitting module, receiving module, transmission timing, and transmission capacity can be freely set even while the musical tone synthesis system is in operation.

■Broadcast mode Next, the operation in broadcast mode is shown in Figure 3 (
b).

(i) In the initial setting operation diagram, a 16-bit broadcast register 42a is provided inside the receiving module 42, and its contents are first set by the main controller 11. The 0th bit to the 15th bit of the broadcast register 42a correspond to the 0th group to the 15th group, respectively, and indicate to the receiving module 42 whether or not it belongs to that group using negative logic. That is, each bit is
If the content is "0", it indicates that the receiving module 42 belongs to the corresponding group, and if the content is "1", it indicates that it does not belong to the corresponding group.

In the illustrated example, broadcast register 422
The Oth bit and the 15th bit of L are set to "0", and the other bits are set to "1". therefore,
It can be seen that the receiving module 42 belongs to the 0th group and the 15th group.

(11) Data transfer operation When the above initial settings are completed, the main controller II sends the address signal SAS, the receive group signal SAG, and the % mode signal SA to the address bus 3 via the bus controller IO.
M is supplied.

Here, the reception group signal SAG is a signal indicating a group of modules that receive data, and is composed of a 16-bit binary signal. The 0th bit to the 15th bit of the reception group signal SAG correspond to the Oth group to the 15th group, respectively, and indicate in negative logic whether a module belonging to the group receives data or not. In other words, if the content of each bit is 0, it indicates that the module in the corresponding group will receive data, and if it is "l", it indicates that it will not receive data. The first group signal SAG
Since 5 bits are set to "0" and the other bits are set to "1", it can be seen that the module belonging to the 15th group receives the data.

Next, one pair of transmitting modules 41! As in the case of the mode, the transmission address signal SAS and my address are compared, and if a match is detected, musical tone data is supplied to the data bus 2.

On the other hand, when the reception module 42 detects that the operation mode is the broadcast mode, it inputs each bit of the broadcast register 42a and the reception group signal SAG.
Calculate the logical OR with the bits of the same number, and at least 1
When the calculation result becomes "0", data is received from the data bus 2.

In the illustrated example, broadcast register 42
the 15th bit of a and the 1st bit of the receiving group signal SAG.
Since both 5 bits are “0”, the logical sum of the two is °
0'', and the reception module 42 executes data reception.

According to the above-described broadcast mode, the same group number can be set for the D/A module 8 and the DSP module 9 in FIG. 2, for example, so that they can perform reception operations simultaneously.

Therefore, the audio signal sampled by the A/D module 5 is transmitted to the audio system 7 via the D/A module 8.
It becomes possible to perform an operation such as recording a waveform in the DSP module 9 while emitting sound in one time slot.

(C) Modifications The present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made, for example, as described below.

■First Modification The present invention can be applied to the audio system shown in FIG. In the figure, 46 is a disk control module through which data can be input and output to the hard disk 45. Further, human output is enabled by inserting a digital I10 module 47 into a digital audio device 48 that is equipped with an input/output interface different from that of this audio system. Further, this system is provided with constituent elements (designated with the same reference numerals as in FIG. 2) corresponding to each part in FIG. 2. These components enable recording, processing, reproduction, etc. of audio signals. In the broadcast mode of this modification, for example, the digital musical tone signal input from the digital audio device 48 via the digital I10 module 47 is emitted via the D/A module 8 while the disk control module 46 An operation such as recording on the hard disk 45 can be performed in one time slot.

(2) Second Modification In the operation description in FIG. 3(b), each bit of the broadcast register 42a and the reception group signal SAG corresponded to one group. That is, if the number of bits was "16", a maximum of 16 types of groups could be set.

However, if it is necessary to set a large number of groups, the group number may be displayed in binary form consisting of 16 bits. In this case, a maximum of 2'8-65536 types of groups can be set.

■Third Modification In the explanation of the operation in FIGS. 3(a) and 3(b), the operation mode was set by the mode signal SAW.

However, without providing the mode signal SAM, it is also possible to distinguish the range of address information in the 1-to-1 mode and the range of group information in the broadcast mode within the set range of the received address information SAR. For example, if the received address signal SAR is composed of 16 bits, if its value is within the range of "0" to a predetermined number rMJ, it is considered a received address signal in l vs. l mode, and on the other hand, if its value is rM+ I J to r65535J
If it is within the range of , it may be used as a group signal in broadcast mode.

"Effects of the Invention" As explained above, according to the present invention, it is possible to provide a data transfer system that is inexpensive and enables both serial and high-speed data transmission.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the configuration of the present invention, FIG. 2 is a block diagram illustrating the configuration of an embodiment of the present invention, and FIGS. 3 (a) and (b) are diagrams explaining the operation of the embodiment, FIG. 4 is a block diagram of a modification of the above embodiment, and FIG. 5 is an explanatory diagram of the operation of a matrix switch according to the prior art. 5...A/D module (transmission device), 8...
...D/A module (first receiving device), 9...
・・・・DSP module (second receiving device), ■0・
...Bus controller (timing control device),
11... Main control device, 101... Main control device, 102... Timing control device, 10
3... Transmitting device, 104... First receiving device, 105... Second receiving device. Figure 1

Claims (2)

[Claims] (1) A transmitting device that transmits data when sent address information is supplied; a first receiving device that receives the data when first receiving address information or group information is supplied; and a second receiving address. a second receiving device that receives the data when information or group information is supplied; and an information string consisting of a set of one address information and one group information, or two pieces of address information, and a plurality of these sets. a main control device that generates an information string including the sending address information, the first receiving address information, the second receiving address information, and the group information; When the information string is supplied, each set of information constituting this is supplied to the transmitting device, the first receiving device, and the second receiving device in a predetermined order and at a predetermined timing. A data transfer system comprising: a timing control device; (2) When outputting group information, the timing control device transmits an identification signal indicating output of group information to the first
and a second receiving device, and the first and second receiving devices identify whether the supplied information is address information or group information using the identification signal. The data transfer system according to item 1.