JPH0795739B2 - Data transfer system - Google Patents

Description

TECHNICAL FIELD The present invention relates to a data transfer system suitable for use in processing a digital audio signal.

“Prior Art” Conventionally, as a data transfer method between digital devices, there has been a data transfer method using a serial data bus group and a matrix switch. This method, as shown in FIG.
Serial data bus group A _{0 to} A _n and serial data bus group
A matrix switch 60 is provided between B _{0 and} B _n to appropriately set the connection relationship between both buses.

In addition, a data transfer method using a so-called VME bus is adopted in general-purpose computers and the like. This is an asynchronous bus that directly connects the boards together and is configured to wait until the sender acknowledges that the receiver has received the data,
This makes it possible to transfer data having various data lengths.

[Problems to be Solved by the Invention] By the way, each of the above-mentioned methods has a problem to be solved.

First, in the data transfer method using the serial data bus group and the matrix switch, there is a drawback that high-speed transmission is difficult due to serial data transmission. Further, if the number of data buses is increased, the matrix switch There is also a drawback that the structure of 60 becomes complicated and expensive.

On the other hand, in the data transfer method using the VME bus, the timing of the data transfer is uncertain, so if it is used to transfer a real-time signal such as a digital audio signal, the transferred data will always be transferred in real time. It was inconvenient because it needed to be corrected.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data transfer system that is inexpensive and enables both serial transmission and high-speed transmission of data.

[Means for Solving the Problems] In order to solve the above problems, in the invention described in claim 1, as illustrated in FIG. 1, a transmission address indicating the address of the device on the transmission side. Address bus for passing information and received address information indicating the address of the receiving device
106, a data bus 107 for flowing data, a transmitter 103 for transmitting data to the data bus 107 when transmission address information is supplied from the address bus 106, and reception address information or reception group information from the address bus 106. Is supplied, a plurality of receiving devices 104 and 105 for receiving the data from the data bus 107, one transmission address information, and one reception address information or reception group information are set as one set, and a plurality of these sets are connected. When the main controller 101 generates an information sequence, and the information sequence is supplied from the main controller 101, each of the pieces of information constituting the information sequence is set in a unit in a predetermined order and at a predetermined timing.
The timing control device 1 that supplies the data to the transmitting device 103 and the plurality of receiving devices 104 and 105 by outputting to the 106.
It is characterized by having 02 and.

In the invention described in claim 2, in the invention described in claim 1, the timing control device 102 outputs the reception group information when outputting the reception group information. The identification signal shown is supplied to the plurality of receiving devices 104 and 105, and the plurality of receiving devices 104 and 105.
Is characterized by identifying whether the supplied information is receiving address information or receiving group information by the identification signal.

[Operation] In the invention described in claim 1, the sets of information supplied from the main control device 101 are output from the timing control device 102 in a predetermined order and at a predetermined timing.
Therefore, when a set of transmission address information and reception address information that specifies the receiving device 104 is included in the information string, data transfer from the transmitting device 103 to the receiving device 104 is executed at the timing when this set is output. Therefore, if the information sequence is configured so that the timing at which this set of information is output is repeated at a fixed cycle, the transmission device 103 can make the first
The data transfer to the receiving device 104 is periodically executed.
Further, if the information sequence is configured so that this set of information is output frequently, a large amount of data can be transferred from the transmitting device 103 to the first receiving device 104 in a short time.

In addition, when a set of transmission address information and reception address information designating the reception device 105 is included in the information string, data transfer from the transmission device 103 to the second reception device 105 is executed in the same manner as above.

In addition, when a set of transmission address information and reception group information is included in the information string, the transmission device can change the plurality of reception devices.
Data transfer is simultaneously executed to 104 and 105.

As described above, in the present invention, by appropriately configuring the information sequence generated by the main control device 101, the timing of data transfer, the amount of data transmission, and one or a plurality of receiving devices for receiving data. Can be set arbitrarily.

Further, in the invention according to claim 2, the type of information supplied to the first and second receiving devices 104 and 105 by the identification signal (that is, receiving address information or receiving group information) Can be easily discriminated.

[Example] (A) Configuration of Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing the electrical configuration of the musical sound synthesis system of an embodiment of the present invention.

In the figure, 5, 6, 8 and 9 are A / D modules,
A waveform storage module, a D / A module, and a DSP module, which are connected to the control bus 1, the data bus 2, and the address bus 3. A predetermined address number is assigned to each of these modules. When the address number appears on the address bus 3, the corresponding module inputs / outputs a digital signal to / from the data bus 2. Reference numeral 11 denotes a main control unit, which includes a central processing unit, a storage unit, and the like (not shown), supplies an address signal to the address bus 3 via the bus controller 10, and transmits a data by the module. , Which module will receive the data. That is, the address bus 3 is supplied with two types of address information indicating a module that transmits data and a module that receives the data.

Further, in this embodiment, a plurality of modules for receiving data can be set. In this case, a group composed of a plurality of modules is set in advance, and the group number to which the module belongs is stored in each module. Then, the address bus 3 is supplied with address information indicating a module that transmits data and group information indicating a group number of a module that receives this data. When each module detects a match between the group information and a group number stored in advance, each module performs a receiving operation (details will be described later).

A keyboard / operation panel 12 is used to input performance information, control signals, etc. to the main controller 11. Bus controller
Reference numeral 10 generates a timing signal for the input / output operation of each module, and supplies the address signal supplied from the main controller 11 to the address bus 3 in synchronization with the timing signal. Although the bus controller 10 can be configured by various methods, for example, in the patent application “data transfer system and timing control device” of the same applicant filed by the present applicant, an example in which two RAMs are used Is listed.

Next, the function of each module will be described. A / D module 5
When an audio signal is input from the microphone 4, the audio signal is converted into a digital signal and output to the data bus 2. Further, the waveform storage module 6 stores musical tone waveforms of various musical instruments (for example, piano, harpsichord, etc.) and outputs a musical tone signal based on the performance information supplied from the main controller 11.
The D / A module 8 also converts a digital audio signal input via the data bus 2 into an analog audio signal,
This is output to the sound system 7. The acoustic system 7
The supplied analog audio signal is amplified and sounded. Further, the DSP module 9 functions as a mixer, an equalizer, or an effector by performing waveform synthesis and waveform processing by digital calculation.

(B) Operation of Embodiment Next, the operation of this embodiment will be described.

The operation mode of this embodiment is a one-to-one mode in which there is one module for transmitting and receiving data, and a broadcast in which there is one module for transmitting data and a plurality of modules for receiving data. There are modes.

One-to-One Mode The operation in the one-to-one mode will be described with reference to FIG.

In the figure, S _A is a signal supplied to the address bus 3, and a transmission address signal S _AS that specifies a module that transmits data, a reception address signal S _AR that specifies a module that receives this data, and an operation mode It consists of the designated mode signal S _AM . Here, when the value of the mode signal S _AM is "1", the operation mode is the one-to-one mode, and when it is "0", the operation mode is the broadcast mode. In the illustrated example, since the value of the mode signal S _AM is "1", the operation mode is the one-to-one mode.
Further, S _D is a data signal supplied to the data bus 2.

The signals S _AS , S _AR , and S _AM described above are supplied from the main controller 11 to the bus controller 10, and are supplied by the bus controller 10 to the address bus 3 at every predetermined unit time. Hereinafter, this unit time is referred to as a time slot. A sample is a time when a predetermined number of time slots are continuous. In the illustrated example, one sample consists of the 0th time slot to the Nth time slot. Also,
One sample is set to be equal to the sampling period of the digital audio signal in the tone synthesis system (see FIG. 2).

Also, in a certain time slot, the transmission address signal S
_The module designated by _AS is the transmission module 41.
The transmission module 41 is either the A / D module 5, the waveform storage module 6, or the DSP module 9 in the example of FIG. Further, the module designated by the reception address signal S _AR in the same time slot is set as the reception module 42. The receiving module 42 is either the D / A module 8, the waveform storage module 6, or the DSP module 9 in the example of FIG.

The transmission module 41 receives its own address (the address assigned to the transmission module 41) and the transmission address signal S.
_When a match with _AS is detected, digitized tone data is supplied to the data bus 2.

On the other hand, the reception module 42 detects that the operation mode is the one-to-one mode, and when it detects the match between the my address and the reception address signal S _AR, it reads the data from the data bus 2.

In this way, the transmission module and the reception module are set for each time slot, and data is transferred between these modules. That is, it is possible to perform a large number of data transmissions in which various transmission and reception modules are designated within one sample period.

Here, the time slot number for transferring the data from the transmission module 41 to the reception module 42 is fixed (Fig. 3 (a)).
In the above example, if the time slot is the third time slot in each sample), the transfer interval is equal to one sample. That is, the timing of data transfer becomes equal to the sampling period of the digital audio signal. Therefore, in the receiving module 42, there is no need to perform time correction or the like at all.

On the other hand, when transmitting a large amount of data from the transmitting module 41 to the receiving module 42 in a short time, a plurality of time slots in one sample may be used for transmission.

As described above, in the one-to-one mode, the transmitting module, the receiving module, the transmission timing and the transmission capacity can be freely set even during the operation of the musical sound synthesizing system.

Broadcast Mode Next, the operation in the broadcast mode will be described with reference to FIG.

(I) Initialization Operation In the figure, a 16-bit broadcast register 42a is provided inside the receiving module 42, and its contents are first set by the main controller 11. The 0th bit to the 15th bit of the broadcast register 42a correspond to the 0th group to the 15th group, respectively, and indicate with negative logic whether or not the receiving module 42 belongs to the group. That is, each bit indicates that the receiving module 42 belongs to the corresponding group if the content is “0”, and indicates that the receiving module 42 does not belong to the corresponding group if the content is “1”.

In the illustrated example, the 0th bit and the 15th bit of the broadcast register 42a are set to "0", and the other bits are set to "1". Therefore, it can be seen that the receiving module 42 belongs to the 0th group and the 15th group.

(Ii) Data transfer operation When the above-mentioned initialization is completed, the main controller 11 sends a transmission address signal to the address bus 3 via the bus controller 10.
S _AS , a reception group signal S _AG and a mode signal S _AM are supplied.

Here, the reception group signal S _AG is a signal indicating a group of modules for receiving data, and is composed of a 16-bit binary signal. And the reception group signal S _AG
0th bit to 15th bit of
Corresponding to the 15th group, whether or not the modules belonging to the group receive data is displayed in negative logic. That is, each bit indicates that the module of the corresponding group receives the data when the content is “0”, and indicates that the module does not receive the data when the content is “1”. In the illustrated example, the 15th bit of the reception group signal S _AG is "0".
, The other bits are set to “1”, the 15th
It can be seen that the modules belonging to the group receive the data.

Next, the transmission module 41 compares the transmission address signal S _AS with my address as in the case of the one-to-one mode,
When a match is detected, the musical tone data is supplied to the data bus 2.

On the other hand, when the reception module 42 detects that the operation mode is the broadcast mode, the reception module 42 calculates the logical sum of each bit of the broadcast register 42a and the bit of the same number of the reception group signal S _AG , and at least one calculation result is obtained. When it becomes “0”, data is received from the data bus 2. In the illustrated example, the broadcast register 42
Since the 15th bit of a and the 15th bit of the reception group signal S _AG are both "0", the logical sum of them is "0",
Data reception is performed in the reception module 42.

According to the above-mentioned broadcast mode, for example, the same group number can be set in the D / A module 8 and the DSP module 9 in FIG. 2 and these can be made to perform the receiving operation at the same time. Therefore, it is possible to perform an operation in which the sound signal sampled by the A / D module 5 is recorded by the DSP module 9 while the sound system 7 outputs the sound signal through the D / A module 8 in one time slot. Becomes

(C) Modifications It is needless to say that the present invention is not limited to the above embodiments, and various modifications can be made, for example, as described below.

First Modification The present invention can be applied to the audio system shown in FIG. In the figure, reference numeral 46 denotes a disk control module, through which data can be input / output to / from the hard disk 45. In addition, the digital I / O module 47 is provided for the digital audio device 48 having an input / output interface different from that of the audio system.
Input and output are possible by inserting the. Further, the present system is provided with constituent elements (corresponding to the same reference numerals as those in FIG. 2) corresponding to the respective portions in FIG. Then, these components enable recording, processing, reproduction and the like of audio signals. In the broadcast mode of this modification, for example, a digital musical sound signal input from the digital audio device 48 via the digital I / O module 47 is output via the D / A module 8 while the disk control is performed. An operation such as recording to the hard disk 45 via the module 46 can be executed in one time slot.

Second Modification In the operation description of FIG. 3B, each bit of the broadcast register 42a and the reception group signal S _AG is 1.
It corresponded to the group. That is, the number of bits is "16"
If so, it was possible to set up to 16 types of groups.

However, when it is necessary to set a large number of groups, the group number may be displayed as a 16-bit binary. In this case, a maximum of 2 ¹⁶ = 65536 types of groups can be set.

Third Modification In the operation description of FIGS. 3A and 3B, the operation mode is set by the mode signal S _AM .

However, without providing the mode signal S _AM , the range of the address information in the one-to-one mode and the range of the group information in the broadcast mode can be divided within the set range of the reception address information S _AR . For example, if the received address signal S _AR is composed of 16 bits,
When the value is within the range of "0" to the predetermined number "M", it is the reception address signal in the one-to-one mode. On the other hand, when the value is within the range of "M + 1" to "65535", it is the broadcast mode. May be the group signal in.

[Advantages of the Invention] As described above, according to the present invention, it is possible to provide a data transfer system which is inexpensive, enables both serial transmission and high-speed transmission of data, and can effectively utilize the bus. You can

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the configuration of the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIGS. 3 (a) and 3 (b) are operation explanatory diagrams of the embodiment. FIG. 4 is a block diagram of a modified example of the above-described embodiment, and FIG. 5 is an operation explanatory diagram of a matrix switch according to the prior art. 5 ... A / D module (transmitter), 8 ... D / A module (first receiver), 9 ... DSP module (second receiver), 10 ... bus controller (timing controller) , 11 ... Main controller, 101 ... Main controller, 102 ...
... Timing control device, 103 ... Transmitting device, 104 ... First
Receiving device, 105 ... Second receiving device.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junichi Fujimori 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha stock company (72) Inventor Takeshi Funada 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha stock company

Claims (2)

[Claims] 1. An address bus for transmitting transmission address information indicating an address of a transmission side device and reception address information indicating an address of a reception side device, a data bus for transmitting data, and transmission address information from the address bus. A transmitter that transmits data to the data bus when supplied, a plurality of receivers that receives the data from the data bus when received address information or reception group information is supplied from the address bus, and one transmission A main control device that generates address information and one reception address information or reception group information as one set, and generates an information sequence formed by connecting the plurality of sets, and when the information sequence is supplied from the main control device, By transmitting each piece of information forming this to the address bus in a predetermined order and at a predetermined timing in units of one set, the transmission is performed. Data transfer system characterized by comprising a device, and a timing controller for supplying to said plurality of receiving devices. 2. The timing control device, when outputting the reception group information, supplies an identification signal indicating the output of the reception group information to the plurality of reception devices, and the plurality of reception devices are provided with the supplied information. The data transfer system according to claim 1, wherein whether the received address information or the received group information is identified by the identification signal.