JPH088756A - High speed serial transmitting method and device - Google Patents

Abstract

PURPOSE:To perform a serial transmission of digital data at high speed without changing the form of a batch of signals. CONSTITUTION:Serial data is divided into plural data in a transmission order by shift registers 1 and 2 and a simultaneous transmission is performed for the plural data via plural lines. On a reception side, plural received data are converted into one data by a serial/parallel converter 7. Therefore, data can be transmitted at high speed without changing the transmission rate a batch of signals, without changing the format of data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed serial transmission method and apparatus for digital data.

[0002]

2. Description of the Related Art There are serial transmission and parallel transmission as methods for transmitting digital data. The former is for sequentially transmitting data on one line, and the latter is for simultaneously transmitting 8-bit data on eight data lines. The latter has a high transmission speed, but has a problem of cost because it requires at least one line for synchronizing the transmission timing of each data in addition to the eight data lines. In addition, the former requires only one data line, so that there is no cost, but there is a problem that the transmission speed is slow.

FIG. 4 is a circuit diagram showing a conventional hardware configuration for serial transmission. Reference numeral 11 is a shift register for outputting input parallel data one by one at each arrival of a clock pulse, and 12 is data. A line driver for transmission, a line receiver 13 for receiving the transmitted data, and a serial / parallel conversion circuit 14 for returning serial data to original parallel data.

FIG. 5 shows the format of the data Tx to be transmitted. First, there is a start bit, then the 8-bit data of D0 to D7 which are the contents of the data, and the parity for error detection, and It consists of a stop bit that indicates the end of the transmitted data. Conventionally, in order to serially transmit such data,
The one signal Tx is transmitted in a time division manner.

[0005]

However, in the above-mentioned prior art, since the data to be serially transmitted is a single signal, even if the frequency of the clock pulse is increased, delays and noises are transmitted in the case of long distance transmission. Therefore, the transmission speed was limited. Therefore, it is an object of the present invention to perform high-speed serial transmission of digital data without changing the form of a single signal.

[0006]

In order to solve the above-mentioned problems, the high-speed serial transmission method of the present invention divides serial data into a plurality of transmission orders and simultaneously transmits them through a plurality of lines. A plurality of received data are converted into one data by serial / parallel conversion.

The high-speed serial transmission device of the present invention is
A means for allocating serial data to a plurality in the order of transmission, a plurality of lines for transmitting the allocated data,
It is provided with a serial / parallel conversion means for converting a plurality of received data into one original data.

[0008]

[Operation] Serial data is divided into multiple pieces and transmitted simultaneously,
By converting into one data on the receiving side, one data can be transmitted at high speed without changing the format of the data.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A concrete embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a hardware circuit diagram showing the configuration of an embodiment of the present invention. In FIG. 1, 1 and 2 are shift registers, 3 and 4 are line drivers, 5 and 6 are line receivers, and 7 is a serial / parallel conversion circuit. The operation of the serial transmission circuit configured as above will be described.

First, the data to be transmitted is divided into two data lines, that is, odd data and even data by using a CPU or the like, and the odd data is output to the shift register 1 and the even data is output to the shift register 2. . For example, assuming that transmission data has 1 bit for start and stop, 8 bits for data, and 1 bit for parity, as shown in FIG.
Bit data D1, third bit data D3, fifth bit data D5, seventh bit data D7, and stop are written. The data Tx2 of the shift register 2 writes 0th bit data D0, 2nd bit data D2, 4th bit data D4, 6th bit data D6, and parity.

In the shift registers 1 and 2, the transmission clock C
Line drivers 3 and 4 from the lower data sequentially by LK
To the line receivers 5 and 6. The data timings transmitted from the line drivers 3 and 4 from Tx1 and Tx2 are as shown in FIG. The serial / parallel conversion circuit 7 converts the thus transmitted Tx1 and Tx2 into parallel data. For example, by using a shift register as shown in FIG. 3, the frequency of the shift clock pulse is doubled, serial data is input every 2 bits, and shifts every 2 bits to convert it into parallel data. Can be realized.

As described above, in the embodiment, the transmission rate can be doubled by dividing the transmission into two. Also, in this example, an example in which the data is divided into two and transmitted is shown, but it is also possible to divide and transmit into three or more in the same manner.

[0013]

As described above, according to the present invention, it is possible to perform high-speed data transmission without changing the data format without changing the data transmission speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a specific embodiment of the present invention.

FIG. 2 is an output timing chart of transmission data.

FIG. 3 is a circuit diagram showing an example of a serial / parallel conversion circuit.

FIG. 4 is a configuration diagram of a conventional example.

FIG. 5 is an output timing chart of transmission data of a conventional example.

[Explanation of symbols]

1, 2 shift register, 3, 4 line driver,
5, 6 line receiver, 7 serial / parallel conversion circuit

Claims (2)

[Claims] 1. Serial data is divided into a plurality of transmission orders and simultaneously transmitted via a plurality of lines, and on the receiving side,
A high-speed serial transmission method characterized by converting a plurality of received data into one data by serial / parallel conversion. 2. A means for distributing serial data into a plurality of transmission order, a plurality of lines for transmitting the distributed data, and a serial / parallel conversion means for converting the plurality of received data into one original data. High-speed serial transmission device equipped with.