JPS61224634A - Multiplex transmitter - Google Patents

Abstract

PURPOSE:To transmit a data at a desired speed depending on a permissible waiting time with simple structure by giving plural code string patterns with different frequency appearance to each transmitter/receiver and allowing each transmitter/receiver to make transmission/reception when a code string pattern assigned to the own transmitter/receiver. CONSTITUTION:An address clock generator 1 generates a clock signal, generates a code string in synchronizing with the clock signal, mixes the code string with the clock signal and sends the result to an address clock line 3 sequentially. A transmitter 5 and a receiver 9 make transmission/reception while 5-bit information in the code string sent via the line 3 is coincident with the 5-bit address assigned to the own device, and transmit data via a 5-bit system data lien 13. While the 3-bit sent via the line 3 is coincident with the own 3-bit address, a transmitter 7 and a receiver 11 make transmission as 3-bit system transmitter and receiver, which both send data via a 3-bit system data lien 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplex transmission device that can transmit data such as control information for vehicles, etc. in multiplexed manner and at high speed.

[Prior art and its problems] An example of a conventional multiplex transmission device is, for example, the
There is something like the one shown in No. 13367.

This is an example of the so-called time-sharing method, and its outline is explained in Section 5.
Shown in the figure.

In the figure, reference numeral 101 is an address clock generator that repeatedly generates a code string called, for example, an M sequence, synchronizes it with a clock signal, and sends it out to an address clock line 103. When considering a 3-bit code string, this M sequence is such that all 3-bit code string patterns except L, L, and L are sequentially cycled once each during the period. The transmitters 105 and 107 connected to the address clock line 103 and the corresponding receivers 109 and 111 constantly monitor the above code string and transmit the 3-bit code string corresponding to the address assigned to their own device. Waiting for a pattern to emerge.

That is, the transmitter 105 and the corresponding receiver 1O9 are assigned addresses H, H, and L, for example.
When a code string pattern matching this appears, the transmitter 1
05 sends data input from the outside to the data line 113, and at the same time the receiver 109 sends this data to the data line 113.
Import from.

On the other hand, the transmitter 107 and the corresponding receiver 111 are
Further, another address, for example H, H, l-1, is given, and data is sent and received at a different time from the above method and the receivers 105 and 109.

In this way, this transmission method, which performs multiple transmission and time division according to the operating timing of the receiver, for multiple code string patterns that appear sequentially in the same period, requires extremely simple configurations of the transmitter and receiver. It has the advantage of being highly reliable and inexpensive, but on the other hand, the time required for multiple transmission/reception operations (transmission delay time) is uniformly determined by the appearance cycle of the code string pattern.

Therefore, when handling data that requires high-speed transmission, high-speed N! Traditionally, the following methods had to be used to control

(1) Increase the clock speed of the address clock generator.

Gero.

(2) Assign multiple addresses to transmitters and receivers that handle data that requires high-speed transmission.

(3) A separate line with a small number of addresses is newly established, and data requiring high-speed transmission is transmitted over this separate line.

However, each of the above methods has the following problems. In other words, in method (1), the transmission speed becomes faster for all code sequences, but it becomes more susceptible to external noise, generates high-frequency noise, or when the transmission distance is long, signal attenuation, Signal distortion may increase due to reflection, and if these countermeasures are taken, the structure will become multiple, resulting in an increase in cost.

In the method (2), since it is necessary to add a function to the transmitter/receiver to determine multiple addresses, the structure becomes complicated and the cost increases.

In method (3), a new address clock generator is required in addition to a newly installed separate system line, which also complicates the structure and increases costs.

[Object of the Invention] An object of the present invention is to improve the above-mentioned problems and provide a multiplex transmission device that can transmit data at a desired speed according to the allowable waiting time without complicating the structure. do.

[Structure of the Invention] In order to achieve the above object, the present invention provides a code string generating means for chronologically generating a plurality of code strings having different frequencies of appearance, and a code string generated by the code string generating means that generates a predetermined code string. an address clock transmission path that is transmitted at the timing of , a data transmission path that is provided corresponding to the number of address digits, and a predetermined data transmission path that monitors the code string and selects a predetermined data transmission path when a self-assigned code string pattern appears. The gist thereof is to have a data transmitting means for transmitting data to the data transmission path, and a receiving means for monitoring the code string and receiving the data from the predetermined data transmission path when a code string pattern assigned to the code string appears. do.

[Embodiments of the invention] The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a multiplex transmission apparatus according to an embodiment of the present invention. In the figure, only representative transmitters and receivers are shown.
An arbitrary number of receivers may be provided.

In the same figure, an address clock generator 1 generates a clock signal and generates a code string having a constant repetition period in synchronization with the clock signal, and uses this code string as the clock signal. By mixing, the pulses are converted into, for example, width modulated pulses, which are sequentially sent to the address clock line 3.

Connected to the address clock line 3 are transmitters 5, 7 and receivers 9, 11 corresponding thereto, respectively.

The transmitter 5 and the receiver 9 each receive a 5-bit address assigned to them from the 5-bit information sequentially sent from the code string sequentially sent from the address clock generator 1 via the address clock line 3. While the signal is in agreement with the data line 13, it performs sending and receiving operations and is connected to the 5-bit system data line 13, through which data is transmitted. Further, the transmitter 7 and the receiver 11 are connected to the address clock generator 1.
A 3-bit system transmitter and a receiver, which perform a transmission operation while the sequential 3 bits sent from the 3-bit address match their own 3-bit address, are both connected to the 3-bit system data line 15. Data is transmitted via the

The structure and operation of these transmitters, receivers 5, 7, and 9.11 will be explained in more detail as follows.

In the 5-bit transmitter 5, the address demodulation circuit 17
is connected to the address clock line and demodulates the input width modulated pulse to extract the fifth-order M-sequence code and the clock signal. A 5-bit address shift register 19 is connected to the output of the address demodulation circuit 17, and a 5-bit code string is inputted by sequentially inputting the outputted 5th order M-sequence code and shifting it sequentially according to a clock signal. hold. A 5-bit address determination circuit 21 is connected to the address shift register 19, which inputs the held 5-bit code string in parallel, and inputs this code string and a pre-assigned 5-bit address, such as L, L, L, H
1, and when the two match, an address match signal is output.

A transmission control circuit 23 is connected to the output of the address determination circuit 21, and while an address match signal is being output, a data manual buffer 25 and a data shift register 2, which will be described next, are connected to the transmission control circuit 23.
7 and the data modulation circuit 29.

The data buffer 725 has a predetermined number of bits depending on the data to be transmitted, and inputs data to be transmitted from the outside and converts it into a logic level within the circuit. A data shift register 27 having the same number of bits as the data input buffer 25 is connected to the data input buffer 25 , and receives transmission data from the data manual buffer 25 in parallel according to a command from the transmission control circuit 23 . The signals are sequentially output serially according to the timing signal. A data modulation circuit 29 is connected to the output line of the data shift register 27, and mixes the serially output data with a timing signal from the transmission control circuit 23 to convert it into, for example, a width modulated pulse, and converts it into a 5-bit pulse. The signals are sequentially sent serially to the system data line 13.

On the other hand, the 5-bit system receiver 9 also has an address demodulation circuit 31 similar to the transmitter 7, a 5-bit address shift register 33, and a 5-bit address determination circuit 35, and performs the same operation at the same timing as the transmitter 7. Address judgment circuit 35
It outputs an address match signal from and drives the reception control circuit 37 connected thereto. The data demodulation circuit 39 is connected to the 5-bit system data line 13, receives a demodulation command from the reception control circuit 37, inputs the width modulated pulse sent from the transmitter 7 from the data line 13, and demodulates it. Extract data and timing signals. A data shift register 41 having the same number of bits as the data shift register 27 of the transmitter 7 is connected to the output of the data demodulation circuit 39, and sequentially inputs the data output from the data demodulation circuit 39, and transfers the data to the adjacent one according to the timing signal. Shift into registers sequentially. A data output buffer 43 with the same number of bits is connected to the data shift register 41, and when data is stored in all registers of the data shift register 41, this data is input in parallel according to a command from the reception control circuit 37. latches it and outputs it to the outside.

In this way, the 5-bit system receiver 5 and the corresponding 5-bit system receiver 9 operate on the 5-bit system data line only when the 5-bit address appears in the address shift register 19.33. Data will be mutually exchanged via 13.

On the other hand, in the 3-bit transmitter/receiver 7.11, the address shift register 47.61 and the address judgment circuit 49.63 connected thereto are of 3 bits.
The external address to which 3-bit addresses, for example L and H, are assigned has exactly the same structure as the 5-bit transmitter and receiver 5 and 9 described above. Therefore, the 3-bit transmitter/receiver 7, 11 transmits data only during the time when the 3-bit 3-address appears in the address shift register 47.61. Furthermore, since this data transmission is performed by a 3-bit system data line 15 that is separate from the 5-bit system data line 13, all data transmission from the 5-bit system transmission and the data transmission of the receivers 5 and 9 (which can be performed independently) is performed. It is something.

FIG. 2 shows an example of a code sequence sent out by the address clock generator 1.

The sequence shown in FIG. 3A is generally called a 5th-order M sequence, and one cycle consists of 31 bits with codes Xo to X30. One bit is sent out every clock signal cycle, and the cycle is T73'. It belongs to j.t.

Using this fifth-order M-sequence code, for the 5-bit transmitter and receiver 5.9, its address register 19.33
to its own address L, L, L, L.

When H appears, as shown in the same figure (B), the symbol x 4
from the time t4 when the code x5 is sent to the time t when the code x5 is sent.
There is only time T50 up to 5, ie once during period 1. Therefore, transmission and reception operations are performed regularly at intervals of period T.

Similarly, in the 5th order M series, L, L.

Since all 5-bit code string patterns except L, L, and L, that is, 25-1=31 patterns, appear once in one period T, there are 31 addresses on the 5-bit system data line 13. Time-division multiplex transmission is possible, and the interval between transmission operations, that is, the duration τ51, matches the period T for any address.

On the other hand, for the 3-bit transmitter/receiver 7.11, its own address L is stored in its address shift register 47.61.
, L, and H appear during one cycle T as shown in the same figure (C).

Time from when X24 X3 o is sent to when the next code is sent T3 o , T3 + , T
32.

There are a total of 4 times, T33. Therefore, the transmission and reception operations are one cycle T.
It was carried out four times in the middle of the day, and the waiting time was τ31°τ32. τ3
3. τ34 is 13·t and 7·t, respectively.

6・t, 5・t (t=T/31).

Similarly, in the 5th order M series, L, L.

All 3-bit code string patterns except L, i.e. 23-
Since 1 = 7 patterns appear 4 times each in one period T, on the 3-bit system data line 15, each 1
Time division multiplex transmission of seven addresses that appear four times in period T becomes possible.

The transmission delay characteristics of such 5-bit data transmission and 3-bit data transmission will be explained below.

First, as shown in FIG. 3, a code string pattern indicating a specific address appears n times during one period T, and the waiting time for each appearance is τn1. When τn2+..., τnn, the expected waiting time τn until data transmission is actually performed when data transmission is requested at a certain time is given by the following equation.

In 5-bit data transmission, each address appears once in one cycle T, and the waiting time τnl coincides with the cycle T, as described above. Therefore, the expected value τ5 of the duration of a 5-bit address is τ5=T2/(2·T)=T/2.

On the other hand, in bit-based data transmission in a 3-bit address string, each address appears four times in one period T, as described above, and the duration is 31 times.
~τ34 differs depending on the address type.

Figure 4 shows the duration τ3 for each 3-bit address.
1 to τ34 and the expected waiting time value τ3 calculated based on these values.

As shown in the figure, the expected value of the waiting time of the 3-bit system τ3
is approximately 1 of the expected value τ5 of the waiting time of the 5-bit system mentioned above.
The speed has been reduced to 1/4 to 1/2, that is, data transmission can be performed at approximately 4 to 2 times the speed.

Therefore, if data that requires high-speed transmission is transmitted using the 3-bit system, and data that does not require high-speed transmission is transmitted using the 5-bit system, transmission can be performed in accordance with the data without causing the problems of the conventional method. can be multiplexed at high speeds.

Also, as can be seen from Figure 4, when the address is LLH, the expected value of the waiting time is smaller than when it is LHL. By assigning a small address, multiplex transmission can be performed at a more suitable transmission speed.

More generally, if an N-order M sequence is used, there are 2-1 patterns of n-bit code string patterns in one cycle, excluding a pattern in which all bits are "L", 2 for a code string pattern of m (m<n) bits.
There is a street pattern. Then, each n-bit code string pattern appears once during one cycle, and for the I-pit code string pattern, pattern 1 in which all bits are "L"
Each of the 2-1 patterns, excluding -rit, appears twice. Therefore, similarly to the above embodiment, the n-bit system,
It is possible to configure a number of time division multiplex transmission systems with gradually increasing transmission speeds, such as n-1 bit system, n-2 bit system, etc., and it is possible to configure many transmission systems. Even if configured, it is only necessary to increase the number of data transmission lines, so the configuration does not become particularly complicated.

Although the case where the M sequence is used has been described above, it goes without saying that sequences other than the M sequence may be used as long as the code sequence has a plurality of code sequence patterns appearing at predetermined different frequencies.

[Effects of the Invention] As explained above, according to the present invention, a plurality of code string patterns with different frequencies of appearance are transmitted and supplied to a receiver, and eight
The transmitters and receivers are divided into groups according to the appearance frequency of the code string patterns assigned to them, and transmission is performed when each code string pattern appears via the data transmission path for each group. It is possible to provide a code multiplexing transmission device capable of transmitting multiple pieces of data at different speeds according to the transmission delay time allowed for each data without requiring a separately complicated configuration compared to conventional devices. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a signal multiplex transmission device according to an embodiment of the present invention, FIG. 2 is a diagram showing the appearance of the 5th order M sequence and code string patterns, and FIG. 3 is a diagram showing the transmission/reception operation. FIG. 4 is a diagram showing a waiting time model, FIG. 4 is a diagram showing the waiting time of each address in a 3-bit system and its expected value, and FIG. 5 is a block diagram showing the configuration of a conventional signal multiplex transmission device. 1... Address clock generator 3... Address clock line 5... 5-bit system transmitter 7... 3-bit system transmitter 9... 5-bit system receiver 11... 3-bit system reception vessel

Claims (1)

[Claims] A code string generation means for chronologically generating a plurality of code strings with different frequencies of appearance, an address clock transmission path for transmitting the code strings generated by the code string generation means at a predetermined timing, and corresponding to the number of address digits. a data transmission path that monitors the code string and sends data to a predetermined data transmission path when a code string pattern assigned to itself appears; 1. A multiplex transmission apparatus comprising: data receiving means for receiving the data from the predetermined data transmission path when a code string pattern assigned to the data transmission path appears.