SU1325709A1 - Unitary code-to-binary position code converter - Google Patents

Abstract

The invention relates to an information technology technique and is assigned to convert a unitary code into a binary position code. The invention makes it possible to simplify the converter. The transformation of the unitary into binary code is carried out according to a sequential approximation algorithm with the presentation of the result in serial and parallel forms. The converter contains a shift register 1, a multiplexer 2, a sequential approximation register 3, a trigger 4 and a clock generator 5 executed on the elements HE 6 and 9, elements 7 and 8, resistors 10-13 and capacitors 14 and 15. 2 Il. c & (L ft.f .. with SL VI O Figure 1

Description

  1325709 The invention relates to information and measuring technology and is intended to convert a unitary code to a binary position code of parallel and sequential types. The purpose of the invention is to simplify the converter.

Figure 1 shows the functional

the lower bit is set to one, and all the lower ones are to the zero state), At the address inputs of multiplexer 2, the binary number of the 16th bit of the unitary code is set, and the value of this bit goes through the multiplexer 2 to the information input of register 3. At the moment C and clock pulse-converter circuit; in FIG. 2, time su from the output of multiplexer 2, readable diagrams explaining its operation.

The converter contains the first shift register 1, the multiplexer 2, the second register 3 of the sequential approximation, D - the trigger 4 and the clock generator 5, performed on the element 6, elements 7 and 8, the element 9, resistors 10-13 and capacitors 14 and 15.

The device works as follows.

The inputs of register 1 are supplied with a (2 -1) -digit unitary code, the value of the most significant bit of the sequential binary result is entered, and by impulse this value is entered into the most significant bit of register 3 and at the same time its more significant bit is set to one the Thus, if the value of the 16th bit of a unitary code is zero, .a means more and more

The 20 bits in the unitary code are zero, then the binary number of the 8th bit (01000) or, otherwise, the number of the 24th bit of the unitar, is formed at the address inputs of multiplexer 2.

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pbrii is entered into it by the strobe-pulse code (HLOO), i.e. on address s a, coming to the clock input of register 1 from the source of the trigger signal. At the same time, the strobe pulse and the trigger 4 is set to one state and allows you to send out clock pulses c and d on the first and second outputs of generator 5, the period of the frequency of which is equal to the total delay time of signals in multiplexer 2 and register 3. By clock pulses at the output of register 3 form a sequence of binary numbers, which are also addresses of register bits 1. In accordance with the received address, the logical signal of the selected bit passes through multiplexer 2 on information input of register 3. This allows the conversion of the input unitary () -bit code to a binary code according to a sequential approximation algorithm for P clock cycles with the result presented in serial form at the output of multiplexer 2 and in parallel form at the outputs of register 3.

Timing diagrams (Fig. 2) explain the operation of the converter using the example of converting a 31-bit unitary code to a 5-bit binary code. At time t per clock

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The multiplexer 2 inputs form a sequence of numbers of switched bits of the unitary code, depending on their values, using a sequential approximation algorithm. This ensures the formation at moments t at the output of the multiplexer 2 values of bits of a serial binary code, where, 2, ...,, and at time t p are the parallel binary code at the outputs of register 3.

A 255-t converter of a unitary code into an 8-bit binary code is implemented on integrated circuits 155 and 531; sequential approximation register of type K155IR17, multiplexer of type K155KP1. The number of intracircuit communications did not exceed three hundred, and the time to receive the 8-bit binary code in serial and parallel forms is 800 not.

Claims (1)

Invention Formula 50 The unitary code to binary positional transducer, a code containing the first register, whose information inputs are the information inputs of the transducer, and a clock generator, the first output of which is connected to the second register clock input, characterized in that, with the initial state lOOOOj ( starter in order to simplify the converter, pulse to register 3 sets9 the lower bit is set to one, and all the lower ones are to the zero state), At the address inputs of multiplexer 2, the binary number of the 16th bit of the unitary code is set, and the value of this bit goes through the multiplexer 2 to the information input of register 3. At the moment C and the clock pulse g from the output of multiplexer 2 is read- The value of the most significant bit of a sequential binary result, and by impulse, this value is entered into the most significant bit of register 3 and at the same time its more significant bit is set to one. Thus, if the value of the 16th bit of a unitary code is zero, .a means more and more  bits in the unitary code are zero, then the binary number of the 8th bit (01000) or, otherwise, the number of the 24th bit of the unitar is formed at the address inputs of the multiplexer 2 code (UYL), i.e. on address The multiplexer 2 inputs form a sequence of numbers of switched bits of the unitary code, depending on their values, using a sequential approximation algorithm. This ensures the formation at moments t at the output of the multiplexer 2 values of bits of a serial binary code, where, 2, ...,, and at time t p are the parallel binary code at the outputs of register 3. A 255-t converter of a unitary code into an 8-bit binary code is implemented on integrated circuits 155 and 531; sequential approximation register of type K155IR17, multiplexer of type K155KP1. The number of intracircuit communications did not exceed three hundred, and the time to receive the 8-bit binary code in serial and parallel forms is 800 not. Invention Formula iero introduced a multiplexer and a trigger, the outputs of the first register are connected to the same information inputs of the multiplexer, the output of which is connected to the information input of the second register and are the first information output of the converter, the first outputs of the second register are connected to the same address inputs of the multiplexer and are the second information outputs the converter, the second output of the second register is connected to its installation input the initial state, clock to 2 J 5 t the trigger input is the first control output of the converter, the trigger output is connected to the first clock input, the trigger input is 1, the second clock input and the first register clock input are combined and are the first control input of the transducer. the transmitter, the information input and the setup input into the trigger O are combined and are the second control input of the converter, the second output of the clock generator is the second control output of the converter. Fio, 2