SU1415360A1 - Pulse-width to analog converter - Google Patents

Abstract

The invention relates to electrical engineering and radio engineering and can be used as a functional converter of a pulse-width signal into an equivalent analog signal. The purpose of the invention is. An increase in the accuracy of the process of converting a pulse-width signal to an analog signal while simultaneously expanding the functionality of the converter. Analogue width-to-analog converter contains an element NOT 1, two waiting pulse generators, two control triggers for the waiting generators 3 and 5 pulses, two N-bit registers 7 and 8 shift pulses of the control triggers 9, an N-bit digital-analog converter 10 with the same weighting factors for each bit, the driver of the 6th level of the logical unit. This device provides accurate conversion of the original pulse-width signal into a multi-phase one. 1 il. (L

Description

The acquisition is related to electrical engineering and can be used, for example, in functional devices for converting a pulse-width signal (SIS) to analog.

The object of the invention is to improve the accuracy of the conversion process of the SIS to an analog signal.

The drawing shows a functional diagram of a width-to-analog converter,

The analog-to-width converter contains a sequence of NOT connected 1 & 1 element, the first D-flip-flop 2 synchronization, the first generator of 3 pulses, the second D-flip-flop 4 of the synchronization connected to the second generator 5, shaper 6 levels of the logical unit, the first 7 and the second 8 N -display shift registers connected to the input and N D-flip-flop 9 controlsEsures, digital-to-analog converter 10, scaling amplifier 11 and low-pass filter 12.

Latitudinal-anapovy converter works as follows.

When a latitude-to-analog converter arrives at the input, generator 5 starts to work when 11MS level takes a high value, and generator 3 starts working when t, level 1П1С takes a low value,

The generator receives 5 high-level signals from the oscillator in a high-level register 7 and, accordingly, into a high-level state at the inverse outputs of three-three1. This process continues until the time when the output N of the register 7, the signal level takes on a high value, as a result of which the D-trigger A is turned off and the generator 5 is blocked. At the same time, from the inverse output of the N-ro D-flip-flop 9, the high level signal arriving at the R input of the zero register 7 registers the 7 and this circuit, which forms the leading edges of the multi-phase I1IHC outputs of the D-Tpur epOB 9, ) 10 returns to the initial state, in which the D-flip-flop 4 of Peklk chugg, generator 5 is blocked and the outputs of all bits of the register 7 have a W 3 ki and a level and a signal a.

On the other hand, and from generator 3, the impulse itself is produced successively.

five

0

0

five

0

five

O

five

the low level state of the register 8 and, accordingly, the level state of the inverse outputs of the D-flip-flops 9. This continues until the output of the digit N of the register 8 takes the high level, and as a result, D- turns off trigger 2, which controls generator 3, and generator 3 is blocked. At the same time, from the direct output of the N-ro D-flip-flop 9, the high level signal arriving at the P input of the register 8 resets the register 8 and this part of the circuit-fbi, the first one of the multi-phase SIS D outputs of the D-flip-flops 9, returns to the initial state in which the D-flip-flop is turned off, the generator 3 is blocked, and the outputs of all bits of the register B are characterized by a low signal level.

From the outputs of the D-flip-flops 9 multiphase WIiC without loss of information, usually occurring at signal sampling, is fed to the p-inputs of the digital-to-analog converter 10, the distinctive feature of which is the same value for all bits. The pre-phase-to-analog signal arrives at the output of a latitude-to-analog converter, where it can be amplified by a scaling amplifier 11 to the required value and filtered from the RF components with Moiuji f.ltra 12.

Thus, the proposed width-to-analog converter converts the IlttlC into an analog signal, the integration of which, within the SIS period, gives the exact value of the original analog signal or the reconstructed signal. Opera tions 1 and reconstructions of the original signal are reflected in the circuit with additional devices — a scaling amplifier 11 and a low-pass filter 12.

The main technical advantage of the proposed analog-to-analog transformer as compared to the known ones is the increased accuracy of the conversion of the SIS, achieved through an accurate conversion of the first SIS to the multi-phase liMC, before it is converted into an analogue string, and is achieved without increasing the number of bits of the shift registers used in the device circuit.

Claims (1)

Invention Wide-Analog Conversion 1415360 The D-flip-flop of the sync circuit is connected to the common wire, and the inverse output is connected to the start input of the second pulse generator, the output connected to the clock input of the first N-relay of the shift register, the installation input to O a coil containing a series-connected element NOT and a clock input of the first synchronization D-flip-flop, the inverse output of which is connected to the start input of the first pulse generator, the outputs of the first N-bit shift register are connected to the clock inputs of the N D-control triggers, The D-inputs of all D-flip-flops are connected to the common wire, they are distinguished and and - so that, in order to increase accuracy, it is equipped with a second pulse generator with a start input, the output pulse period of which is equal to the pulse period of the first pulse generator, the second A synchronization D-trigger, a second N-bit shift register, a logic unit level shaper, an N-bit D / A converter with the same weighting factors for all bits, and the input element is NOT ene to the clock input of the second flip-flop D- synchronization and intended for connecting a source iptrotno pulse signal, D-input of the second which is connected to the inverse output N-ro of the D-control trigger, the output of the discharge N is connected to the installation input of the second D-trigger of synchronization, and the information input is connected to the information input of the second N-bit d-I shift register and the output of the level generator of the logical unit , the output of the first pulse generator is connected to the clock input of the second N-bit shift register, the installation input in O of which is connected to the N-ro D-trigger of the control trigger, and the N outputs are connected to the control inputs of the D-trigger triggers respectively, the inverted outputs of the N D-control flip-flops are connected to digital inputs of a digital-analog converter, the analog input of which is intended to be connected to a control signal source, and the analog outputs to connect to an analog signal receiver, the setup input of the first D-trigger of synchronization is connected to the output N-ro bit of the second N-bit shift register.