SU1394418A1 - Pulse driver - Google Patents

Abstract

The invention relates to devices in which pulses are generated at different times on different outputs, and can be used to simulate signals from an optical-mechanical sensor of linear displacements. The purpose of the invention is the extension of functionality - achieved by providing a phase shift of the output pulses depending on the temporal position of the input pulses and the formation of additional sequences of pulses. To do this, the sixth D-flip-flop is additionally inserted into the pulse shaper, and the fifth flip-flop is replaced by the trigger D -type and executed new functional relationships. The drawing shows the triggers 1-5 D-type, the first 6 and the second 7 input tires, output tires.8, 9 and 10, the sixth trigger 11 D-type. During operation of the driver, trigger 1 triggers a resolution signal to one of the triggers 3, 4 and a prohibition signal to the other. The pulses from these flip-flops establish (and set upon failure) the zero state on flip-flops 5 and 1, which ensures the required ratio of signals at their outputs. At the same time, at the outputs of triggers 3 and 4, pulses are formed when simulating the movement forward or backward. These pulses can be used for testing circuits, as well as a reversible counter. 2 Il. (L

Description

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The invention relates to a pulse technique, namely, devices in which pulses are generated at different times at different outputs, and can be used to simulate signals from an optical-mechanical linear displacement sensor.

The purpose of the invention is to expand the functionality by providing a phase shift of the output pulses depending on the temporal position of the input pulses and the formation of additional sequences of pulses,

Fig. 1 is an electrical schematic diagram of a pulse shaper; in fig. 2 - time diagrams of work.

The pulse shaper contains the first-fifth triggers 1-5, the first, second, third and fourth ones are made as D-triggers, the clock inputs of the first 1 and second 2 triggers are connected to the first input bus 6, the second input bus 7, the first 8, the second 9 and the third 10 output busses, the inverse output of the third D-flip-flop is connected to the input of the installation in the O fifth B-flip-flop 5, the sixth flip-flop 11 of the D-type, the fifth flip-flop 5 is executed on the D-type flip-flop, the second input bus 7 is connected to the D input of the first D flip-flop 1, the direct output of which is connected to the D input of the three d-gr D-flip-flop 3, inverse - with the D-input of the fourth D-flip-flop 4, direct output of the second D-flip-flop 2 is connected to the synchronizing input of the fifth D-flip-flop 5, and the inverse - with the D-BXO- house of the second D -trigger 2 and the synchronization input of the sixth D-flip-flop 11, the inverse output of the third D-flip-off, hera 3 is connected to the installation input

in the third D-flip-flop 3 and the first output bus 8, the inverse output of the fourth D-flip-flop 4 is connected to the installation input of the fourth D-flip-flop 4, the installation input of the sixth D-flip-flop 11 and the second output bus 9, direct output The fifth L-flip-flop 5 is connected to the synchronization input of the fourth D-flip-flop 4 and the third output bus 10, and the inverse is connected to the D-input of the fifth D-flip-flop 5, the direct output of the sixth D-flip-flop 11 is connected to the sync input of the third D- trigger 3 and fourth output bus: 12, and inverse

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Ny - with the D-input of the sixth D-flip-flop 1 1.

The pulse shaper operates as follows.

The second input bus 7 (Fig. 2a) is used to set the motion direction simulation signal: the logical O signal corresponds to the forward movement, the logical 1 signal moves backward. The pulses (on the leading edge) supplied to the first input bus 6 (Fig. 26) are set to the corresponding state D-flip-flop 1 (Fig. 2c) and D-flip-flop 2 is started (Fig. 2d), which, in its the queue, triggers D-flip-flops 5 and 11 (fig.2h, h), respectively, by signals from the direct and inverse outputs, therefore the signals at the outputs of D-flip-flops 5 and 11 are shifted by a quarter of the period.

From D-flip-flop 1, one of the D-flip-flops 3, 4 receives a resolution, and the other, respectively, a ban, the pulses from which (fig.2d, e) set the chickpeas to a D-flip-flop 5 and 11 and thus ensures the required ratio of signals (shift in one direction or another) at their outputs. At the outputs of the D-flip-flops 3 and 4, short impulses or simulations of forward movement (FIG. 2e) and, when simulating backward movement (FIG. 2e), are generated. These pulses can be used to feed a reversible counter during circuit testing, as well as testing the reversing counter itself.

Claims (1)

Formula isobteni The pulse shaper containing the first to fifth triggers, the first, second, third and fourth ones are made as D-triggers, the clock inputs of the first and second {triggers are connected to the first input bus, the second input bus, the first, second and the third output bus, the inverse output of the third D-flip-flop is connected to the input of the installation of the first D-flip-flop, characterized in that, in order to increase the functionality, a sixth D-type flip-flop is entered into it, and the fifth executed on the D-type trigger, the second input bus with One is connected to the D input of the first D flip-flop, the direct output of which is connected to D-input of the third D-flip-flop, inverse - with the D-input of the fourth D-flip-flop, direct output of the second D-flip-flop is connected to the clock input of the fifth D-flip-flop, and inverse - with the D-input of the second D-flip-flop and sync input the sixth D-flip-flop, the inverse output of the third D-flip-flop is connected to the input of the third D-flip-flop and the first output bus, the inverse output of the fourth D-flip-flop is connected to the input of the fourth D-flip-flop, the input of the sixth D-D trigger and second output bus, direct output n of that D-flip-flop is connected to the synchronization input of the fourth D-flip-flop and the third output bus, and the inverse is connected to the D-input of the fifth D-flip-flop, the direct output of the sixth D-flip-flop is connected to the synchronizing input of the third D-flip-flop and the fourth output bus, and the inverse - with D-input of the sixth D-flip-flop. S JlJTTLTTnj JlJlJlJlJ jnJ 1 J fuz. 2