SU1383508A1 - Serial-to-parallel code converter - Google Patents

Abstract

The invention relates to automation and digital computing and can be used in the interface nodes of digital devices. The aim of the invention is to expand the functionality of the possibilities by providing control of the operation of the converter, to the converter according to

Description

from 00 with

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An optional code in parallel, a group of trigger trigger 28, impulse distributor 5, element NOT 6, a column of I.PI 9-11, a bit-wise comparison scheme.

shaper puller p 8, (this comparison by comparison 7 contains groups of elements AND 29, 30, groups of elements OR 31, 32 and the element ШШ-НК 2, 1 з.п. ф-л, 3 Il.

The invention relates to automation and computing and can be used in the coordination and communication nodes of computing and measuring devices.

The aim of the invention is to enhance the functionality by controlling the operation of the converter.

None of figs. 1 shows a block diagram of a converter; in fig. 2 - timing diagrams corresponding to the normal operation of the device without failures; in fig. 3 - timing charts corresponding to the malfunction of the device.

FIG. 2 and 3, the following notation is accepted: a - input signal at input 27 of the device; b, c, d, d - signals, respectively, on the first, second, third and fourth outputs of the distributor 5; e is the signal at the output of the imager 8; g, g, and k are the signals at the direct outputs of the flip-flops 1-4, respectively, l is the signal at the output of the device.

The serial-to-parallel converter contains triggers 1-4, the distributor 5 pulses, the element 6, the circuit 7 of the same comparison, the driver 8 pulses the elements OR 9-11.

. A bitwise comparison circuit 7 consists of AND 12-17 elements, OR elements 18-23, OR OR NOT 24 element. In addition to Toto, the converter has an AND-NOT 25 element, a delay element 26, and information input 27 of the converter.

Triggers 1-4 together form a group of 28 triggers, elements And 12, 14 and 16 form the first group of 29 elements And, elements And 13, 15 and 17 form a second group of 30 elements And, elements OR 18, 20 and 22 form the first group 31 elements OR, elements OR 19, 21 and 23 form the second group of 32 elements OR.

The serial to parallel converter works as follows.

In the initial state, the device triggers 1-4 are in the initial state.

a state in which at the direct output of the triggers are zero levels of sitals, and in the inverse are single. On the distributor 5 outputs there are zero signal levels, the output

Former 8 - single signal level, at the output of the element OR NOT 24 - zero level.

The input information signal from input 27 (FIG. 2a), receiving on

In the first cycle, the unit value goes to the first S-inputs, and also through the NOT 6 element - to the first R-BXOs of the triggers 1–4.

With some delay on the first

The output of the distributor 5 is a signal (Fig. 2b), which arrives at the second R- and S-inputs of the trigger 1 directly and at the second R- and S-inputs of the flip-flops 2-4 through the elements OR 9-11. .

thirty

35

40

45

The triggers 1-4 are set to one (Fig. 2g, 3, and, k), in which single signals from the direct outputs of the triggers arrive at the first inputs of the And 12, 14 and 16 elements, as well as through the OR 18 element to the second input element And 12, the Single signal from the output of the element And 12 through the element OR 20 is fed to the second input of the element And 14, from the output of which through the element OR 22 a single signal is fed to the second input of the element And 16.

From the output of the element And 16 a single signal is fed to the input of the element ILINE 24 and confirms the zero level of the signal at its output (fig.2l). : The signal from the output of the element OR 11 is also inputted to the driver 8. After a delay time determined by the delay element 26, a zero signal is set at the output of the driver 8 (Fig. 2e), which is fed to the input of the element OR-24 But due to the fact that there is a single signal from the output of the element AND 16, the zero level of the signal remains at the output of the OR-NOT 24 element (Fig. 2n).

The first conversion cycle completed the input one signal was received in parallel to all the triggers 1–4, the readings of all the triggers 1–4 were compared to each other by circuit 7, there is no malfunction, therefore, a zero signal arrives at the device output.

In the second cycle of operation of the device, the signal from input 27 (Fig. 2a) goes through the NOT 6 element to the first R-BXO triggers 1-4. With a slight delay at the second output of the distributor 5, a signal appears (Fig. 2b), which arrives at the second R- and S-inputs of the flip-flops 2-4 through the elements OR 9-11

Triggers 2-4 return to the initial state (FIG. 2h, and k), in which single signals from the inverse outputs of the flip-flops arrive at the bit inputs of the bitwise comparison circuit 7. Simultaneously, the signal from the second output of the distributor 5 (FIG. 2c) through the element OR 19 enters the second input of the element AND 13 and spreads through the chain of elements AND 13 - OR 21 - AND 15 - OR 23 - And 17, in which elements 13, 15 and 17 are prepared on the first inputs with single signals with inverse outputs of flip-flops 2-4,

The signal from the second output of the distributor 5 through the element OR 11 is also fed to the input of the driver B, the output of which with a certain delay establishes the zero level (Fig. 2e) and is fed to the input of the element OR-NOT 24.

However, a single signal from an AND 17 element arrives at the other input of the OR-NOT 24 element, therefore the zero level of the signal remains at the output of the OR-NOT 24 element and at the device output.

The second conversion cycle is completed, the input signal is zero.

5 g

50

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fixed by trigger 2 of this bit and by triggers 3 and 4. The trigger readings were compared with each other by circuit 7, there is no malfunction, therefore a zero level signal is generated at the device output.

In the third cycle of the converter operation, a single signal from input 27 (Fig. 2a) is fed to the first S-inputs of the flip-flops 1-4. With some delay, a signal is generated at the third output of the distributor 5 (Fig. 2d), coming through the elements OR 10 and 11 to the second R and S inputs of the flip-flops 3 and 4.

Triggers 3 and 4 are switched to a single state (Fig. 2i, k), in which single signals from the direct outputs go to the first inputs of the elements in And 14 and 16 of the comparison circuit 7.

At the same time, the signal from the third output of the distributor 5 through the element OR 20 enters the second input of the element AND 14 and propagates through the elements AND 14, OR 22, AND 16 and confirms the zero level at the output of the WL-NE 24 and at the device output.

The signal from the third output of the distributor 5 through the element OR 11 also enters the driver 8, the output of which with a certain delay establishes a zero signal level (Fig. 2e) and enters the input of the element OR NOT 19. a single signal from the element AND 16, so the output level of the element OR NOT 24 remains zero signal level.

The third conversion cycle is completed, the input single signal is fixed by triggers 3 and 4, the trigger readings are monitored, there is no malfunction, and the output signal of the device is zero.

In the draft stroke of the converter operation, the zero-level signal from input 27 (Fig. 2a) through the element 6 is fed to the first R-inputs of trigger 1-4.

With some delay on, the third output of the distributor 5 generates a signal (Fig. 2d), which is fed through element 11 to the second R- and S-inputs of the trigger 4 and to the input of the imaging unit 8.

The trigger 4 returns to its initial state (FIG. 2k), in which a single signal from the inverse output goes to the first input of the element AND 17, to the second input of which a pulse arrives from the fourth output of the distributor through the element OR 23.

The signal of a single level from the output of the element And 17 is fed to the input of the element SH-24 and confirms the zero level at the output of the device. On: the output of the imaging unit 8 sets the signal level to zero with (fig.2e), but the zero level of the element OR-HE 24 is maintained by a single signal arriving at its second input.

The fourth conversion cycle is complete, the input signal of the zero level is fixed by trigger 4, operation. JKOTOporo is tested on three previous ticks.

j The sequence conversion loop, JHoro code, received at input 27, is completed,

The output parallel code is fixed on triggers 1–4, the code conversion was performed without disrupting the operation of the device, so a fault signal at the output of the device was not formed;

 Consider as an example the operation of the converter with violations when the same input sequence 1-0-1-0 arrives.

 The input information signal from Input 27 (FIG. Za), which receives a single value on: the first clock, goes to the first S-inputs of the flip-flops 1-4. At the first output of the distributor 5, a signal (Fig. 36) appears, which arrives at the second R- and S-inputs of the trigger 1 directly and at the second S- and R-inputs of the flip-flops 2-4 through the elements 9-19.

Triggers 1, 2, and 4 are set to one (Fig. 3, 3), in which single signals from the direct outputs of the triggers arrive on. the first inputs of the elements OR 18 and And 12, 1b.

Consider the case when a violation of the third bit of the converter occurs, the trigger 3 OCTSI - in its initial state (Fig. 3i).

The signals from the outputs of the flip-flops 1-4 are fed to the bit inputs of the comparison circuit 7. A single signal from the direct output of trigger 1 through the element SHI

five

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18, through the element 12, prepared at the first input, and further through the element OR 20 enters the second input of the element 14.

Element And 14 is closed at the first input by a zero signal from the direct output of flip-flop 3, therefore, at the output of element And 14 there remains a zero signal level.

The second input element And 15 also receives a zero signal from the elements And 13 and OR 21, since the first input of the element And 13 receives a signal of zero level from the inverse output of trigger 2. The signals of zero level from the outputs of elements And 14, 15 and OR 22, 23 close-on the second inputs are elements AND 16 and 17, from the outputs of which the signals of the zero level are fed to the inputs of the element OR-NOT 24.

The signal from the first output of the distributor through the OR 11 element also enters the input of the imaging unit 8, the output of which with a certain delay sets the signal to zero level (Fig. 2e), which enters the input of the OR-NOT element 24. At the output of the OR-24 element, the signal unit level (FIG. 3L) and arrives at the output of the device, thereby detecting a malfunction of the converter, which consists in the fact that the trigger 3 does not switch to a single state.

The first conversion cycle is completed, the input single signal is received on triggers 1, 2, and 4. Trigger 3, due to a malfunction, remained in the initial state. The trigger data did not match, which indicates a malfunction, an error signal was generated at the output of the device. An error signal may be perceived. subsequent devices controlling the output code or repeating the transmitted code parcel.

In the second cycle, the signal at the input 27 takes a zero value (fig.Za), this signal through the inverter 6 is fed to the first R-inputs of the triggers 1-4.

With some delay at the second output of the distributor 5, a signal appears (Fig. 3) coming to the second R- and S-inputs of the trigger 1 directly and to the second R- and S-inputs of the triggers 2-4 through the elements ИШ1 9-11.

The triggers 1, 2 and 4 are reset (Fig. 3g, g, k), with

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where the single signals from the inverse outputs go to the first inputs of the elements OR 19 and H 13, 17

The signal of the unit level from the output of the elements OR 19 propagates through the elements AND 13 and OR 21, then through the element, AND 15 prepared by the first input with a single signal from the inverse output of the trigger 3, and further through the elements OR 23 and AND 17 to the second input of the element OR-24, confirming the zero level of the signal at its output (Fig. 3l).

The second conversion cycle is in -. with completed, the input signal of the zero level is fixed by the triggers 1-4, while the overshoot of which coincided between the sbby. The output of the device receives a zero signal.

In the third cycle of the converter operation, a single signal from input 27 (Fig. Per) arrives at. first S-inputs of triggers 1-4. With some delay, a signal is generated at the third output of the distributor 5 (Fig. 3g), arriving through the elements OR 10 and 11 at the second R- and S-inputs of the flip-flops 3 and 4.

The trigger 4 switches to the single state (Fig. 3k), and the trigger 3 due to malfunction remains in the initial state (Fig. 3i), in which the single signal from its inverse output opens the first input element And 15. Pulse c third20

25

thirty

in a single state. The readings of the three Geers 3 and 4 did not coincide, the device’s output received a signal of device malfunction.

Further operation of the converter occurs in the same way.

At each Kth cycle, the input signal is remembered by the Km trigger of the information bit and (N – K) triggers of the subsequent bits. Readings (N-K-t-1 flip-flops are compared between each other, the normal operation of the device without failures and without failures corresponds to the coincidence of the readings of the flip-flops.

The inconsistency of the trigger indications indicates a malfunction of the converter elements, a violation that is detected promptly during the main work, while immediately at this conversion cycle, the malfunction signal arrives at the output of the device, thus the effect of the malfunction neutralized immediately on this conversion cycle.

The conversion of the first (N-1) bits always takes place with a higher controlling capacity, i.e. It is possible to more fully detect the malfunction of the converter than in the known device. The conversion of the remaining bits (P + 1) in the proposed device is carried out with a monitoring capacity not worse than

the output of the distributor 5 through the well-known 35, ment OR 21, the element AND 15 and the element g, if the input information OR 23 arrives at the second input of the element AND 17, but the element And 17 is closed at the first input by a zero signal from the inverse output of the trigger 4 Element AND 16 is also closed on the second input by the zero signal from the elements AND 14, OR 22. Therefore, the inputs of the element OR-NOT 24 are affected by the signals of the zero level. When the third input of the element OR-24 from the output of the imaging unit 8 is set to zero (Fig. 3A), then a single signal is produced at the output of the OR-NOT 24 element (Fig. 3L), which is fed to the output 28 of the device and fixes the occurring violation of the converter.

represented by words of variable length, when short words arrive, the extra bits of the converter are used for additional reservation of information bits and increase the control capacity of the device.

Claims (2)

1. Serial-to-parallel code converter, which contains an impulse distributor and a group of N triggers, where N is the number of output bits, the first S-inputs of the triggers are combined and connected to the information input of the converter, which is NOT connected to the first R-inputs of the triggers the groups, the second R and B inputs of the first trigger of the group are connected to the first output of the pulse distributor, about 3 and the third conversion cycle is completed, a single signal is received at the device input 27, but due to a malfunction trigger 3 remained in its original state, and trigger 4 switched in a single state. The readings of the triggers 3 and 4 did not match, the device’s output received a signal of the device’s malfunction. Further operation of the converter occurs in the same way. At each Kth cycle, the input signal is remembered by the Km trigger of the information bit and (N – K) triggers of the subsequent bits. The indications (N-K-t-1) of the triggers are compared between themselves; the normal operation of the device without failures and without failures corresponds to the coincidence of the readings of the triggers. The inconsistency of the trigger indications indicates a malfunction of the converter elements, a violation that is detected promptly during the main work, while immediately at this conversion cycle, the malfunction signal arrives at the output of the device, thus the effect of the malfunction neutralized immediately on this conversion cycle. The conversion of the first (N-1) bits always takes place with a higher controlling capacity, i.e. it is possible to more fully detect a malfunction of the converter than in the known device. The conversion of the remaining bits (P + 1) in the proposed device is carried out with a monitoring capacity not worse than   g, if the input information   g, if the input information represented by words of variable length, when short words arrive, the extra bits of the converter are used for additional reservation of information bits and increase the control capacity of the device. Invention Formula   g, if the input information 1. Serial-to-parallel code converter, which contains an impulse distributor and a group of N triggers, where N is the number of output bits, the first S-inputs of the triggers are combined and connected to the information input of the converter, which is NOT connected to the first R-inputs of the triggers the groups, the second R and B inputs of the first trigger of the group are connected to the first output of the pulse distributor, which is 9138 Allowed by the fact that, in order to increase functionality 1; an account for providing control of the Iota of the converter, (N-1) OR elements are entered into it, the pulse shaper and the comparison circuit, the first and second groups of inputs lioTopoA are connected to the direct and inverse outputs of the group triggers, i-th () the output is distributed; the pulses are connected to 1-y with i-ro through (K-1) th OR elements, the outputs of which are respectively connected with the second R and S inputs with (i + l) -ro with N group triggers, jth (j 2 - "- N) output of the pulse distributor is connected to (jl) -M polling input of the bitwise comparison circuit, Nth test input which is connected to the pulse generator code, the input of which is connected to the output of the (N-l) -ro epement OR, the output of the bit comparison circuit is the output of the transducer. : 2. Converter according to claim. 1, t-L; and that with the fact that it contains, in a random comparison, the element OR NOT, the first and second groups ten elements from (Nl) -ro element H, the first and SECOND; groups from. (Nl) -ro element OR, the first inputs of the first elements OR of both groups, respectively, are connected to the inputs of the first bits of the first and second groups of bit inputs of the bitwise comparison circuit. , the first inputs of Kx (K 2 + N-1) elements OR of the first and second groups are respectively connected to the outputs (K-1) of the elements AND of the first and second groups, the first inputs of which are connected to the outputs (K-1) - x elements OR of the first and second groups, respectively, the second inputs of the Kx elements OR of the first and second groups are combined and are with K-e polling inputs of the comparison reference circuit, the N-th polling input of which is connected to the first input of the element SHI-NOT, the second and third inputs of which are connected to the outputs (Nl) -x of the elements AND of the first and second groups, respectively, and the output of the element OR- is NOT the output of the bitwise comparison circuit, the inputs from the second to (M-1) -th first and second groups of which are connected respectively to the second inputs of the AND elements of the first and second groups. "Pi / aJ