SU1416998A1 - Test-suitable digital device - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in the construction of hand-held digital devices, especially in the form of large integrated circuits, and equipment based on them. The goal is to increase control. Device I is connected by inputs 4 and outputs 5 to the diagnosed unit 25 and performs system functions under the control of input 14 of system synchronization. In the test mode, any group of registers can be transferred to the shift mode of information received from test input 11 to output 12. The state of the other registers does not change. The selection of registers is determined by the contents of control register 9. The trigger 8 allows information to be transmitted from input 11 directly to output 12 and is used when building the device. The operation in test mode is controlled by the control encoder 13 under the influence of operation mode inputs 16 and 17 and test synchronization input 15. The group of multiplexers 3 and multiplexer 10 provide the necessary configuration of the information shift chain. The device allows to increase the information content of the control with a significant reduction in the number of external communications, as well as to combine several such devices with the possibility of simultaneously performing the normal mode and the monitoring mode, which expands its functionality. 3 il. S (L 4 about: with from 00

Description

The invention relates to automation and computer technology and can be used to build digital devices that are easy to test, especially implemented in the form of large integral cxe, and equipment based on them.

The purpose of the invention is to increase the depth of control.

Figure 1 shows the structural diagram of the device connected to the diagnosed unit; figure 2 - scheme of the encoder; FIG. 3 is an example of a device build-up.

The testable digital device 1 contains a group of m series-parallel registers 2, a group of m multiplexers 3, parallel information input 4 and output 5 and serial input 6. and output 7 of register 2 (il, m), trigger 8, m-bit shift control register 9, multiplexer 10, device test set input 11, used to select a device, select group registers 2, enter test information and connect to the serial the input of the register 2, the information input of the multiplexer 3, the information input of the register 9 of the control, the D input of the trigger 8 and the information input of the multiplexer 10, the serial output 12, which is the output of the current state of the control points of the device, the encoder 1 3, input 14 of the system synchronization input 15 of the test synchronization, inputs 16 and 17 of the operation mode setting, output 18 of the encoder 13 are connected to the synchronization input of the trigger 8, output 19 of the encoder 13 are connected to the synchronization input of the control register 9, the output of the trigger 8 is connected to the input

20 of the decoder 13, the parallel output of the register 9 forms a t-bit input

21 of the encoder 13, the output 22, - (, m) of the generator 13 is connected to the control

, the inputs of the multiplexer 3 and the register 2 |, the output 231 (, t) of the encoder 13 is connected to the synchronization input of the register 2, the output 24 of the encoder 13 is the control input of the multiplexer 10.

Inputs 4; and exits 5; (, t) devices are connected to the diagnosed unit 25, which has inputs-outputs 26.

.

but

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The encoder 13 contains a binary converter 27 with outputs 28-31, elements AND 32-35, element NO 36, element I-CM 37, elements And 38 and 39, the element

 OR NOT 40, elements AND 41- (, t), elements AND-OR 42, - and 43; (, t). The output 28 of the encoder 27, the output 44 of the element AND-OR 37, the output of the 45 element

d and 33 and the output 46 of the element And 35 form the output 24 of the encoder 13.

The device 1 and block 25 can be made in the form of a single functionally complete module, for example, in

15 as a large integrated circuit, the register part of which corresponds to device 1, and the combination

part - block 25.

Each of the registers 2 (, t) is issued in the form of a shift register with the possibility of parallel recording and reading of information. The shift mode corresponds to the state of a high logic level at the output of the 22. encoder 13, while the output of the multiplexer is 3 /; information is received from the serial output of register 2. A low logic level at the output of the 22-encoder 13 provides for the output at the output of multiplexer 3 information from the output of multiplexer 3};, (the output of multiplexer 3 in this case receives information from input 11 of the device). Trigger 8 and

35, all device registers change their state on the leading edge of the signal at the corresponding synchronization input (transition from low to high level).

40 The device operates in four modes determined by the information on. inputs 16 and 17: Device selection, Register selection, Shift, Func

citing

In the Device Select mode, a combination 00 is present at the inputs 16 and 17, a logical unit level is formed at the output 28 of the decoder 27, which connects the trigger output 8 to the device output 12 via a multiplexer 10. The information from the device test input input 11 is recorded in the trigger 8 by a clock signal, coming from the input 15 of the test synchronization of the device to the output 18 of the block 13 through the element 32. Setting the trigger 8 to one state means selecting the device for conducting diagnostic procedures.

In the Register selection mode, the combination 01, forming the output of the encoder 27, the logical unit level, connected between the input 11 and the device output 12, is outputted to the inputs 16 and 17 of the encoder 27, and only those registers are combined to which the unit state corresponds to

At the outputs 28-31 - the logical, active register register 9, the control switch, connected between the input 11 and the output 12 of the device, combines only those registers that correspond to the unit state corresponding to

go zero With a single state of the trigger 8 in block 13, the output unit 45 of the element 33 forms a logical unit level, and at the output 44 of the element AND-OR 37 and the output 46 of the element 35 it is logical zero, which ensures the connection of the serial output of the register 9 control, e - nor to exit 12 of the device. Information from the input 1 of the device is sequentially recorded in the control register 9 under the action of the synchronization signal from the input 15 of the test synchronization to the output 19 of the encoder 13 through the AND 38 element. When the trigger 8 is at zero, the output of the 44 AND-37 element is formed and at the output 45 of the element I.33 and at the output 46 of the element I 35 there is a logical zero, which both connects the input P of the device to the output 12.

In the Shift mode, the combination 10 is applied to the inputs 16 and 17 of the device, forming a logical unit level at the output 30 of the decoder 27, and a logical zero at the outputs 28 - 3J. In the unit state of the trigger 8 at the output 46 of the element. And 35, a logical unit level is formed, and at the output 44 of the AND-OR element 37 and the output 45 of the element AND 33, a logical zero, which ensures the connection of the output of the multiplexer 3 to the output 12 of the device . The presence of a single state of the bit (, t) of the control register 9 leads to the appearance of a high logic level at the outputs of the corresponding elements And 41 | and AND-OR 42., which ensures transfer to register shift mode 2., connecting its serial output 7 {to the output of multiplexer 3; and passing the clock signal from the input 15 of the test sync to the output 23 of the encoder 13 through the element AND-OR 43-. The zero state of bit 21 | of control register 9 leads to the disconnection of the input 15 of the test synchronization from the input 23; the encoder 13, while the output of the multiplexer 3- receives information from the output of the multiplexer 3. Thus, in the shift target

neither The information in them is input under the action of the sync signal at the input 15 of the test synchronization, while the number of the remaining registers does not change. At zero state of the trigger

8 at the output 44 of the AND-OR 3 / element, the level of a logical unit is formed, and at the output 45 of the element 33 and 33 and the output 5 of the 46 element 35, a logical zero, which ensures that the input 11 of the device is connected to output 12.

In the Operation mode, the inputs 16 and 17 of the device are fed

0 is a combination of 11, forming at the output 31 of the decoder 27 a level of a logical unit, and at outputs 28-30 - a logical zero. At all outputs of the 22 elements and 4 there are levels

5 logical zero, which ensures the absence of the shift mode of the registers 2o. With a single state of the trigger 8, the level of the logical unit is formed at the output of the AND 34 element.

0 The presence of a single state of discharge 21J (, t) of control register 9 leads to the appearance of a high logic level at the output of the AND-OR element

.42 j, which allows the passage of I .-

5 sync signals from test input 15

synchronization to the output 23, the encoder 13. Thus, the parallel recording of information from the inputs 4 is carried out only in those registers, which corresponds to the unit state of the corresponding register bit

9 guides.

The alternation of the Shift and Function modes ensures the input of test information into the selected group of registers, the execution of the operation by block 25 and the output of the result. In this case, the state of the remaining registers remains unchanged.

Under the zero state of the trigger 8 in the Shift and Operation modes and in any state of the trigger 8 in the Select device and Select registers modes, all the outputs of the encoder 13 can receive a clock signal from the system synchronizer input 14, all outputs 22 are in the zero state . This ensures 5

0

514

FUNCTIONS OF SYSTEM (WORKING) FUNCTIONS BY BLOCK 25 TOGETHER WITH REGISTERS 2 At single value of trigger 8 in Shift and Functional modes. The synchronization signal from the input 14 of the system synchronization to the outputs 23 of the encoder 13 is blocked.

Consider the possibility of increasing the device. FIG. 3 shows an example of combining modules made in accordance with FIG. 1 into a group (for example, combining large integrated circuits on a board). Input 1 and output 12 are successive inputs and outputs, inputs 14 and 15 respectively are system inputs and test sync ,,: inputs 6 and 17 - inputs work mode: you. At the same time, the number of inputs does not depend on the number of modules in the group: From the information links inside the group, only one is conventionally shown - the connection between the output register 2: module 1 and the input register 2 Mo Dul Z.

Each of the modules can be diagnosed independently of the rest by setting the trigger in the Select device mode in one of the modules to the unit state, in the others to the zero state. After this, the test information in the unselected modules will be fed from the serial input 11 directly to the serial output 125, ensuring the connection of the serial inputs 1i and output 12 of the group to the selected module. This capability provides the simplicity of constructing a test sequence for a group of modules based on the test sequences formed to diagnose each of the modules.

In order to diagnose the connections between the modules, it is sufficient to include only the input and output registers in the shifts along the chain of the group. For example, when diagnosing communication 11 in the device selection mode, trigger 8 in each of the modules is 1/2. and 1 is set to one, and in modules i and D is set to zero. Then, in the Select registers mode in the control registers 9 of the module f) and 1, the bits corresponding to registers 2 and 2 are set to one. diagnosis is implemented86

is an alternation of the Shift and F idyllination modes.

The presence of a tritter 8 allows one or several modules to be diagnosed simultaneously with the performance of the remaining modules of the system functions under the action of the system synchronization input 17.

Claims (1)

Invention Formula A testable digital device containing a group of m serial-parallel registers (where m is the number of control point groups of the monitored block), the parallel information inputs and outputs of which are the information inputs and outputs of the device for connecting to the outputs and inputs of the monitored digital block, respectively The first information input of the first register of the group is connected to the input of the test of the device, characterized in that, in order to increase the depth of control, the multiplex group is entered into it eksorov, m-bit shift register nsh railway control, trigger encoder, a multiplexer, wherein the serial output i-ro (, .zsh). serial-parallel register of the group is connected to the first information input of the corresponding group multiplexer, the second information input of the first group multiplexer is connected to the device test input, and to the first information input of the multiplexer, with the serial information input of the H-bit shift control register and D -switch input, respectively, the output of which is connected to the second information input 1 1 multipl.exora and the first gate of the encoder, the first and second inf The formatting inputs of which are the first and second inputs of the device operation mode, respectively, the first and second synchronous inputs of the device are connected to the third and fourth information inputs of the cipher — the first output of which is connected to the synchronous trigger input, the second output of the encoder is connected to synchronous input of the t-bit shift control register, a group of bit outputs of which is connected to the ctp of information inputs of the cipher 14 the torus, the first group of outputs of which is connected to the group of control inputs of the group multiplexers and with the inputs of setting the mode of series-parallel registers of the group, the output of the group multiplexer i-ro is connected to the second information input of the group multiplexer and the serial information input ( i + l) -ro of the serial-parallel register of the group, the serial output of the t-th serial-parallel register of the group is connected to the first information input of the t-th group multiplexer, output 15 J8 19 70 2ft Tim 72i / Lt 2bi ly / 6998 which is connected to the third information input of the multiplexer, the fourth information input of which is connected to the serial output of the t-bit shift control register, the outputs of the second encoder group are connected to the synchronous inputs of the series-parallel registers of the group, the third group of outputs of the encoder is connected to the group of control inputs of the multiplexer, output which is the output of the current state, groups of control points of the device. 0 15 /four / J / rr four // / 15 16 J7 / FIG.