JPS6245202A - Frequency multiplier circuit - Google Patents

Abstract

PURPOSE:To decrease the chip size in case of circuit integration by using two coincidence circuits including a delay circuit so as to process digitally frequency multiplication. CONSTITUTION:Signals 3-1, 3-2 having a delay of td1 are given between input terminals of an EC-OR circuit 8-1. As a result, a waveform at an output point (c) of the coincidence circuit 8 is shown in 3-3. Further, signals 3-3, 3-4 having a delay of td2 are given between input terminals of an EX-OR 9-1. As a result, a waveform at an output point (e) of the coincidence circuit 9 is shown in 3-5. The output of the coincidence circuit 9 is outputted to an output terminal 12 via a 1/2 frequency division circuit 10 and a duty correction circuit 11. Thus, the output waveforms of the circuits 10, 11 are shown in 3-6, 3-7 and a signal having a frequency being twice the frequency f0 of the input signal s obtained at the terminal 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital frequency multiplier circuit.

BACKGROUND ART Digital equipment requires a reference frequency as a system clock, but in order to improve the accuracy of the system, it is better to double the input reference frequency a and use it as the system clock.

Conventionally, a PLL type circuit shown in FIG. 2 has been used for the frequency multiplier circuits 1 to 1. In FIG. 2, 1 is an input terminal to which a signal of frequency fo is input. 2 is a phase detector, 3 is a low-pass filter, 4 is a voltage controlled oscillator,
5 is a 1/n frequency dividing circuit, 6 is an output terminal, and f is connected to terminal 6.
It is possible to do a frequency that is twice as high as oO.

[The problem that the invention is trying to solve]

The conventional circuit shown in Figure 2 outputs the exact 0 times frequency! However, since the operation is analog-like, a transistor with a large element size is required to increase the oscillation characteristics and control sensitivity, and it is also necessary to pay attention to the humidity characteristics and shoe sound characteristics. .

In VTR and TV equipment, the standard frequency, e.g. NTS
In the case of C, sufficient characteristics can be obtained as a system clock by simply doubling 3.58MH2, and the second
The circuit shown in the figure is disadvantageous in terms of chip size and the number of external terminals of the IC.

An object of the present invention is to provide a circuit that digitally multiplies frequencies while suppressing increases in chip size and number of external terminals.

[Means for solving problems]

In the present invention, frequency multiplication is performed digitally, and the present invention will be described in detail below.

〔Example〕

FIG. 1 shows one embodiment of the present invention, and FIG. 3 is an operational waveform diagram of the multiplier circuit of the present invention.

In FIG. 1, 8 is a first matching circuit, 9 is a second matching circuit, 10 is a 1/2 frequency dividing circuit, and 11 is a duty correction circuit. The first matching circuit 8 includes one EX-OR circuit 8-
1, and (2n+l) stage inverters, where n is an integer of 1 or more, provided between one input terminal of this circuit and the signal input terminal 7. Therefore, between the two input terminals of the EX-OR circuit 8-1, 3-1.3-
A signal with a delay of td as shown in the two waveform diagrams is given. As a result, the waveform at the output point C of the first coincidence circuit 8 becomes as shown in 3-3 in FIG.

Second matching circuit 91d, one EX-0 circuit 9-1
and (2n-rn) stages provided at the input terminal of this circuit, where m is 1 or more (2n-m≧1)
inverter. Therefore, between the two input terminals of the EX-0 circuit 9-1, there is a
A delay of td2 is given as shown in the waveform diagram. td,
)td, and the waveform at the output point e of the matching circuit 9 is as shown in FIG. 3-5. The output of the second matching circuit passes through the 1/2 frequency divider circuit 1° and the continuation circuit of the Tudy correction circuit 11 and is outputted to the terminal 12. Therefore, the circuit 10°1
The output shaping of 1 is shown at 3-6.3-7 in FIG. As a result, a signal having a frequency twice the frequency fo of the input signal can be obtained at the output terminal 12.

Since the (2n-z)-stage inverter and the (2n-+n)-stage inverter each constitute a delay (b) path, it is a matter of course that other configurations may be used.

〔Effect of the invention〕

As described above, in the present invention, frequency multiplication can be performed digitally, so when integrated into an IC, the chip size can be reduced, and it is particularly suitable for CMO8 implementation. In the present invention, outputs are obtained from 12 outputs, but if the duty of the waveform does not require 50 outputs, point f of the 10 outputs may be output.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional example, and FIG. 3 is an operation waveform diagram of the present invention. Agent Patent Attorney Uchihara 1'゛・Nichihara

Claims (1)

[Claims] an input terminal, a first delay circuit coupled to the input terminal, a first matching circuit coupled to the input terminal and the first delay circuit, and a first matching circuit coupled to the first matching circuit. 2 delay circuits, the first matching circuit and the second delay circuit;
A frequency multiplier circuit comprising: a second matching circuit coupled to a delay circuit; and a frequency dividing circuit that frequency divides the output of the second matching circuit.