JPS6054523A - Phase lock loop circuit - Google Patents
Phase lock loop circuitInfo
- Publication number
- JPS6054523A JPS6054523A JP58162838A JP16283883A JPS6054523A JP S6054523 A JPS6054523 A JP S6054523A JP 58162838 A JP58162838 A JP 58162838A JP 16283883 A JP16283883 A JP 16283883A JP S6054523 A JPS6054523 A JP S6054523A
- Authority
- JP
- Japan
- Prior art keywords
- range
- voltage
- voltage control
- control oscillator
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
- 230000000295 complement effect Effects 0.000 claims 1
- 230000002159 abnormal effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、フェーズロックループ（以下Ｐ ＬＬと記
す）回路の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a phase locked loop (hereinafter referred to as PLL) circuit.
従来のＰＬＬ回路の基本的な構成を第１図を用いて説明
する。第１図において、■はＰＬＬ回路の基準となる信
号を発生する基準側回路、２は位相検波器、３は低域ろ
波器、４は電圧制御発振器、５は電圧制御発振器４の出
力信号を入力として動作する応用側回路である。The basic configuration of a conventional PLL circuit will be explained using FIG. In Figure 1, ■ is a reference side circuit that generates a reference signal for the PLL circuit, 2 is a phase detector, 3 is a low-pass filter, 4 is a voltage controlled oscillator, and 5 is the output signal of voltage controlled oscillator 4. This is an application side circuit that operates with input.
次に動作について説明する。基準側回路ｌは、ＰＬＬ回
路の基準となる信号を発生し、位相検波器２は、この信
号と電圧制御発振器４の出力信号を位相比較して誤差信
号を出す。この誤差信号は、低域ろ波器３を通過して、
電圧制御発振器５の制御入力に入り、該発振器５の発振
周波数を制御する。位相検波器２．低域ろ波器３．電圧
制御発振器４によるループにより、基準側回路１が発生
する信号と応用側回路５に入力される信号の周波数と位
相は、ある関係に保たれる。Next, the operation will be explained. The reference circuit 1 generates a signal that serves as a reference for the PLL circuit, and the phase detector 2 compares the phases of this signal with the output signal of the voltage controlled oscillator 4 to generate an error signal. This error signal passes through a low-pass filter 3 and
It enters the control input of the voltage controlled oscillator 5 and controls the oscillation frequency of the oscillator 5. Phase detector 2. Low-pass filter 3. Due to the loop formed by the voltage controlled oscillator 4, the frequency and phase of the signal generated by the reference circuit 1 and the signal input to the application circuit 5 are maintained in a certain relationship.
従来のこのＰＬＬ回路では、基準側回路ｌが何らかの原
因によって、異常な出力信号を発生ずると、電圧制御発
振器４の出力信号は、応用側回路５にとって不適当な周
波数になり、応用側回路５／
の動作に何らかの障害を与える可能性があった。In this conventional PLL circuit, when the reference side circuit 1 generates an abnormal output signal for some reason, the output signal of the voltage controlled oscillator 4 becomes a frequency inappropriate for the application side circuit 5, and the application side circuit 5 / There was a possibility that it would cause some kind of trouble to the operation.
この発明はかかる欠点を解消する為になされたもので、
電圧制御発振器の前段に、振幅制限器を備えることによ
り、応用側回路の許容できる周波数範囲に、電圧制御発
振器の出力信号を制限するようにしたＰＬＬ回路を折供
することを目的としている。This invention was made to eliminate such drawbacks.
The purpose of this invention is to provide a PLL circuit that limits the output signal of the voltage controlled oscillator to a frequency range that is allowable for the applied circuit by providing an amplitude limiter in the front stage of the voltage controlled oscillator.
以下、第２図を用いて、この発明の一実施例を説明する
。第２図において、１はＰ Ｌ Ｌ回路の基準となる信
号を発生する基準側回路、２は位相検波器、３は低域ろ
波器、４は電圧制御発振器、５は電圧制御発振器４の出
力信号を入力として動作。An embodiment of the present invention will be described below with reference to FIG. In Fig. 2, 1 is a reference side circuit that generates a reference signal for the PLL circuit, 2 is a phase detector, 3 is a low-pass filter, 4 is a voltage controlled oscillator, and 5 is the voltage controlled oscillator 4. Operates using output signal as input.
する応用側回路、６は振幅制限器である。6 is an amplitude limiter.
一般的に、電圧制御発振器４の周波数可変範囲に比較し
て、応用側回路５の許容できる入力信号の周波数の範囲
は狭く、基準側回路１の出力信号の周波数は正常な状態
においてはある範囲に限られていて、位相を合わせる為
に使用される電圧制御発振器４の制御入力の電圧範囲は
、電圧制御発振器４に゛入力可能な電圧範囲の一部分Ｇ
こすぎなｌ、Ｍ。Generally, compared to the variable frequency range of the voltage controlled oscillator 4, the allowable frequency range of the input signal of the application side circuit 5 is narrow, and the frequency of the output signal of the reference side circuit 1 is within a certain range under normal conditions. The voltage range of the control input of the voltage controlled oscillator 4 used for phase matching is limited to a part of the voltage range that can be input to the voltage controlled oscillator 4.
Kosuina l, M.
従ってこのことを利用して、低域ろ波器３とｆｆｔ Ｂ
Ｅ制御発振器４との間に、振幅制限器６を入れ、電圧制
御発振器４の入力電圧範囲を制限することＧこより、応
用側回路５が許容できる入力信号の周波数範囲内に、電
圧制御発振器４の出力信列の周波数を制限することがで
きる。一方、正常な状態においては振幅制限器６は振幅
制限動作を行わなし）ので、ＰＬＬ回路の動作に影響を
与えなし）。Therefore, using this fact, low-pass filter 3 and fft B
An amplitude limiter 6 is inserted between the E-controlled oscillator 4 and the input voltage range of the voltage-controlled oscillator 4 is limited. The frequency of the output signal train can be limited. On the other hand, in a normal state, the amplitude limiter 6 does not perform any amplitude limiting operation, so it does not affect the operation of the PLL circuit.
第３図は本発明のより具体的な実施例を示し、第３図に
おいて、１〜６は第２図と同しものを示し、Ｖｃｃｌ’
、Ｖｃｃ２は高圧、低圧側の電源、７し才基準電圧源、
８はＮＰＮ Ｉ・ランジスタ、９（まＰＮＰトランジス
タであり、基準電圧源７とＮ Ｐ Ｎ Ｉ−ランジスタ
８とＰＮＰ トランジスタ９とで半導体集積回路よりな
る振幅制限器６を構成してし）る。FIG. 3 shows a more specific embodiment of the present invention. In FIG. 3, 1 to 6 are the same as in FIG. 2, and Vccl'
, Vcc2 is the high-voltage and low-voltage side power supplies, and the 7-year-old reference voltage source.
Reference numeral 8 denotes an NPN I transistor, and 9 (also a PNP transistor, the reference voltage source 7, the NPN I transistor 8, and the PNP transistor 9 constitute an amplitude limiter 6 made of a semiconductor integrated circuit).
第３図の基本的な動作は第２図と同様であるが、第３図
の実施例の特徴は、半導体集積回路よりなるＮＰＮ）ラ
ンジスタとＰＮＰＩ−ランシスタノ相禎形の回路により
、振幅レベルを、基′ｖ′電圧源７の出力電圧から±Ｖ
ｂｅ（ベース・エミッタ間電圧）の範囲内に振幅制限し
ていて、簡単な回路で振幅制限を実現できることにある
。The basic operation of FIG. 3 is the same as that of FIG. 2, but the feature of the embodiment of FIG. , ±V from the output voltage of base 'v' voltage source 7
The amplitude is limited within the range of be (base-emitter voltage), and the amplitude limitation can be realized with a simple circuit.
なお以上は基本的なＰ、ＬＬ回路を例にとって説明した
が、本発明は種々のＰＬＬ回路に適用できることは言う
までもない。Although the above explanation has been given by taking a basic P, LL circuit as an example, it goes without saying that the present invention can be applied to various PLL circuits.
以上のようにこの発明によれば、ＰＬＬ回路の電圧制御
発振器の前段に振幅制限器を備えたので、正常な状態で
の動作に影響を与えることなく、ＰＬＬ回路に異常な入
力があった場合にも、Ｐ Ｌ Ｌ回路の出力信号を、該
出力信号を使用する応用側回路の許容できる周波数範囲
内に制限でき、回路の性能及び信頼性の向上に有効であ
る。As described above, according to the present invention, since the amplitude limiter is provided in the front stage of the voltage controlled oscillator of the PLL circuit, it is possible to prevent abnormal input from occurring in the PLL circuit without affecting the operation under normal conditions. In addition, the output signal of the PLL circuit can be limited to a frequency range that is allowable for the application circuit that uses the output signal, which is effective in improving the performance and reliability of the circuit.
第１図は従来の基本的なＰＬＬ回路を示すブロック図、
第２図はこの発明の一実施例によるＰＬ工、回路のブロ
ック図、第３図はこの発明のより具体的な実施例を示す
回路図である。
１はＰＬＬ回路の基準となる信号を発生する基準側回路
、２は位相検波器、３は低域ろ波器、４は電圧制御発振
器、５は電圧Ｗｉｌ制御発１辰」器の出カ信号を使用す
る応用側回路、６ζま１辰ＩＩ’畠ｉｌｒ’ｌ ＩＱｔ
著３．７番よ基準電圧源、８はＮＰＮ ｌ−ランジスタ
、９番よＰＮＰトランジスタである。
なお図中同一符号は同−又しよ卑口当ｕｌ〜分を示す。
代理人 大 岩 増 雄FIG. 1 is a block diagram showing a conventional basic PLL circuit.
FIG. 2 is a block diagram of a PL device and circuit according to an embodiment of the present invention, and FIG. 3 is a circuit diagram showing a more specific embodiment of the present invention. 1 is a reference side circuit that generates a reference signal for the PLL circuit, 2 is a phase detector, 3 is a low-pass filter, 4 is a voltage controlled oscillator, and 5 is the output signal of the voltage controlled oscillator. Application side circuit that uses 6ζ or 1
3. No. 7 is a reference voltage source, No. 8 is an NPN l-transistor, and No. 9 is a PNP transistor. Note that the same reference numerals in the drawings indicate the same numbers. Agent Masuo Oiwa
Claims (1)
とを位相比較する位相検波器と、この位相検波器の出力
に接続された低域ろ波器と、この低域ろ波器の出力を振
幅制限する振幅制限器と、この振幅制限器の出力を制御
入力とする電圧制御発振器とを備えたことを特徴とする
フェーズロックループ回路。 （２） 半導体集積回路により構成されていることを特
徴とする特許請求の範囲第１項記載のフェーズロックル
ープ回路。、 （３） 振幅制限器として、ＮＰＮ）ランジスクとＰＮ
Ｐ ）ランジスタとを有する相補形の回路を用いたこと
を特徴とする特許請求の範囲第２項記載のフェーズロッ
クループ回ｉ。[Claims] A phase-locked loop circuit comprising: an amplitude limiter that limits the amplitude of the output of a filter; and a voltage-controlled oscillator whose control input is the output of the amplitude limiter. (2) Constructed from a semiconductor integrated circuit. (3) As an amplitude limiter, a phase-locked loop circuit according to claim 1, characterized in that:
The phase-locked loop circuit i according to claim 2, characterized in that a complementary circuit having a transistor P) is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58162838A JPS6054523A (en) | 1983-09-05 | 1983-09-05 | Phase lock loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58162838A JPS6054523A (en) | 1983-09-05 | 1983-09-05 | Phase lock loop circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6054523A true JPS6054523A (en) | 1985-03-29 |
Family
ID=15762202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58162838A Pending JPS6054523A (en) | 1983-09-05 | 1983-09-05 | Phase lock loop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6054523A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230426U (en) * | 1985-08-03 | 1987-02-24 | ||
| JPS63276370A (en) * | 1987-05-07 | 1988-11-14 | Sony Corp | Pll circuit |
| JPH0221725A (en) * | 1988-07-11 | 1990-01-24 | Nec Corp | External synchronizing clock pulse generating circuit |
| JPH04108353U (en) * | 1991-02-28 | 1992-09-18 | 株式会社富士通ゼネラル | resin mold motor |
| JP2009515726A (en) * | 2005-11-14 | 2009-04-16 | セダ エス．ピー．エイ． | Stacking protrusion and container manufacturing apparatus having the same stacking protrusion |
-
1983
- 1983-09-05 JP JP58162838A patent/JPS6054523A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230426U (en) * | 1985-08-03 | 1987-02-24 | ||
| JPS63276370A (en) * | 1987-05-07 | 1988-11-14 | Sony Corp | Pll circuit |
| JPH0221725A (en) * | 1988-07-11 | 1990-01-24 | Nec Corp | External synchronizing clock pulse generating circuit |
| JPH04108353U (en) * | 1991-02-28 | 1992-09-18 | 株式会社富士通ゼネラル | resin mold motor |
| JP2009515726A (en) * | 2005-11-14 | 2009-04-16 | セダ エス．ピー．エイ． | Stacking protrusion and container manufacturing apparatus having the same stacking protrusion |
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