JPH01280930A - Frequency synthesizer system receiver - Google Patents

Abstract

PURPOSE:To reduce lockup time by selecting a reference frequency of a phase locked loop to a multiple M of a minimum broadcast frequency interval, frequency-dividing the oscillated output of a voltage controlled oscillator of the phase locked loop and utilizing the frequency division output as a local oscillation signal. CONSTITUTION:When a reference frequency fr' and an oscillated frequency fv' of a voltage controlled oscillation circuit 13' are multiplied by a factor of M, the frequency division ratio N' is expressed as N'=fv'/fr'=M.fv/M.fr=N and it is enough to be the same as a conventional example. Moreover, as to the minimum change frequency of the local oscillating frequency, the relation of DELTAfl=DELTAfv'/M=fr'/M=fr is obtained and this is the same as that of a conventional receiver. On the other hand, the natural angular frequency omegan' is expressed as omegan'=sq. rt. Kv'.Kp'.KL/N'=sq. rt. M.Kv.Kp.KL/N=sq. rt. M.omegan because the gain constant Kv' of the voltage controlled oscillator 13 is expressed as Kv'=M.Kv, then the natural angular frequency is a factor of sq. rt. M in comparison with a conventional receiver. Thus, the lockup time is decreased as a factor 1/sq. rt. M in comparison with a conventional receiver.

Description

[Detailed Description of the Invention] The present invention relates to a frequency synthesizer type receiver using a phase-locked loop (hereinafter referred to as P, L, L), and in particular to one configured to shorten lock-up time. It is.

FIG. 1 shows a block diagram 11 of a conventionally known frequency synthesizer type Lanau receiver using P, L, and L. (1) is a high frequency amplifier circuit, (2
) is a mixing circuit, (3) is an intermediate frequency amplification circuit, (4) is a detection circuit, (5) is a low frequency amplification circuit, and (6) is a speaker. Now, the local oscillation signal that can be input to the mixing circuit (2) is obtained from P1. In other words, a stable reference oscillation circuit (1
The oscillation output of 0) is passed through a frequency dividing circuit (11
), and the reference frequency 1g (that frequency is rr
It becomes one input of the phase comparator circuit (12). - On the other hand, the oscillation output (its frequency is f'v) of the voltage controlled oscillator (13) is controlled by the programmable frequency divider circuit (14) whose frequency division ratio (N) is varied in response to the desired local oscillation frequency. ) and becomes the other input of the phase comparison circuit (12). An output based on the phase difference between both signals input to the phase comparator circuit (12) is fed back to the voltage controlled oscillator (13) via a low pass filter (15). Such P
, L, and L become locked at f'v-N-f'r (N is an integer), as is well known. By varying the frequency division ratio (N) of the programmable frequency divider circuit (14), a local oscillation frequency (fv) that is an integral multiple of the reference frequency (fr) can be obtained. Therefore, in general, the reference frequency (fr)
is set to match the minimum broadcast frequency interval.

By the way, in the AM broadcast medium wave band, the inter-office frequency is mostly 9 KHz, but in some parts of Europe it may be 8 KHz or I KHz, so the reference frequency (fr) had no choice but to set it to I KHz.

However, if the reference frequency (fr) is set to IK)Iz, the lock amplifier time of P, L, and L becomes long, which becomes a problem especially in an auto-search type radio receiver.

A problem also arises when the reference frequency (fr>) is made small so that variations in the characteristics of the intermediate frequency filter can be corrected digitally.

Here, if the reference frequency (fr> is made smaller, why P,
L, I will briefly explain whether L's mouth/come-up time will be longer. Now, if the gain constants of the voltage controlled oscillator (13), phase comparator circuit 12), and low-pass filter (15) are respectively Kv, Kp, and KL, the natural angular frequencies of P, L, and L are as follows. , ωnw-Kv-Kp-KL N.By the way, since N=rv/rr, if the reference frequency (fr> is made smaller, N becomes larger and the natural angular frequency (ωn) becomes smaller. , the lockup time becomes longer.

Now, in the conventional frequency synthesizer type receiver shown in FIG. 1, it was not possible to solve the problem mentioned above. As shown in the figure. Second
In the figure, circuits with the same functions as those in FIG. 1 are given the same figure numbers.

In the embodiment shown in FIG. 2, the reference frequency is set to (fr'
), the division ratio of the programmable frequency divider (14') is (N'
), the oscillation frequency of the voltage controlled oscillator<13') is (fv'
), and f'v' = N' · f'r'. The feature of the present invention is that the voltage controlled oscillator (13')
Instead of using the oscillation output directly as a local oscillation signal, the frequency (fffi) (fffi - r v ' /
M) is used as a local oscillation signal, and this signal is passed through a low-pass filter (17) to a mixing circuit (
2). Low pass filter (17)
is for removing harmonic noise, and the frequency (f12
') band pass filter etc. may be used.

Now, assume that the reference frequency (fr') in the present invention and the oscillation frequency (fv') of the voltage controlled oscillation circuit (13°) are made M times that of the conventional example shown in FIG. That is, rr'-M-r
Let r, fv'-M-fv. Then, the division ratio (N'
) is N'=rv'/rr'-M, f'v/M-fr
-N, which may be the same as the conventional example.

Also, regarding the minimum change frequency of the local oscillation frequency, △r
p-△f'v'/M-f'r'/M
-rr, which is the same as the conventional example. On the other hand, the natural angular frequency ωnl) is the gain constant (K
v') becomes Kv' = M - Kv, so ωn'
=l Kv -Kp-KL/N'I-I M-Kv-K
p-KL N-fM・ωn, which is 1E compared to the conventional example.
Therefore, the lock-up time can be increased by 1/f compared to the conventional example.In other words, the frequency division ratio, the maximum /J% change frequency of the local oscillation frequency, etc. can be increased by 1/f compared to the conventional example. The characteristics remain the same as the conventional example, and the lock-up time has been reduced to 1.
/, /”” can be made as short as R- times.

According to the present invention described above, the lockup time of P, L, and L can be shortened while other characteristics remain the same as in the conventional example.

[Brief explanation of the drawing]

Each of the drawings shows a block diagram of a frequency synthesizer type radio receiver; FIG. 1 shows a conventional example, and FIG. 2 shows an embodiment of the present invention. (10')...Reference oscillation circuit, (12')...Phase comparison circuit, (13')...Voltage controlled oscillator, (14''
J...Programmable frequency divider circuit, (15') (17
)...low-pass filter, (16)...frequency divider circuit.

Claims (1)

[Claims] (1) A frequency synthesizer type receiver that obtains a local oscillation signal from a phase-locked loop configured to vary the oscillation output of a voltage-controlled oscillator in response to varying the frequency division ratio of a programmable frequency divider, comprising: The reference frequency of the phase-locked loop is set to M times the minimum broadcast frequency interval, and the oscillation output of the voltage-controlled oscillator of the phase-locked loop is divided by a frequency divider, so that the divided output of this frequency divider is A frequency synthesizer type receiver characterized in that it uses as a local oscillation signal.