JPS6339129B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a radio device that is used as a signal source for the transmitting frequency or receiving local oscillation frequency of an FM radio device, has a crystal oscillator, and directly modulates a signal using the output of the crystal oscillator. The present invention relates to a PLL circuit, and specifically relates to a PLL circuit with improved S/N and C/N of an output signal.

FM radios used as mobile radios in the VHF band or UHF band have high S/N (signal-to-noise ratio) and C/N (carrier power to sideband noise) as the signal source of the transmitting frequency and receiving local oscillation frequency. power ratio) is required. For example, for the received local oscillation signal in a 150MHz band FM radio, in order to satisfy the sensitivity suppression characteristics of the receiver, the carrier wave power and the single sideband wave that falls into the 16KHz band centered on a frequency detuned by 20KHz from the carrier wave. The ratio to noise power is required to be 90 dB or more. Also, for the received local oscillation signal in a 400MHz band FM radio, for the same reason, the ratio between the carrier wave power and the single sideband noise power that falls in the 16KHz band centered on a frequency detuned by 25KHz from the carrier wave is 80dB or more. That is required.

In order to satisfy these strict conditions, conventional FM radios generally use a crystal oscillation circuit as a signal source. In other words, a method was mainly adopted in which the output of a crystal oscillator circuit was multiplied using a multiplier circuit to obtain a signal in the 150 MHz band or 400 MHz band. However, this crystal oscillation multiplication method has the problem of requiring many circuit components and requiring many adjustment points in the circuit. It was also difficult to integrate the device into an IC. Therefore, recently, a PLL (Phase-Locked Loop) circuit has been proposed as an alternative signal source.

FIG. 1 shows a PLL circuit proposed as a signal source for the transmitting frequency or the receiving local oscillation frequency. In the PLL circuit, a crystal oscillator 11 is used to oscillate a reference frequency f _xp . This signal is then supplied to the phase comparator 12 to detect a phase error between it and the output signal of the voltage controlled oscillator 14 whose frequency has been divided by the frequency divider 13. Phase comparator 12 generates a phase error voltage in response to the detected phase error. The phase error voltage is applied to the voltage controlled oscillator 14 through a low-pass filter 15 that removes unnecessary noise, and controls the oscillation frequency. As a result, divider 1
When the frequency division number of 3 is N, the output frequency f' _p of the voltage controlled oscillator 14 is controlled to the following value.

f' _p = N x f _xpNow , in this PLL circuit, the frequency division number N of the frequency divider 13 is set to a value as small as possible, for example, N = 8, and the phase comparison frequency by the phase comparator 12 is set to several
The frequency is set as high as 10MHz. Therefore, in this PLL circuit, the natural frequency fn (=2π/ωn) of the phase-locked loop
can be set to a very large value, for example approximately 400KHz. Therefore, the S/N and C/N of the output signal output from the PLL circuit are predominantly controlled by the S/N and C/N of the crystal oscillator used in the reference frequency oscillator over a wide offset frequency range. , the following relational expression holds.

Output signal S/N (or C/N) [dB] = Crystal oscillator S/N (or C/N) [dB] -20logN [dB]
(1) However, the relationship in equation (1) holds true only when the noise generated from the phase comparator 12 and the frequency divider 13 is sufficiently small. In reality, it is difficult to obtain such phase comparators and frequency dividers, so
It has been difficult to make the S/N and C/N of the output signal of the PLL circuit equal to the output signal of the above-mentioned crystal oscillation multiplication method.

One way to solve this problem is to reduce the frequency division number of the frequency divider. In this method, the oscillation frequency of the crystal oscillator is increased, and the frequency division number of the frequency divider is reduced by that amount, thereby reducing the influence of noise generated from the phase comparator and frequency divider on the output signal of the PLL circuit. do. However, the crystal oscillator used in this method has a high oscillation frequency and is difficult to manufacture. Furthermore, when attempting to directly modulate a signal using a crystal oscillator, a circuit using this method has the disadvantage that sufficient modulation characteristics cannot be obtained. Of course, this drawback cannot be improved by increasing the loop gain of the PLL circuit.

The present invention was made in view of the above circumstances, and an object of the present invention is to provide a PLL circuit that can improve the S/N and C/N of an output signal without setting the oscillation frequency of a crystal oscillator particularly high. shall be.

In the present invention, by multiplying the output signal of the crystal oscillator circuit using a frequency multiplier circuit and using this as a reference frequency signal, the S/N or C/N ratio of the output signal due to noise generated from the phase comparator or frequency divider is To achieve the above objective by reducing the influence on N.

The present invention will be explained in detail with reference to Examples below.

In FIG. 2, the crystal oscillator 21 is similar to the conventional crystal oscillator commonly used, for example,
Generate fxo signal. The frequency of this signal is multiplied by L times by the frequency multiplier circuit 22, and becomes a reference frequency signal of frequency _fR . The frequency f _R is as follows.

f _R =L×f _xp This reference frequency signal is supplied to the phase comparator 23. Then, a phase error is detected between the output signal of the voltage controlled oscillator 25 and the frequency divided by the frequency divider 24. The phase comparator 23 generates a phase error voltage according to the detected phase error. The phase error voltage is applied to the voltage controlled oscillator 25 as a control voltage after passing through the low pass filter 26. When the frequency division number of the frequency divider 24 is M, the output frequency f _p of the voltage controlled oscillator 25 is controlled to the following value.

f _p = M x f _R = M x L x f _xp Therefore, similarly to the conventional PLL circuit, if the noise generated from the phase comparator 23 and the frequency divider 24 is sufficiently small, the output output from the PLL circuit The following relational expression holds true for the signal.

Output signal S/N (or C/N) [dB] = Crystal oscillator S/N (or C/N) [dB] - 20logL
[dB] -20logM [dB] (2) Of course, this equation (2) does not hold if the noise generated from the phase comparator 23 or the frequency divider 24 is large. However, in the case of the circuit of this embodiment, the output frequency fo of the circuit is equal to the output frequency f′o of the conventional circuit.
, the frequency division number N of the frequency divider in the conventional circuit and the frequency division number M of the frequency divider 24 in this embodiment have the following relationship.

N=M×L...(3) Therefore, the difference in the amount of noise generated by the phase comparator or frequency divider between the conventional circuit and the circuit of this embodiment satisfies equation (3). When the following happens.

20logN/M [dB] ...(4) In other words, in this embodiment, the frequency division number M of the frequency divider 24
can be selected to be smaller than that of conventional circuits, so the noise generated from the phase comparator or frequency divider will be smaller than the S/N or C/N of the output signal of the PLL circuit.
The effect on N is reduced. This means that it becomes possible to use phase comparators or frequency dividers that generate a large amount of noise. As an example, if N=8 and L=2, then M=4 and equation (4) becomes as follows.

20logN/M [dB] = 6 [dB] In other words, it is possible to create an FM radio using a phase comparator or frequency divider that generates 6 dB more noise than conventional circuits.

As described above, according to the present invention, the S/N and C/N ratios are almost the same as those of the crystal oscillation multiplication type without using an expensive and difficult-to-obtain phase comparator or frequency divider that generates particularly little noise. Since an output signal can be obtained, the circuit can be manufactured more cheaply and easily than conventional PLL circuits.
Furthermore, the circuit of the present invention can significantly reduce the number of parts and adjustment points compared to a crystal oscillation multiplication type circuit. In other words, the PLL circuit of the present invention requires a multiplier circuit that is not required in conventional PLL circuits, but unlike the multiplier circuit required in the crystal oscillation multiplier type circuit, this multiplier circuit eliminates unnecessary frequency components (spurious components). Does not require high spurious rejection ratios for high-level rejection. Therefore, whereas the multiplier circuit required for the crystal oscillation multiplier type circuit required high selectivity and the circuit configuration and circuit adjustment were complicated, the multiplier circuit required for the PLL circuit of the present invention is Easy to configure and requires little adjustment. Since a crystal oscillator oscillates a low frequency, multiplies it, and leads it to the PLL loop, sufficient modulation characteristics can be obtained even if the signal is directly modulated using the output of this crystal oscillator.
Moreover, since the PLL circuit of the present invention allows for significant IC integration and miniaturization, when this circuit is used in equipment such as mobile radio equipment, it has great economical and performance effects.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional PLL circuit, Figure 2 is a block diagram of a conventional PLL circuit.
The figure is a block diagram of a PLL circuit in one embodiment of the present invention. 21... Crystal oscillator, 22... Frequency multiplier circuit, 23... Phase comparator, 24... Frequency divider, 25
...Voltage controlled oscillator.

Claims (1)

[Claims] 1 A PLL circuit of a radio device that has a crystal oscillator and directly modulates a signal using the output of this crystal oscillator, which includes a voltage controlled oscillator that changes the oscillation frequency according to a control voltage, and the output of this voltage controlled oscillator. A frequency divider that divides the signal by a frequency division number according to the noise tolerance of the loop, and a frequency divider that multiplies the output of the crystal oscillator by a multiplication number determined in relation to the frequency division number of the frequency divider. It comprises a frequency multiplier circuit, and a phase comparator that detects a phase error in the output signal of the frequency divider using the output signal of the frequency multiplier circuit as a reference and generates the control voltage according to this phase error, A PLL circuit characterized by obtaining a signal of a controlled frequency from a controlled oscillator.