JPH011335A - Transmitter with noise prevention circuit - Google Patents

Transmitter with noise prevention circuit

Info

Publication number
JPH011335A
JPH011335A JP62-155504A JP15550487A JPH011335A JP H011335 A JPH011335 A JP H011335A JP 15550487 A JP15550487 A JP 15550487A JP H011335 A JPH011335 A JP H011335A
Authority
JP
Japan
Prior art keywords
transmitter
frequency
circuit
phase comparator
digital phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62-155504A
Other languages
Japanese (ja)
Other versions
JPS641335A (en
Inventor
伸一 藤沢
Original Assignee
日本電気株式会社
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP15550487A priority Critical patent/JPS641335A/en
Priority claimed from JP15550487A external-priority patent/JPS641335A/en
Publication of JPH011335A publication Critical patent/JPH011335A/en
Publication of JPS641335A publication Critical patent/JPS641335A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は送信機、特に周波数安定化のためにデジタルの
位相比較器を使用した送信機に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to transmitters, and more particularly to transmitters that use digital phase comparators for frequency stabilization.

[従来の技術] 従来、この柱の送信機は、周波数を安定化させるため、
例えば、自動位相制御回路(AI)C)、自動周波数制
御回路(AFC)が用いられている。
[Conventional technology] Conventionally, this pillar transmitter has been designed to stabilize the frequency by
For example, an automatic phase control circuit (AI) and an automatic frequency control circuit (AFC) are used.

第2図には、従来のA )) C方式の送信機の一例が
示されており、同図において、4は電圧制御発振器<V
CO) 、5は分周器、6はデジタルの位相比較器、7
は基準周波数発生器、8はローパスフィルタ(LPF)
、9はミキサー、10は高周波増幅器、11は局部発振
器である。
Figure 2 shows an example of a conventional A))C type transmitter, in which 4 is a voltage controlled oscillator <V
CO), 5 is a frequency divider, 6 is a digital phase comparator, 7
is a reference frequency generator, 8 is a low-pass filter (LPF)
, 9 is a mixer, 10 is a high frequency amplifier, and 11 is a local oscillator.

そして、この送信機は、VCO4の出力信号のの周波数
を分周器5を用いて位相比較可能周波数まで分周し、デ
ジタル位相比較器6に入力している。
This transmitter uses a frequency divider 5 to divide the frequency of the output signal of the VCO 4 to a frequency that allows phase comparison, and inputs the frequency to a digital phase comparator 6.

デジタル位相比較器6は、この分周信号と基準周波数発
生器7からの信号とを位相比較し、その比軸信号をL 
11 F 8を介して出力しVCO4の出力制御を行い
、発振器の周波数を安定化させている。
The digital phase comparator 6 compares the phases of this frequency-divided signal and the signal from the reference frequency generator 7, and outputs the ratio axis signal as L.
11F8 to control the output of VCO4 and stabilize the frequency of the oscillator.

[解決しようとする問題点] しかし、従来の送信機は、電源起動時に、VCo4の発
振周波数が中心より離れた所から立ち上り、数秒から士
数秒かけて引き込まれる。
[Problems to be Solved] However, in the conventional transmitter, when the power is turned on, the oscillation frequency of the VCo 4 rises from a place far from the center and is drawn in over several seconds to several seconds.

この過程の中で1.デジタル位相比較器6からは、連続
的なパルス信号が出力されずに、デユーティ〜の異なる
段階的なパルス13号が出力されるため、L ))F 
8はこの段階的なパルス信号を充分乎滑できずにノイズ
成分を含んだままVCo4に向は出力してしまう。
In this process, 1. Since the digital phase comparator 6 does not output a continuous pulse signal, but outputs a stepwise pulse No. 13 with a different duty, L))F
8 cannot sufficiently absorb this stepwise pulse signal and outputs it to the VCo 4 while containing noise components.

このノイズ成分により、VCo4からはFM変調された
信号が出力され、これが受信側ではノイズと12で観測
されるという問題があった。
Due to this noise component, an FM modulated signal is output from the VCo 4, and this is observed as noise on the receiving side.

本発明は、この様な従来の課題にかんがみてなされたも
のであり、その目的は、電源起動時にノイズを発生する
ことのない雑音発生防止回路付送信機を提供することに
ある。
The present invention has been made in view of such conventional problems, and an object thereof is to provide a transmitter with a noise generation prevention circuit that does not generate noise when power is turned on.

し問題点の解決手段1 前記目的を達成するため、本発明は、 送信出力周波数安定化にデジタル位相比較器を使用して
いる送信機において、 電源起動時にデジタル位相比較器から発生するノイズを
検出するAPC電圧判定回路と。
Means for Solving Problems 1 To achieve the above object, the present invention provides the following features: In a transmitter that uses a digital phase comparator for stabilizing the transmission output frequency, the present invention detects noise generated from the digital phase comparator when the power is turned on. APC voltage determination circuit.

電源起動時に、ノイズ発生が終了してから所定の遅延時
間経過後に送信を開始する遅延スイ・ソチ回路と、 を含む構成としている。
The configuration includes a delay switching circuit that starts transmission after a predetermined delay time has elapsed after noise generation ends when the power is turned on.

「実施例」 次に、本発明の好適な実施例を、図面にもとづき説明す
る。なお、第2図に示す従来装置と対応する部材には同
一符号を付してその説明は省略する。
"Embodiments" Next, preferred embodiments of the present invention will be described based on the drawings. Note that the same reference numerals are given to the members corresponding to those of the conventional device shown in FIG. 2, and the explanation thereof will be omitted.

第1図には、本発明に係る雑音発生防止回路付送信機の
好適な一実施例が示されている。
FIG. 1 shows a preferred embodiment of a transmitter with a noise prevention circuit according to the present invention.

本実施例の送信機には、A P C電圧判定回路1、遅
延回路2、スイッチ3が設けられている。
The transmitter of this embodiment is provided with an APC voltage determination circuit 1, a delay circuit 2, and a switch 3.

そして、APC電圧判定回路1は、L P F 8から
出力されるVCO制御電圧の正常、異常を判別し、正常
時には[1]、異常時には「0」の信号を遅延回路2に
向は出力する。
Then, the APC voltage determination circuit 1 determines whether the VCO control voltage output from the LPF 8 is normal or abnormal, and outputs a signal of [1] when normal and "0" when abnormal to the delay circuit 2. .

遅延回路2は、APC電圧が正常になってから完全に周
波数がロックされるまでの間、スイッチ3をオーブンに
制御する。また、APC制御電圧が異常を示す場合にも
、直ちにスイッチ3をオーブンに制御する。
The delay circuit 2 controls the switch 3 to oven until the APC voltage becomes normal and the frequency is completely locked. Further, even if the APC control voltage indicates an abnormality, the switch 3 is immediately controlled to the oven.

すなわち、電源オンしてからある一定時間は、A P 
C制御電圧は異常を示すため、A P C電圧判定回路
1は“0″のロジック信号を遅延回路2に送出する。
In other words, for a certain period of time after the power is turned on, A P
Since the C control voltage indicates an abnormality, the APC voltage determination circuit 1 sends a logic signal of "0" to the delay circuit 2.

遅延回路2は、“0″のロジック信号入力時に直ちにス
イッチ3をオーブンに制御する。
The delay circuit 2 immediately controls the switch 3 to open when a logic signal of "0" is input.

次にAPC制御電圧が正常値になると、APC電圧判定
回路1は111 I+のロジック信号を発生し、遅延回
路2は、送信出力周波数がロックされるのに必要とされ
る遅延時間が経過した後に、スイッチ3をオン制御する
Next, when the APC control voltage becomes a normal value, the APC voltage determination circuit 1 generates a logic signal of 111 I+, and the delay circuit 2 generates a signal after the delay time required for the transmission output frequency to be locked. , turns on the switch 3.

し発明の効果−1 以上説明したように、本発明によれば、電源起動時に、
VCOの発振周波数が中心より離れた所から立ち上がっ
ても、雑音が発生することのない送信機を提供できると
いう効果がある。
Effects of the Invention-1 As explained above, according to the present invention, when the power is turned on,
This has the effect of providing a transmitter that does not generate noise even if the oscillation frequency of the VCO rises from a location far from the center.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係るAPC周波数安定化方式の送信機
の一実施例を示すブロック回路図、第2図は従来のAP
C周波数安定化送信機を示すブロック回路図である。 1:APC電圧判定回路 2:遅延回路 3:スイッチ 4:VCo 5:分周器 6:位相比較器 7:基準周波数発生器 8 : LPF 9:ミキサー 10:高周波増幅器 11:局部発振器 代理人  弁理士  渡 辺 喜 平 箔1図 第2図
FIG. 1 is a block circuit diagram showing an embodiment of an APC frequency stabilization transmitter according to the present invention, and FIG. 2 is a block circuit diagram of a conventional APC frequency stabilization transmitter.
FIG. 2 is a block circuit diagram illustrating a C frequency stabilization transmitter. 1: APC voltage judgment circuit 2: Delay circuit 3: Switch 4: VCo 5: Frequency divider 6: Phase comparator 7: Reference frequency generator 8: LPF 9: Mixer 10: High frequency amplifier 11: Local oscillator agent Patent attorney Yoshi Watanabe Hirahaku Figure 1 Figure 2

Claims (1)

【特許請求の範囲】 送信出力周波数安定化にデジタル位相比較器を使用して
いる送信機において、 電源起動時にデジタル位相比較器から発生するノイズを
検出するAPC電圧判定回路と、 電源起動時に、ノイズ発生が終了してから所定の遅延時
間経過後に送信を開始する遅延スイッチ回路と、 を含むことを特徴とする雑音発生防止回路付送信機。
[Claims] In a transmitter that uses a digital phase comparator to stabilize the transmission output frequency, there is provided an APC voltage determination circuit that detects noise generated from the digital phase comparator when power is turned on; A transmitter with a noise generation prevention circuit, comprising: a delay switch circuit that starts transmission after a predetermined delay time has elapsed after the generation ends;
JP15550487A 1987-06-24 1987-06-24 Transmitter with noise preventing circuit Pending JPS641335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15550487A JPS641335A (en) 1987-06-24 1987-06-24 Transmitter with noise preventing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15550487A JPS641335A (en) 1987-06-24 1987-06-24 Transmitter with noise preventing circuit

Publications (2)

Publication Number Publication Date
JPH011335A true JPH011335A (en) 1989-01-05
JPS641335A JPS641335A (en) 1989-01-05

Family

ID=15607490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15550487A Pending JPS641335A (en) 1987-06-24 1987-06-24 Transmitter with noise preventing circuit

Country Status (1)

Country Link
JP (1) JPS641335A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006025300A1 (en) * 2004-08-30 2006-03-09 Jms Co., Ltd. Aid for coronary artery bypass operation

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BRPI0117269B8 (en) 2000-03-02 2021-11-23 Sekisui Chemical Co Ltd Interlayer film for laminated glass and laminated glass comprising the same
JP3599183B2 (en) * 2001-03-28 2004-12-08 日本電気株式会社 Satellite communication transmission control system and small earth station

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006025300A1 (en) * 2004-08-30 2006-03-09 Jms Co., Ltd. Aid for coronary artery bypass operation

Similar Documents

Publication Publication Date Title
JPH027718A (en) Phase synchronizing loop circuit having high speed phase synchronizing current reducing and clamping circuit
JPH07170176A (en) Device for setting up tuning frequency of pll circuit and its method
JPS5917727A (en) Bandwidth control circuit of phase locked loop
JPH011335A (en) Transmitter with noise prevention circuit
JP3326286B2 (en) PLL frequency synthesizer circuit
JPH0797745B2 (en) Phase synchronization circuit
JP3161137B2 (en) PLL circuit
JP2853817B2 (en) Phase lock loop
JPH09224057A (en) Fsk modulation circuit
JP2510130Y2 (en) PLL circuit
JPH0328606Y2 (en)
JPH04139917A (en) Pll circuit
JP3343019B2 (en) High frequency signal generator, video signal reproducing device, and video signal recording / reproducing device
JPH05327492A (en) Ppl synthesizer
JPS5846586Y2 (en) Circuit with phase locked loop
JP2927801B2 (en) PLL circuit
JPH0724819Y2 (en) Phase synchronization circuit
JP3281833B2 (en) PLL circuit
JP3019434B2 (en) Frequency synthesizer
JPS6359008A (en) Fm modulation circuit
KR950016077A (en) Frequency Modulator
JPH08139767A (en) Fsk modulation system
JPH06284002A (en) Pll circuit
JPH07154432A (en) Fsk modulator
JPH0345937B2 (en)