JP3343019B2 - High frequency signal generator, video signal reproducing device, and video signal recording / reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency signal generator (hereinafter, referred to as an RF signal generator), a video signal reproducing apparatus, and a video signal recording / reproducing apparatus, and particularly to a TV system RF signal including an audio signal. Related to generator improvement.

[0002]

2. Description of the Related Art An RF signal generator having a modulation function (hereinafter, referred to as an RF modulator) converts a video signal and an audio signal into a high-frequency signal (hereinafter, referred to as an RF signal) and converts it into a television (hereinafter, referred to as an RF signal). , TV) is a circuit to be inserted into an empty channel of a broadcast. The RF signal is supplied to a TV receiver. Usually, the video signal and the audio signal that are the source are signals that have been subjected to signal processing at the time of reproduction in a recording / reproducing apparatus or a reproduction-only apparatus (for example, a VTR, a disc, a TV game, or the like) of a package media system. As an RF modulator, for example, a PLL (Phase Lock Lo) described in Japanese Patent Application Laid-Open No. 3-204286 is used.
Op) type RF modulators are known.

FIG. 8 to FIG. 11 are diagrams showing a circuit configuration of an example of a conventional video signal reproducing device and a PLL type RF modulator. The overall configuration will be described. As shown in FIG. 8, an RF signal 2 from an antenna 1 is input from an input terminal 4 of a video signal reproducing device 3. On the other hand, means for reproducing package media such as VTRs, disks, and TV games 6
The reproduction signal reproduced from the video signal 8
Is restored to the audio signal 9 and input to the RF modulator 5. The RF signal 10 output from the RF modulator 5 and the RF signal 2 of the TV broadcast from the antenna 1 are added to the adder 1.
1 is added, added and output. The added output RF signal 12 is supplied to, for example, an RF input terminal of a TV receiver. On the other hand, control data 13a such as frequency setting data from the microcomputer 13 and switching of various modes.
Is input to the RF modulator 5.

An outline of the entire operation will be described. The reproduced signal is restored to a video signal 8 and an audio signal 9 by a known signal processing circuit 7. The RF modulator 5 converts the video signal 8 and the audio signal 9 from the signal processing circuit 7 into an RF signal 1 having a frequency of a vacant channel (for example, the second channel) of the TV broadcast.
Convert to 0. This RF signal 10 and the RF signal 2 of the TV broadcast from the antenna 1 are added, and the RF signal 12
Is output as

[0005] TV broadcasting system is PAL system, SECAM
In the case of the system, the frequency of this TV broadcast channel is UHF
(Ultra High Frequency) band, and the number of channels is very large. The channel frequency of the TV broadcast differs depending on the country or region, and when these conditions are set, for example, the microcomputer 13 in the video signal reproducing device 3
To the RF modulator 5 as control data 13a.

Next, the configuration of the RF modulator 5 will be described. As shown in FIG. 8, the video signal 8 from the signal processing circuit 7 is input to the RF encoder 14. The audio signal 9 from the signal processing circuit 7 is input to an audio subcarrier signal oscillation circuit (including, for example, an FM modulator) 15. The output audio subcarrier signal (eg, FM signal) 16 is R
Input to the F encoder 14. One output signal of the reference oscillator 18 using the crystal oscillator 17 is input to the audio subcarrier signal oscillation circuit 15. The reference oscillator 18
Is output to the main carrier signal oscillation circuit 19, and the output main carrier signal 20 is output to the RF encoder 14.
Is input to The RF encoder 14 performs modulation (for example, AM modulation) of the video signal 8 and frequency conversion of the audio sub-carrier signal 16 and adds them, and outputs the result as an RF signal 10 of a frequency of a vacant channel of the TV broadcast. The control signal 13a is demodulated by the data demodulator 21.
For example, two control signals are input to the audio sub-carrier signal oscillation circuit 15 and the main carrier signal oscillation circuit 19, respectively. The control data 13a may include other data for another circuit, and in this case, another demodulated control signal is supplied to another circuit. Further, the RF modulator 5 may include an adder 11 depending on the system design.

Next, the RF encoder 14 will be described. As shown in FIG. 9, the video signal 8 is input to the AM modulator 22 and AM-modulates the main carrier signal 20 supplied from the main carrier signal oscillation circuit 19. Audio subcarrier signal oscillation circuit 1
The audio sub-carrier signal 16 supplied from 5 is input to the frequency converter 23 and frequency-converted by the main carrier signal 20. The output signal of the AM modulator 22 and the frequency-converted audio subcarrier signal 16 are added by an adder 24 and
It is output as signal 10.

The audio sub-carrier signal oscillation circuit 15 will be described. The audio signal 9 is input to the adder 25 of the audio subcarrier signal oscillation circuit 15. Adder 25, voltage controlled oscillator (hereinafter referred to as VCO) 26, variable frequency divider (frequency division ratio N1) 2
7, phase comparison circuit 28, filter 29, adder 25
Are connected in this order to form a PLL circuit. Reference oscillator 1 using crystal oscillator 17
The reference signal 31 obtained by dividing the signal supplied from 8 by the frequency divider 30 is input from another input terminal of the phase comparison circuit 28.
The audio subcarrier signal 16 output from the audio subcarrier signal oscillation circuit 15 is an output signal of the VCO 26. FIG.
As shown in (a), a filter 2 of a general PLL circuit is used.
The configuration 9 includes a resistor R connected in series to the circuit and a capacitor C connected in parallel. As shown in FIG. 10B, in the case of the filter 29a of another example, at least a capacitor C connected in parallel is included.

The main carrier signal oscillation circuit 19 will be described. V
The output terminal and the input terminal of the CO 32, the variable frequency divider (division ratio N2) 33, the phase comparison circuit 34, the filter 35, and the VCO 32 are connected in this order to constitute a PLL circuit. A reference signal 37 obtained by dividing a signal from the reference oscillator 18 by a frequency divider 36 is input to another input terminal of the phase comparison circuit 34. The main carrier signal 20 output from the main carrier signal oscillation circuit 19 is an output signal of the VCO 32. As shown in FIG. 11, the error signal 38 from the filter 35 is input to a transistor Q1 which is a common-emitter amplifier provided at the input terminal of the VCO 32. The collector of the transistor Q1 is connected to the high voltage power supply terminal 39 via the load resistor RL. Although not particularly shown, the tuning voltage signal Vt of the collector of the transistor Q1 is V
It is connected to the latter part of CO32.

Next, the operation of the RF modulator 5 will be described. In the audio subcarrier signal oscillation circuit 15, the input audio signal is added to the error signal 40 by the adder 25,
FM modulation is performed by directly changing the frequency of the VCO. At this time, the frequency shift is defined as f _MOD . On the other hand, the reference oscillator 18
Is divided by a frequency divider 30 to become a reference signal 31 having a frequency fr1. The audio subcarrier signal 16 output from the VCO 26 is frequency-divided by a variable frequency divider 27 having a frequency division ratio N1. The reference signal 31 and the output signal 41 of the variable frequency divider 27 are compared by the phase comparator 28 and the output signal 42
Becomes Eventually, the phase of the reference signal 31 and the output signal 41 of the variable frequency divider 27 are synchronized, so that the oscillation frequency fs of the audio subcarrier signal 16 is expressed by the following equation (1).

Fs = N1 × fr1 ± f _MOD (1) That is, the oscillation frequency fs is set to the frequency of the audio subcarrier signal of the TV system (PAL system, SECAM system, etc.) of each country by changing the frequency division ratio N1. Is done.

Similarly, the main carrier signal oscillation circuit 19
Then, the reference signal 37 of the frequency fr2 of the output of the frequency divider 36
The output signal 43 of the variable frequency divider 33 having the frequency division ratio N2 is compared with the output signal 43 of the variable frequency divider 33 by the phase comparison circuit 34 to become the output signal 44. After all, the reference signal 37 and the output signal 43 of the variable frequency divider 33 are phase-synchronized, and the oscillation frequency fc of the main carrier signal 20 is expressed by the following equation (2).

Fc = N2 × fr2 (2) That is, the frequency of the main carrier signal is adjusted to an available channel of the TV broadcast by changing the frequency division ratio N2.

In the RF encoder 14, the above-mentioned audio sub-carrier signal 16 is frequency-converted by the frequency converter 23 using the main carrier signal 20. The video signal 8 is AM-modulated by the AM modulator 22 on the main carrier signal 20. The AM signal and the output signal of the frequency converter are added by an adder 24 to generate an RF signal 10 of a predetermined TV broadcast channel.

The control data 13a input from an external control bus line (for example, Philips I ² C-BUS) is demodulated by the data demodulator 21 and becomes an actual control signal. To control the frequency division ratio N
1. Set to N2.

On the other hand, the VCO of the main carrier signal oscillation circuit 19
Generally, an LC resonance circuit is used for the 32 resonance circuits. The resonance frequency is represented by the following equation (3), where Lvco is the inductance of the coil and Cvco is the capacitance of the capacitor.

F0 = 1 / (2π × (Lvco × Cvco) ^1/2 ) (3) The resonance frequency of the resonance circuit is changed to set the main carrier signal 20 in an empty channel of the TV broadcast. Therefore, the capacitor is a variable capacitor Cvco, and the tuning voltage V applied to the variable capacitor Cvco is
By varying t, the capacitance is changed, and the resonance frequency is changed. In order to increase the capacitance change ratio of the variable capacitor Cvco, the tuning voltage Vt is generated from a high-voltage power supply (for example, 33 V) supplied to the high-voltage power supply terminal 39 separately from the normal power supply (for example, 5 V).

As shown in FIG. 11, the error signal 38 output from the filter 35 is input to the transistor Q1. This transistor Q1 is a common-emitter amplifier driven by a high-voltage power supply via a load resistor RL, and has a large amplification factor. The collector voltage of the transistor Q1 is used as the tuning voltage Vt as the variable capacitor Cvco.
Supplied to The error signal 38 is generated by the main carrier signal oscillation circuit 19 driven by a normal power supply (for example, 5 V). Therefore, the error signal 38 immediately after power-on is turned on.
The time difference between the power supply and the high-voltage power supply being in a steady state changes the tuning voltage Vt, and the frequency of the main carrier signal 20 becomes unstable. For example, immediately after the power is turned on, the error signal 3
If the time until the steady state of FIG. 8 is later than that of the high-voltage power supply, there is no voltage drop due to the load resistance RL. Therefore, the tuning voltage Vt is a high voltage,
The voltage gradually decreases as the error signal 38 rises, and stabilizes at a voltage corresponding to the set oscillation frequency fc of the main carrier signal 20. That is, the oscillation frequency of the main carrier signal 20 is high immediately after the power is turned on, and gradually decreases.

[0019]

However, the above configuration has the following problems. For example, when the VTR using the conventional RF modulator is set to the timer recording mode to receive the RF signal 2 of the TV broadcast, the RF signal 2 is not shown via the adder 11 as the RF signal 12 as it is. It has been sent to the TV receiver. When the timer set time comes and the VTR is turned on, an RF signal 10 having an unstable frequency is output from the RF modulator 5. The RF of the TV broadcast that the RF signal 10 is receiving
Since the signal is added to the signal 2, there is a problem that a large reception failure occurs when the fluctuating RF signal 10 becomes the same frequency as the RF signal 2.

In general, when the FM modulation system using a PLL circuit is adopted for the audio subcarrier signal oscillation circuit 15 and the audio signal 9 is FM-modulated by directly controlling the oscillation frequency of the VCO 26, the audio signal 9 generates a PLL. The reference signal 31 at the output of the frequency divider 30 is used so that the operation of the circuit is not affected.
Is set to a relatively low frequency. In order to eliminate the effect of lowering the frequency of the reference signal 31, the cutoff frequency of the filter 29 for attenuating and smoothing unnecessary components is reduced.

A general filter 29 used in a PLL circuit as shown in FIG. 10A includes a resistor R connected in series and a capacitor C connected in parallel. The phase comparison circuit 28 includes a series circuit including a phase comparator 28a and a charge / discharge circuit (hereinafter, referred to as a charge pump) 28b for charging / discharging the capacitor C of the filter 29. The cut-off frequency fcut of the filter 29 at this time is expressed by the following equation (4).

Fcut = 1 / (2πRC) (4) That is, in order to lower the cut-off frequency fcut, at least one of the capacitor C and the resistor R must be increased.

In the above case, the time from when the power supply is turned on to when it reaches the steady state can be represented by a time constant τ. The time constant τ is given by the following equation (5). τ = RC (5) That is, when the cutoff frequency fcut is reduced and the resistance R and the capacitor C are increased, the time constant τ also increases. That is, the time required for the output of the filter 29 to reach the steady state (phase-locked state) becomes longer. Therefore, the filter 29 affects the oscillation frequency of the VCO 26, and eventually, the time until the frequency of the audio sub-carrier signal 16 reaches the set frequency, that is, until the fluctuation of the frequency becomes small (hereinafter referred to as lock-in time). ) Becomes longer.

A general filter 29a used in a PLL circuit as shown in FIG. 10B includes at least a capacitor C connected in parallel. The filter operation is performed by charging and discharging the capacitor C. Assuming that only the capacitor C is considered for simplicity and the output signal current from the phase comparison circuit 28 is I, the output voltage Vout to the adder 25 is given by the following equation (6).

Vout = I / (2πfC) (6) In other words, even if the input current is the same, the output voltage increases as the frequency decreases, and the effect of reducing the frequency of the reference signal 31 is eliminated. In order to realize this, it is necessary to at least reduce the output signal current I from the phase comparison circuit 28 or increase the value of the capacitor C.

However, the time from a transient state such as immediately after power-on to a steady state is the charging and discharging time until the output voltage of the capacitor C reaches a predetermined voltage. Even if I is small,
Even if the value of the capacitor C is increased, the time becomes longer and the lock-in time becomes longer.

If the lock-in time of the audio sub-carrier signal is long, FM demodulation cannot be performed normally during that time, and the time during which the audio signal demodulated by a TV receiver or the like becomes abnormal becomes longer.

In the case of the PAL system and the SECAM system, since the RF signals 2 and 10 are in the UHF band, a switch is not suitable in terms of crosstalk, loss and cost, and the adder 11 adds the two signals. , Synthesis is essential. An object of the present invention is to provide a high-frequency signal generator, a video signal reproducing device, and a video signal recording / reproducing device which do not cause reception failure and output abnormal sound.

[0029]

To achieve the solution to the purpose the above-mentioned problems SUMMARY OF THE INVENTION, Oite high frequency signal generator of the present invention has taken the following means. The high-frequency signal generator according to the first aspect of the present invention receives the audio sub-carrier signal, the main carrier signal, and the video signal modulated by the audio signal,
A high-frequency encoder that converts a high frequency signal of a television broadcast, is input before SL RF signal, and a circuit breaker for interrupting the high-frequency signal when the first control signal is input, the stable frequency 1 When the reference signal is
And a first resistor connected in series and a first resistor connected in parallel.
In the first PLL circuit including the filter including one capacitor
Therefore, the main carrier signal phase-locked to the first reference signal
And supplies it to the high-frequency encoder
A main carrier signal oscillation circuit, the voice signal and a stable frequency
Number of second reference signals are input and connected at least in series.
Connected second resistor and a second capacitor connected in parallel.
A second PLL circuit including a
The signal is FM-modulated and phase-locked to the second reference signal.
Generating an audio sub-carrier signal and
An audio subcarrier signal oscillation circuit for supplying a signal to the
Connected in parallel to at least one of a resistor and the second resistor.
When the second control signal is input, both ends of the resistor
A short circuit for short-circuiting, the audio sub-carrier signal and the main
If at least one frequency of the carrier signal is unstable,
A tie for outputting the first control signal and the second control signal
A mining generator. Further, the high frequency
The coder modulates the video signal with the main carrier signal.
An AM modulator, and the main carrier for transmitting the audio subcarrier signal.
A frequency converter for performing frequency conversion by a wave signal;
Output signals of the M modulator and the frequency converter
And an adder for adding and outputting .

In the high-frequency signal generator according to the present invention, when the frequencies of the main carrier signal and the audio sub-carrier signal are unstable, the high-frequency signal is cut off by the circuit breaker in response to the first control signal. Therefore, the high-frequency signal in that case is not output. In addition, the second control
The first PLL circuit or the second P
Since the time constant of the filter of the LL circuit is reduced,
The capacitor of the PLL circuit to which the short circuit is connected is
Reduces the time required to reach the specified voltage,
The time until the time can be shortened. Therefore, the high
Wave signal of the main carrier signal and the audio sub-carrier signal
Shorten the time until the frequency becomes stable, and
It is possible to reduce the bad influence on the vehicle .

According to the second aspect of the present invention, there is provided a high-frequency signal generator.
The generator is an audio subcarrier signal modulated by the audio signal
And the main carrier signal and video signal are
High-frequency encoder that converts it into a high-frequency signal for broadcast and outputs it
And the high frequency signal is inputted, and the first control signal is inputted.
A circuit breaker that cuts off the high-frequency signal when the
A first reference signal having a high frequency is input to the first PLL circuit.
The main carrier phase-locked to the first reference signal by
A signal is generated and supplied to the high-frequency encoder.
A main carrier signal oscillation circuit,
The second reference signal having the wave number is input, and the second PLL circuit
Thus, the audio signal is FM-modulated and placed on the second reference signal.
Generating the phase synchronized voice subcarrier signal and
The oscillation frequency of the audio subcarrier signal supplied to the high-frequency encoder
Path and a small amount of the audio sub-carrier signal and the main carrier signal.
If at least one frequency is unstable, the first control signal
And a timing generator for outputting a second control signal.
I have. Further, the high-frequency encoder includes
An AM modulator whose signal AM modulates the main carrier signal;
The audio sub-carrier signal is frequency-divided by the main carrier signal.
A frequency converter for converting the number, the AM modulator and the frequency converter.
Adds the output signals of the wave number converters and outputs the sum.
A first PLL circuit and the second P circuit.
At least one of the LL circuits includes a charge / discharge circuit as an output part.
Including a phase comparison circuit and an output signal of the charge / discharge circuit.
When the second control signal is input, the charge / discharge cycle
The output current of the road is increased and output otherwise,
A current increasing circuit that outputs the output current of the discharge circuit as it is
Contains .

In the high-frequency signal generator according to the present invention, when the frequencies of the main carrier signal and the audio sub-carrier signal are unstable , the cutoff is performed in response to the first control signal.
In this case, the high-frequency signal is cut off by the
Is not output. In addition, the second control
The output current of the charge / discharge circuit increases in response to a signal.
And a capacitor of the PLL circuit having the current increasing circuit.
The time it takes for the sensor to reach the specified voltage,
Time to the initial state can be shortened. Therefore, before
The main carrier signal and the audio subcarrier of the high frequency signal
Reduce the time it takes for the signal frequency to stabilize,
It is possible to reduce a bad influence on the slave device .

[0033] Further, as set forth in claim 3, the timing
The generator has a stable frequency just after the power is turned on.
The output signal of the reference oscillator that generates the signal is counted and
Outputs the first control signal for a time until it reaches one reference value
And the time until the second reference value is reached.
Output a signal .

In the high-frequency signal generator according to the present invention, the frequency of the main carrier signal and the audio sub-carrier signal is
When the number is unstable, the output signal of the reference
Is easily detected by the event value .

[0035]

[0036]

[0037]

[0038]

[0039]

[0040]

[0041]

[0042]

[0043]

[0044]

[0045]

[0046]

[0047]

[0048]

[0049]

[0050]

[0051]

[0052]

[0053]

[0054]

[0055]

[0056]

Embodiments of the present invention will be described below with reference to the drawings. 8 to 10 are denoted by the same reference numerals, and different portions will be mainly described. (First Embodiment) FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention. FIGS. 2A, 2B, and 3 are diagrams showing a part of the circuit of the first embodiment.

As shown in FIG. 1, the RF signal 10 output from the RF encoder 14 is input to a circuit breaker 45, and the RF signal 10 a output from the circuit breaker 45 is input to an adder 11. The output signal of the reference oscillator 18 is input to the timing generator 46, and the cutoff control signal 47 is supplied to the breaker 45.

As shown in FIG. 2A, the timing generator 46 comprises a frequency divider (timer) 46a. Immediately after the power is turned on or in response to a user operation, the main carrier signal 20
Or, when the frequency of the audio subcarrier signal 16 changes and becomes a transient state (hereinafter, referred to as a case immediately after turning on the power),
The cutoff control signal 47 is output, and the circuit breaker 45 is in a cutoff state. In that case, the frequency divider 46a counts the output signal of the reference oscillator 18 and stops outputting the cutoff control signal 47 when the output signal reaches the reference value. When the output of the cutoff control signal 47 stops, the circuit breaker 45 becomes conductive. The time during which the circuit breaker 45 is in the cutoff state is set to be equal to or longer than the time during which the frequency of the RF signal 10 stabilizes at the set frequency (frequency of any TV channel selected by the user). The latter time is about several msec to several hundred msec. During this time, the reference value of the count is determined in advance so that the cutoff control signal 47 is generated.
Therefore, in the case immediately after the power is turned on or the like, the R while the frequency of the main carrier signal 20 or the audio sub-carrier signal 16 is fluctuating,
The F signal 10 is not output.

As shown in FIG. 2B, the timing generator 46 may be a PLL lock detector 46b. In this case, the lock detection signal 44a is input from the phase comparison circuit 34 of the main carrier oscillation circuit 19 to the PLL lock detector 46b. For example, immediately after the power is turned on, the main carrier signal 2
While 0 is fluctuating, the output signal of the phase comparison circuit 34 fluctuates greatly, and the PLL circuit is in the unlocked state.
If this output signal fluctuates greatly, it is determined that the PLL lock detector 46b is in the unlocked state (phase asynchronous state), and the cutoff control signal 47 is output to put the breaker 45 in the cutoff state.

The error signal 38 output from the filter 35 may be used instead of the lock detection signal 44a. In this case, when the amplitude of the error signal 38 is larger than the reference value set separately (phase asynchronous state), the PLL lock detector 46b outputs the cutoff control signal 47. In this case, the time when the frequency of the main carrier signal 20 becomes the set value corresponds to the time when the voltage across the capacitor C of the filter 35 becomes the predetermined voltage.

In the above embodiment, when the frequency of the main carrier signal 20 is unstable, for example, immediately after the power is turned on,
Since the RF signal 10 is not output by the circuit breaker 45 in response to the cutoff control signal 47, the R
The F signal 10a is an RF signal 2 of a TV broadcast from the antenna 1
Does not have a bad effect on

As shown in FIG. 3, the timing generator 46
May be a PLL lock detector 46c. In this case, the lock detection signal 42a is input from the phase comparison circuit 28 of the audio subcarrier signal oscillation circuit 15 to the PLL lock detector 46c. For example, immediately after the power is turned on, while the audio subcarrier signal 16 fluctuates, the output signal of the phase comparison circuit 28 fluctuates greatly, and the PLL circuit is in an unlocked state. If this output signal fluctuates greatly, the PLL
Assuming that the lock detector 46c is in the unlocked state (phase asynchronous state), it outputs the cutoff control signal 47,
5 is turned off. Further, the error signal 40 of the output of the filter 29 may be used instead of the lock detection signal 42a. In this case, when the amplitude of the error signal 40 becomes larger than a separately provided reference value, the PLL lock detector 46c outputs the cutoff control signal 47. In this case, the time when the frequency of the audio subcarrier signal 16 becomes the set value approximately corresponds to the time when the voltage of the capacitor of the filter 29 becomes the predetermined voltage.

In the above embodiment, when the frequency of the main carrier signal 20 or the audio sub-carrier signal 16 is unstable immediately after power-on or the like, the RF signal 10 is turned on by the circuit breaker 45 in response to the cut-off control signal 47. Is not output,
The RF signal 10a output from the RF module 5 is
It does not adversely affect the RF signal 2 of TV broadcast from TV. Therefore, a bad influence such as a reception failure on other TV receivers does not occur. The unstable state of the frequency is easily detected by the count of the output signal of the reference oscillator 18 and the lock detection signals 42a and 44a of the PLL circuit. (Second Embodiment) FIGS. 4A and 4B, FIG. 5A
(B) is a figure which shows a part of 2nd Embodiment. FIG.
The same reference numerals are given to the same parts as in FIGS. 1 to 3, and different parts are mainly shown.

A case where a short circuit 48 is connected in parallel with the resistor R of the filter 29 of the audio subcarrier signal oscillation circuit 15 shown in FIG. A short circuit control signal 49 output from the frequency divider 46 a of the timing generator 46 is connected to the short circuit 48. The output signal of the reference oscillator 18 is supplied to the frequency divider 46a.

For example, immediately after the power is turned on, the short circuit control signal 49 is input, and the short circuit 48 is in a short circuit state. That is, both ends of the resistor R are short-circuited, and the time constant of the filter 29 is small. As in the case of generating the cutoff control signal 47, the frequency divider 46a
Counts the output signal of the reference oscillator 18 and stops outputting the short-circuit control signal 49 when the output signal reaches the reference value. When the output of the short-circuit control signal 49 is stopped, the short-circuit 48 is opened. That is, the filter 29 includes the resistor R and the capacitor C
The normal operation is performed by and. Therefore, for example, immediately after the power is turned on, the charging current to the capacitor C is increased, and the time until the capacitor C is charged to the predetermined voltage is shortened. Can be shortened. The reference value of the count of the frequency divider 46a is set in advance to a value corresponding to a time when the frequency of the audio subcarrier signal 16 becomes a set value, that is, a time until the capacitor C is charged to a predetermined voltage. Keep it.

FIG. 4B shows a configuration for increasing the charge / discharge current from the phase comparison circuit 28 to the capacitor C included in the filter 29a. As shown in FIG. 4B, the current increase control signal 50 output from the frequency divider 46a of the timing generator 46 is used to increase the current increase inserted between the charge pump 28c and the filter 29a including at least the capacitor C. The signal is supplied to a circuit 28d. Divider 4
The output signal of the reference oscillator 18 is supplied to 6a.

For example, immediately after the power is turned on, a current increase control signal 50 is output, and the charge / discharge current from the charge pump 28c to the capacitor C is increased. That is, the time required for the voltage of the capacitor C to reach the predetermined voltage can be reduced. Similarly to the case of generating the cutoff control signal 47, the frequency divider 46a counts the output signal of the reference oscillator 18 and stops outputting the current increase control signal 50 when the output signal reaches the reference value. When the output of the current increase control signal 50 is stopped, the output current of the phase comparison circuit 28 becomes a normal value. Therefore, for example, immediately after the power is turned on, the charging current to the capacitor C is increased, and the time until the capacitor C is charged to the predetermined voltage is shortened. As a result, the time until the phase synchronization of the PLL circuit of the audio subcarrier oscillation circuit 15 is reached. Can be shortened. Note that the frequency divider 4
The count value of 6a is set in advance to a value corresponding to the time when the frequency of the audio subcarrier signal 16 becomes a set value, that is, the time until the capacitor C is charged to a predetermined voltage.

FIGS. 5A and 5B respectively show FIGS.
(A), the timing generator 4 of the embodiment of FIG.
6 shows a case where the PLL lock detector 6c is constituted by a PLL lock detector 46c as in FIG.

As shown in FIG. 5A, the phase comparison circuit 2
8 to the lock detection signal 42a (dotted line 42a in FIG. 1)
Is input to the PLL lock detector 46c. PLL
A short-circuit control signal 49 (dotted line 49 in FIG. 1) output from the lock detector 46c is connected to the short-circuit 48. If the output signal of the phase comparator 28 fluctuates greatly, the PLL
Assuming that the lock detector 46c is in the unlocked state (phase asynchronous state), it outputs the short-circuit control signal 49 to bring the short-circuit circuit 48 into the short-circuit state.

In the second embodiment shown in FIGS. 4A and 5A, when the frequency of the audio subcarrier signal 16 is unstable, for example, immediately after the power is turned on, etc. Since the time constant of the filter 29 of the PLL circuit is reduced by the short circuit 48, the time required for the capacitor C to reach a predetermined voltage can be shortened, and eventually the time required for the phase synchronization can be shortened.

FIG. 5B shows a case in which the charge / discharge current from the phase comparison circuit 28 to the capacitor C of the filter 29a is increased.
6c. As in FIG. 5A, the lock detection signal 42a is input from the phase comparison circuit 28 to the PLL circuit detector 46c. The current increase control signal 50 output from the PLL lock detector 46c is input to the current increase circuit 28d. When the output signal of the phase comparison circuit 28 fluctuates greatly, the PLL lock detector 46c outputs a current increase control signal 50 assuming that the PLL lock detector 46c is in the unlocked state (phase asynchronous state).
, The charge / discharge current to the capacitor C is increased.

In the second embodiment shown in FIGS. 4 (b) and 5 (b), when the frequency of the audio subcarrier signal 16 is unstable, such as immediately after power-on, etc., the current increase control signal 50
, The charge / discharge current from the phase comparison circuit 28 to the capacitor C is increased, so that the time required for the capacitor C to reach a predetermined voltage is shortened, and eventually the time required for the phase synchronization state can be shortened.

Accordingly, the time until the frequency of the carrier signal of the audio sub-carrier signal 16 becomes stable is shortened, and the audio signal abnormality does not occur when the TV broadcast is received. FIG. 6 and FIG.
5 shows a case where the first embodiment and the second embodiment shown in FIGS. 4A and 5A are combined. FIG.
(A), FIG. 3, and FIG. 4 (a), FIG. 5 (a) are denoted by the same reference numerals, and mainly different parts are shown.

As shown in FIG. 6, the output of the RF encoder 14 is supplied to a circuit breaker 45, and a short circuit 48 is connected in parallel with the resistor R of the filter 29 of the audio subcarrier signal oscillation circuit 15. In this case, the frequency divider 46d of the output signal of the reference oscillator 18, which is the timing generator 46, is shared. Although the cutoff control signal 47 and the short circuit control signal 49 are output independently at different timings, the cutoff control signal 47 and the short circuit control signal 49 may be signals having the same timing.

As shown in FIG. 7, the PLL lock detector 46e may be shared with the timing generator 46.
The lock detection signal 44a (dotted line 44a in FIG. 1) of the phase comparison circuit 34 of the main carrier signal oscillation circuit 19 or the error signal 38 of the output of the filter 35 is output to the PLL lock detector 46.
e may be input. The main carrier signal oscillation circuit 19
The short circuit 48 may be connected in parallel to the resistor R connected in series to the filter 35 circuit. In this case, the short-circuit control signal 49 (dotted line 49 in FIG. 1)
Is supplied to the short circuit 48. Note that the cutoff control signal 47 and the short circuit control signal 49 may be delayed. Note that R
The F encoder 14 converts the video signal 8 and the audio subcarrier signal 1
A configuration in which AM modulation is performed after adding 6 may be used.

In the above case, since the timing generator 46 is shared, the circuit scale does not increase. When the first and second embodiments are combined as shown in FIGS. 6 and 7, the audio subcarrier signal oscillation circuit 15 may be of a type that increases the charge / discharge current to the capacitor C of the filter 29. In this case, the timing generator 46 that outputs the cutoff control signal 47 and the current increase control signal 50 is shared.

In the case where the current increasing circuit 28d is not used, that is, in the case of FIGS. 3, 4 (a), 5 (a), 6 and 7, the phase comparison circuit 28 of the PLL circuit does not require a charge pump. An analog phase comparison circuit may be used. In addition, P
The phase comparison circuit 34 of the LL circuit may be a phase comparison circuit with a charge pump or a phase comparison circuit without a shardy pump.

Note that the RF modulator 5 may include an adder 11. Further, the video signal reproducing device may be a video signal recording and reproducing device including a video signal recording device. That is, in the case of recording, the signal processing circuit 7 restores the video signal 8 and the audio signal 9 from the RF signal 2 of the television broadcast, converts the signals into recording signals, and outputs the recording signals. Record the signal.

[0079]

As described above, according to the present invention, it is possible to provide a high-frequency signal generator, a video signal reproducing apparatus, and a video signal recording / reproducing apparatus which do not cause reception trouble and do not output abnormal sound.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a video signal reproducing device according to first and second embodiments of the present invention.

FIG. 2 is a diagram illustrating an RF modulator according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an RF modulator according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating an RF modulator according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating an RF modulator according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an RF modulator according to one embodiment of the present invention.

FIG. 7 illustrates an RF modulator according to one embodiment of the present invention.

FIG. 8 is a diagram showing a circuit configuration of a conventional video signal reproducing device.

FIG. 9 is a diagram showing a circuit configuration according to a conventional RF modulator.

FIG. 10 illustrates a circuit configuration of a conventional RF modulator.

FIG. 11 is a diagram illustrating a circuit configuration according to a conventional RF modulator.

[Explanation of symbols]

 Reference Signs List 11: adder, 14: RF encoder, 15: audio sub-carrier signal oscillation circuit, 16: audio sub-carrier signal, 17: crystal oscillator, 18: reference oscillator, 19: main carrier signal oscillation circuit, 20: main carrier signal 21: Data demodulator, 22: AM modulator, 23: Frequency converter, 24: Adder, 25: Adder, 26: VCO 28, 34: Phase comparator circuit, 28a: Phase comparator, 28b, 28c ... Charge pump, 28d: current increasing circuit, 29, 29a: filter, 45: breaker, 46: timing generator, 46a, 46d: frequency divider (timer), 46b, 46c, 46e: PLL lock detector 47: shutoff Control signal, 48: short circuit, 49: short circuit control signal, 50: current increase control signal.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-18878 (JP, A) JP-A-3-204286 (JP, A) JP-A-62-216528 (JP, A) JP-A-7- 30416 (JP, A) JP-A-56-78236 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03L ⁷ /06-7/23

Claims (3)

(57) [Claims] 1. A sound modulated by the audio signal sub-carrier signal and the main carrier signal and a video signal is input, a high-frequency encoder that converts a high frequency signal of a television broadcast, prior SL RF signal is input a breaker first control signal to shut off the high-frequency signal when it is input, the first reference signal of a stable frequency is input, at least linear
A first resistor connected in a column and a first resistor connected in parallel.
By a first PLL circuit including a filter including a capacitor
Generating the main carrier signal synchronized in phase with the first reference signal;
Main transfer for producing and supplying to the high frequency encoder
Wave signal oscillating circuit, the audio signal and a second reference signal having a stable frequency are input.
And at least a second resistor connected in series and a second resistor connected in parallel.
A second P including a filter including a second capacitor
The audio signal is FM-modulated by the LL circuit and the second
Generating the audio subcarrier signal phase-synchronized with a reference signal;
Audio sub-carrier to be supplied to the high-frequency encoder
Wave signal oscillation circuit , parallel to at least one of the first resistor and the second resistor
And when the second control signal is input, the resistance
And a short circuit that short-circuits both ends of the audio sub-carrier signal and the main carrier signal.
If one of the frequencies is unstable, the first control signal and
A timing generator for outputting the second control signal.
In addition , the high-frequency encoder includes an AM converter that modulates the video signal by AM on the main carrier signal.
A frequency controller, and the audio subcarrier signal is frequency-divided by the main carrier signal.
Frequency converter for performing number conversion , and respective outputs of the AM modulator and the frequency converter
A high-frequency signal generator, comprising: an adder for adding and outputting a signal. 2. An audio subcarrier modulated by an audio signal.
Signal, main carrier signal and video signal
High-frequency signal that is converted to a high-frequency signal
A coder, the high-frequency signal is input, and a first control signal is input.
And a circuit breaker for cutting off the high-frequency signal, a first reference signal having a stable frequency, and a first PLL.
The main carrier phase-synchronized with the first reference signal by a circuit;
A transmission signal is generated and supplied to the high-frequency encoder.
A main carrier signal oscillating circuit to be supplied and the audio signal and a second reference signal having a stable frequency.
And the audio signal is FM-modulated by the second PLL circuit.
The audio sub-carrier phase-locked to the second reference signal
A signal is generated and supplied to the high-frequency encoder.
Audio sub-carrier signal oscillation circuit, and at least the audio sub-carrier signal and the main carrier signal.
If one of the frequencies is unstable, the first control signal and
A timing generator that outputs a second control signal , wherein the high-frequency encoder is configured to perform an AM conversion on the video signal to AM modulate the main carrier signal.
A frequency controller, and the audio subcarrier signal is frequency-divided by the main carrier signal.
Frequency converter for performing number conversion , and respective outputs of the AM modulator and the frequency converter
An adder for adding and outputting a signal , wherein a small number of the first PLL circuit and the second PLL circuit are provided.
At least one is a phase comparison circuit that includes a charge / discharge circuit in the output section.
And an output signal of the charge / discharge circuit,
When a control signal is input, the output current of the charge / discharge circuit is
Increase and output, otherwise output of the charge / discharge circuit
And a current increasing circuit that outputs the current as it is.
And a high frequency signal generator. 3. The timing generator is operated immediately after power is turned on.
The output of the reference oscillator, which produces a stable frequency signal.
Time before the force signal is counted and reaches the first reference value
The first control signal is output until the second reference value is reached.
Outputting the second control signal for a period of time
The high-frequency signal generator according to claim 1 .